prompt
stringlengths 162
4.26M
| response
stringlengths 109
5.16M
|
|---|---|
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_47 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied | module IssueSlot_47( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s2 :
input clock : Clock
input reset : Reset
output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>}
node default = gt(io.prv, UInt<1>(0h1))
wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmp0_WIRE.mask, UInt<32>(0h0)
connect _pmp0_WIRE.addr, UInt<30>(0h0)
connect _pmp0_WIRE.cfg.r, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.w, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.x, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.a, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.res, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.l, UInt<1>(0h0)
wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp0, _pmp0_WIRE
connect pmp0.cfg.r, default
connect pmp0.cfg.w, default
connect pmp0.cfg.x, default
node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1)
node _res_hit_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_T_2 = not(_res_hit_T_1)
node _res_hit_T_3 = or(_res_hit_T_2, UInt<2>(0h3))
node _res_hit_T_4 = not(_res_hit_T_3)
node _res_hit_T_5 = xor(io.addr, _res_hit_T_4)
node _res_hit_T_6 = not(io.pmp[7].mask)
node _res_hit_T_7 = and(_res_hit_T_5, _res_hit_T_6)
node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0))
node _res_hit_T_9 = bits(io.pmp[7].cfg.a, 0, 0)
node _res_hit_T_10 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_11 = bits(_res_hit_T_10, 1, 0)
node _res_hit_T_12 = not(_res_hit_T_11)
node _res_hit_T_13 = shl(io.pmp[6].addr, 2)
node _res_hit_T_14 = not(_res_hit_T_13)
node _res_hit_T_15 = or(_res_hit_T_14, UInt<2>(0h3))
node _res_hit_T_16 = not(_res_hit_T_15)
node _res_hit_T_17 = lt(io.addr, _res_hit_T_16)
node _res_hit_T_18 = eq(_res_hit_T_17, UInt<1>(0h0))
node _res_hit_T_19 = shl(io.pmp[7].addr, 2)
node _res_hit_T_20 = not(_res_hit_T_19)
node _res_hit_T_21 = or(_res_hit_T_20, UInt<2>(0h3))
node _res_hit_T_22 = not(_res_hit_T_21)
node _res_hit_T_23 = lt(io.addr, _res_hit_T_22)
node _res_hit_T_24 = and(_res_hit_T_18, _res_hit_T_23)
node _res_hit_T_25 = and(_res_hit_T_9, _res_hit_T_24)
node res_hit = mux(_res_hit_T, _res_hit_T_8, _res_hit_T_25)
node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0))
node res_ignore = and(default, _res_ignore_T)
node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0))
node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1))
node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r)
node _res_T_6 = eq(_res_T_5, UInt<1>(0h0))
node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r)
node _res_T_8 = eq(_res_T_7, UInt<1>(0h1))
node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r)
node _res_T_10 = eq(_res_T_9, UInt<2>(0h3))
node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r)
node _res_T_12 = eq(_res_T_11, UInt<3>(0h4))
node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r)
node _res_T_14 = eq(_res_T_13, UInt<3>(0h5))
node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r)
node _res_T_16 = eq(_res_T_15, UInt<3>(0h7))
node _res_T_17 = eq(res_ignore, UInt<1>(0h0))
node _res_T_18 = and(_res_T_17, res_hit)
node _res_T_19 = and(_res_T_18, UInt<1>(0h1))
node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_21 = and(_res_T_19, _res_T_20)
node _res_T_22 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_23 = and(_res_T_22, UInt<1>(0h1))
node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_25 = and(_res_T_23, _res_T_24)
node _res_T_26 = eq(res_ignore, UInt<1>(0h0))
node _res_T_27 = and(_res_T_26, res_hit)
node _res_T_28 = and(_res_T_27, UInt<1>(0h1))
node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_30 = and(_res_T_28, _res_T_29)
node _res_T_31 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_32 = and(_res_T_31, UInt<1>(0h1))
node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_34 = and(_res_T_32, _res_T_33)
node _res_T_35 = eq(res_ignore, UInt<1>(0h0))
node _res_T_36 = and(_res_T_35, res_hit)
node _res_T_37 = and(_res_T_36, UInt<1>(0h1))
node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_39 = and(_res_T_37, _res_T_38)
node _res_T_40 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_41 = and(_res_T_40, UInt<1>(0h1))
node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_43 = and(_res_T_41, _res_T_42)
wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur, io.pmp[7]
node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore)
node _res_cur_cfg_r_T_1 = and(UInt<1>(0h1), _res_cur_cfg_r_T)
connect res_cur.cfg.r, _res_cur_cfg_r_T_1
node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore)
node _res_cur_cfg_w_T_1 = and(UInt<1>(0h1), _res_cur_cfg_w_T)
connect res_cur.cfg.w, _res_cur_cfg_w_T_1
node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore)
node _res_cur_cfg_x_T_1 = and(UInt<1>(0h1), _res_cur_cfg_x_T)
connect res_cur.cfg.x, _res_cur_cfg_x_T_1
node _res_T_44 = mux(res_hit, res_cur, pmp0)
node _res_hit_T_26 = bits(io.pmp[6].cfg.a, 1, 1)
node _res_hit_T_27 = shl(io.pmp[6].addr, 2)
node _res_hit_T_28 = not(_res_hit_T_27)
node _res_hit_T_29 = or(_res_hit_T_28, UInt<2>(0h3))
node _res_hit_T_30 = not(_res_hit_T_29)
node _res_hit_T_31 = xor(io.addr, _res_hit_T_30)
node _res_hit_T_32 = not(io.pmp[6].mask)
node _res_hit_T_33 = and(_res_hit_T_31, _res_hit_T_32)
node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0))
node _res_hit_T_35 = bits(io.pmp[6].cfg.a, 0, 0)
node _res_hit_T_36 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_37 = bits(_res_hit_T_36, 1, 0)
node _res_hit_T_38 = not(_res_hit_T_37)
node _res_hit_T_39 = shl(io.pmp[5].addr, 2)
node _res_hit_T_40 = not(_res_hit_T_39)
node _res_hit_T_41 = or(_res_hit_T_40, UInt<2>(0h3))
node _res_hit_T_42 = not(_res_hit_T_41)
node _res_hit_T_43 = lt(io.addr, _res_hit_T_42)
node _res_hit_T_44 = eq(_res_hit_T_43, UInt<1>(0h0))
node _res_hit_T_45 = shl(io.pmp[6].addr, 2)
node _res_hit_T_46 = not(_res_hit_T_45)
node _res_hit_T_47 = or(_res_hit_T_46, UInt<2>(0h3))
node _res_hit_T_48 = not(_res_hit_T_47)
node _res_hit_T_49 = lt(io.addr, _res_hit_T_48)
node _res_hit_T_50 = and(_res_hit_T_44, _res_hit_T_49)
node _res_hit_T_51 = and(_res_hit_T_35, _res_hit_T_50)
node res_hit_1 = mux(_res_hit_T_26, _res_hit_T_34, _res_hit_T_51)
node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0))
node res_ignore_1 = and(default, _res_ignore_T_1)
node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0))
node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1))
node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r)
node _res_T_51 = eq(_res_T_50, UInt<1>(0h0))
node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r)
node _res_T_53 = eq(_res_T_52, UInt<1>(0h1))
node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r)
node _res_T_55 = eq(_res_T_54, UInt<2>(0h3))
node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r)
node _res_T_57 = eq(_res_T_56, UInt<3>(0h4))
node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r)
node _res_T_59 = eq(_res_T_58, UInt<3>(0h5))
node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r)
node _res_T_61 = eq(_res_T_60, UInt<3>(0h7))
node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_63 = and(_res_T_62, res_hit_1)
node _res_T_64 = and(_res_T_63, UInt<1>(0h1))
node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_66 = and(_res_T_64, _res_T_65)
node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_68 = and(_res_T_67, UInt<1>(0h1))
node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_70 = and(_res_T_68, _res_T_69)
node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_72 = and(_res_T_71, res_hit_1)
node _res_T_73 = and(_res_T_72, UInt<1>(0h1))
node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_75 = and(_res_T_73, _res_T_74)
node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_77 = and(_res_T_76, UInt<1>(0h1))
node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_79 = and(_res_T_77, _res_T_78)
node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_81 = and(_res_T_80, res_hit_1)
node _res_T_82 = and(_res_T_81, UInt<1>(0h1))
node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_84 = and(_res_T_82, _res_T_83)
node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_86 = and(_res_T_85, UInt<1>(0h1))
node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_88 = and(_res_T_86, _res_T_87)
wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_1, io.pmp[6]
node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1)
node _res_cur_cfg_r_T_3 = and(UInt<1>(0h1), _res_cur_cfg_r_T_2)
connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3
node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1)
node _res_cur_cfg_w_T_3 = and(UInt<1>(0h1), _res_cur_cfg_w_T_2)
connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3
node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1)
node _res_cur_cfg_x_T_3 = and(UInt<1>(0h1), _res_cur_cfg_x_T_2)
connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3
node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44)
node _res_hit_T_52 = bits(io.pmp[5].cfg.a, 1, 1)
node _res_hit_T_53 = shl(io.pmp[5].addr, 2)
node _res_hit_T_54 = not(_res_hit_T_53)
node _res_hit_T_55 = or(_res_hit_T_54, UInt<2>(0h3))
node _res_hit_T_56 = not(_res_hit_T_55)
node _res_hit_T_57 = xor(io.addr, _res_hit_T_56)
node _res_hit_T_58 = not(io.pmp[5].mask)
node _res_hit_T_59 = and(_res_hit_T_57, _res_hit_T_58)
node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0))
node _res_hit_T_61 = bits(io.pmp[5].cfg.a, 0, 0)
node _res_hit_T_62 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_63 = bits(_res_hit_T_62, 1, 0)
node _res_hit_T_64 = not(_res_hit_T_63)
node _res_hit_T_65 = shl(io.pmp[4].addr, 2)
node _res_hit_T_66 = not(_res_hit_T_65)
node _res_hit_T_67 = or(_res_hit_T_66, UInt<2>(0h3))
node _res_hit_T_68 = not(_res_hit_T_67)
node _res_hit_T_69 = lt(io.addr, _res_hit_T_68)
node _res_hit_T_70 = eq(_res_hit_T_69, UInt<1>(0h0))
node _res_hit_T_71 = shl(io.pmp[5].addr, 2)
node _res_hit_T_72 = not(_res_hit_T_71)
node _res_hit_T_73 = or(_res_hit_T_72, UInt<2>(0h3))
node _res_hit_T_74 = not(_res_hit_T_73)
node _res_hit_T_75 = lt(io.addr, _res_hit_T_74)
node _res_hit_T_76 = and(_res_hit_T_70, _res_hit_T_75)
node _res_hit_T_77 = and(_res_hit_T_61, _res_hit_T_76)
node res_hit_2 = mux(_res_hit_T_52, _res_hit_T_60, _res_hit_T_77)
node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0))
node res_ignore_2 = and(default, _res_ignore_T_2)
node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0))
node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1))
node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r)
node _res_T_96 = eq(_res_T_95, UInt<1>(0h0))
node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r)
node _res_T_98 = eq(_res_T_97, UInt<1>(0h1))
node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r)
node _res_T_100 = eq(_res_T_99, UInt<2>(0h3))
node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r)
node _res_T_102 = eq(_res_T_101, UInt<3>(0h4))
node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r)
node _res_T_104 = eq(_res_T_103, UInt<3>(0h5))
node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r)
node _res_T_106 = eq(_res_T_105, UInt<3>(0h7))
node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_108 = and(_res_T_107, res_hit_2)
node _res_T_109 = and(_res_T_108, UInt<1>(0h1))
node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_111 = and(_res_T_109, _res_T_110)
node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_113 = and(_res_T_112, UInt<1>(0h1))
node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_115 = and(_res_T_113, _res_T_114)
node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_117 = and(_res_T_116, res_hit_2)
node _res_T_118 = and(_res_T_117, UInt<1>(0h1))
node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_120 = and(_res_T_118, _res_T_119)
node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_122 = and(_res_T_121, UInt<1>(0h1))
node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_124 = and(_res_T_122, _res_T_123)
node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_126 = and(_res_T_125, res_hit_2)
node _res_T_127 = and(_res_T_126, UInt<1>(0h1))
node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_129 = and(_res_T_127, _res_T_128)
node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_131 = and(_res_T_130, UInt<1>(0h1))
node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_133 = and(_res_T_131, _res_T_132)
wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_2, io.pmp[5]
node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2)
node _res_cur_cfg_r_T_5 = and(UInt<1>(0h1), _res_cur_cfg_r_T_4)
connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5
node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2)
node _res_cur_cfg_w_T_5 = and(UInt<1>(0h1), _res_cur_cfg_w_T_4)
connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5
node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2)
node _res_cur_cfg_x_T_5 = and(UInt<1>(0h1), _res_cur_cfg_x_T_4)
connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5
node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89)
node _res_hit_T_78 = bits(io.pmp[4].cfg.a, 1, 1)
node _res_hit_T_79 = shl(io.pmp[4].addr, 2)
node _res_hit_T_80 = not(_res_hit_T_79)
node _res_hit_T_81 = or(_res_hit_T_80, UInt<2>(0h3))
node _res_hit_T_82 = not(_res_hit_T_81)
node _res_hit_T_83 = xor(io.addr, _res_hit_T_82)
node _res_hit_T_84 = not(io.pmp[4].mask)
node _res_hit_T_85 = and(_res_hit_T_83, _res_hit_T_84)
node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0))
node _res_hit_T_87 = bits(io.pmp[4].cfg.a, 0, 0)
node _res_hit_T_88 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_89 = bits(_res_hit_T_88, 1, 0)
node _res_hit_T_90 = not(_res_hit_T_89)
node _res_hit_T_91 = shl(io.pmp[3].addr, 2)
node _res_hit_T_92 = not(_res_hit_T_91)
node _res_hit_T_93 = or(_res_hit_T_92, UInt<2>(0h3))
node _res_hit_T_94 = not(_res_hit_T_93)
node _res_hit_T_95 = lt(io.addr, _res_hit_T_94)
node _res_hit_T_96 = eq(_res_hit_T_95, UInt<1>(0h0))
node _res_hit_T_97 = shl(io.pmp[4].addr, 2)
node _res_hit_T_98 = not(_res_hit_T_97)
node _res_hit_T_99 = or(_res_hit_T_98, UInt<2>(0h3))
node _res_hit_T_100 = not(_res_hit_T_99)
node _res_hit_T_101 = lt(io.addr, _res_hit_T_100)
node _res_hit_T_102 = and(_res_hit_T_96, _res_hit_T_101)
node _res_hit_T_103 = and(_res_hit_T_87, _res_hit_T_102)
node res_hit_3 = mux(_res_hit_T_78, _res_hit_T_86, _res_hit_T_103)
node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0))
node res_ignore_3 = and(default, _res_ignore_T_3)
node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0))
node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1))
node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r)
node _res_T_141 = eq(_res_T_140, UInt<1>(0h0))
node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r)
node _res_T_143 = eq(_res_T_142, UInt<1>(0h1))
node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r)
node _res_T_145 = eq(_res_T_144, UInt<2>(0h3))
node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r)
node _res_T_147 = eq(_res_T_146, UInt<3>(0h4))
node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r)
node _res_T_149 = eq(_res_T_148, UInt<3>(0h5))
node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r)
node _res_T_151 = eq(_res_T_150, UInt<3>(0h7))
node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_153 = and(_res_T_152, res_hit_3)
node _res_T_154 = and(_res_T_153, UInt<1>(0h1))
node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_156 = and(_res_T_154, _res_T_155)
node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_158 = and(_res_T_157, UInt<1>(0h1))
node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_160 = and(_res_T_158, _res_T_159)
node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_162 = and(_res_T_161, res_hit_3)
node _res_T_163 = and(_res_T_162, UInt<1>(0h1))
node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_165 = and(_res_T_163, _res_T_164)
node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_167 = and(_res_T_166, UInt<1>(0h1))
node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_169 = and(_res_T_167, _res_T_168)
node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_171 = and(_res_T_170, res_hit_3)
node _res_T_172 = and(_res_T_171, UInt<1>(0h1))
node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_174 = and(_res_T_172, _res_T_173)
node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_176 = and(_res_T_175, UInt<1>(0h1))
node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_178 = and(_res_T_176, _res_T_177)
wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_3, io.pmp[4]
node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3)
node _res_cur_cfg_r_T_7 = and(UInt<1>(0h1), _res_cur_cfg_r_T_6)
connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7
node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3)
node _res_cur_cfg_w_T_7 = and(UInt<1>(0h1), _res_cur_cfg_w_T_6)
connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7
node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3)
node _res_cur_cfg_x_T_7 = and(UInt<1>(0h1), _res_cur_cfg_x_T_6)
connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7
node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134)
node _res_hit_T_104 = bits(io.pmp[3].cfg.a, 1, 1)
node _res_hit_T_105 = shl(io.pmp[3].addr, 2)
node _res_hit_T_106 = not(_res_hit_T_105)
node _res_hit_T_107 = or(_res_hit_T_106, UInt<2>(0h3))
node _res_hit_T_108 = not(_res_hit_T_107)
node _res_hit_T_109 = xor(io.addr, _res_hit_T_108)
node _res_hit_T_110 = not(io.pmp[3].mask)
node _res_hit_T_111 = and(_res_hit_T_109, _res_hit_T_110)
node _res_hit_T_112 = eq(_res_hit_T_111, UInt<1>(0h0))
node _res_hit_T_113 = bits(io.pmp[3].cfg.a, 0, 0)
node _res_hit_T_114 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_115 = bits(_res_hit_T_114, 1, 0)
node _res_hit_T_116 = not(_res_hit_T_115)
node _res_hit_T_117 = shl(io.pmp[2].addr, 2)
node _res_hit_T_118 = not(_res_hit_T_117)
node _res_hit_T_119 = or(_res_hit_T_118, UInt<2>(0h3))
node _res_hit_T_120 = not(_res_hit_T_119)
node _res_hit_T_121 = lt(io.addr, _res_hit_T_120)
node _res_hit_T_122 = eq(_res_hit_T_121, UInt<1>(0h0))
node _res_hit_T_123 = shl(io.pmp[3].addr, 2)
node _res_hit_T_124 = not(_res_hit_T_123)
node _res_hit_T_125 = or(_res_hit_T_124, UInt<2>(0h3))
node _res_hit_T_126 = not(_res_hit_T_125)
node _res_hit_T_127 = lt(io.addr, _res_hit_T_126)
node _res_hit_T_128 = and(_res_hit_T_122, _res_hit_T_127)
node _res_hit_T_129 = and(_res_hit_T_113, _res_hit_T_128)
node res_hit_4 = mux(_res_hit_T_104, _res_hit_T_112, _res_hit_T_129)
node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0))
node res_ignore_4 = and(default, _res_ignore_T_4)
node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0))
node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1))
node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r)
node _res_T_186 = eq(_res_T_185, UInt<1>(0h0))
node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r)
node _res_T_188 = eq(_res_T_187, UInt<1>(0h1))
node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r)
node _res_T_190 = eq(_res_T_189, UInt<2>(0h3))
node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r)
node _res_T_192 = eq(_res_T_191, UInt<3>(0h4))
node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r)
node _res_T_194 = eq(_res_T_193, UInt<3>(0h5))
node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r)
node _res_T_196 = eq(_res_T_195, UInt<3>(0h7))
node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_198 = and(_res_T_197, res_hit_4)
node _res_T_199 = and(_res_T_198, UInt<1>(0h1))
node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_201 = and(_res_T_199, _res_T_200)
node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_203 = and(_res_T_202, UInt<1>(0h1))
node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_205 = and(_res_T_203, _res_T_204)
node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_207 = and(_res_T_206, res_hit_4)
node _res_T_208 = and(_res_T_207, UInt<1>(0h1))
node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_210 = and(_res_T_208, _res_T_209)
node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_212 = and(_res_T_211, UInt<1>(0h1))
node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_214 = and(_res_T_212, _res_T_213)
node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_216 = and(_res_T_215, res_hit_4)
node _res_T_217 = and(_res_T_216, UInt<1>(0h1))
node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_219 = and(_res_T_217, _res_T_218)
node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_221 = and(_res_T_220, UInt<1>(0h1))
node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_223 = and(_res_T_221, _res_T_222)
wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_4, io.pmp[3]
node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4)
node _res_cur_cfg_r_T_9 = and(UInt<1>(0h1), _res_cur_cfg_r_T_8)
connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9
node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4)
node _res_cur_cfg_w_T_9 = and(UInt<1>(0h1), _res_cur_cfg_w_T_8)
connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9
node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4)
node _res_cur_cfg_x_T_9 = and(UInt<1>(0h1), _res_cur_cfg_x_T_8)
connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9
node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179)
node _res_hit_T_130 = bits(io.pmp[2].cfg.a, 1, 1)
node _res_hit_T_131 = shl(io.pmp[2].addr, 2)
node _res_hit_T_132 = not(_res_hit_T_131)
node _res_hit_T_133 = or(_res_hit_T_132, UInt<2>(0h3))
node _res_hit_T_134 = not(_res_hit_T_133)
node _res_hit_T_135 = xor(io.addr, _res_hit_T_134)
node _res_hit_T_136 = not(io.pmp[2].mask)
node _res_hit_T_137 = and(_res_hit_T_135, _res_hit_T_136)
node _res_hit_T_138 = eq(_res_hit_T_137, UInt<1>(0h0))
node _res_hit_T_139 = bits(io.pmp[2].cfg.a, 0, 0)
node _res_hit_T_140 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_141 = bits(_res_hit_T_140, 1, 0)
node _res_hit_T_142 = not(_res_hit_T_141)
node _res_hit_T_143 = shl(io.pmp[1].addr, 2)
node _res_hit_T_144 = not(_res_hit_T_143)
node _res_hit_T_145 = or(_res_hit_T_144, UInt<2>(0h3))
node _res_hit_T_146 = not(_res_hit_T_145)
node _res_hit_T_147 = lt(io.addr, _res_hit_T_146)
node _res_hit_T_148 = eq(_res_hit_T_147, UInt<1>(0h0))
node _res_hit_T_149 = shl(io.pmp[2].addr, 2)
node _res_hit_T_150 = not(_res_hit_T_149)
node _res_hit_T_151 = or(_res_hit_T_150, UInt<2>(0h3))
node _res_hit_T_152 = not(_res_hit_T_151)
node _res_hit_T_153 = lt(io.addr, _res_hit_T_152)
node _res_hit_T_154 = and(_res_hit_T_148, _res_hit_T_153)
node _res_hit_T_155 = and(_res_hit_T_139, _res_hit_T_154)
node res_hit_5 = mux(_res_hit_T_130, _res_hit_T_138, _res_hit_T_155)
node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0))
node res_ignore_5 = and(default, _res_ignore_T_5)
node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0))
node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1))
node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r)
node _res_T_231 = eq(_res_T_230, UInt<1>(0h0))
node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r)
node _res_T_233 = eq(_res_T_232, UInt<1>(0h1))
node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r)
node _res_T_235 = eq(_res_T_234, UInt<2>(0h3))
node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r)
node _res_T_237 = eq(_res_T_236, UInt<3>(0h4))
node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r)
node _res_T_239 = eq(_res_T_238, UInt<3>(0h5))
node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r)
node _res_T_241 = eq(_res_T_240, UInt<3>(0h7))
node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_243 = and(_res_T_242, res_hit_5)
node _res_T_244 = and(_res_T_243, UInt<1>(0h1))
node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_246 = and(_res_T_244, _res_T_245)
node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_248 = and(_res_T_247, UInt<1>(0h1))
node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_250 = and(_res_T_248, _res_T_249)
node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_252 = and(_res_T_251, res_hit_5)
node _res_T_253 = and(_res_T_252, UInt<1>(0h1))
node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_255 = and(_res_T_253, _res_T_254)
node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_257 = and(_res_T_256, UInt<1>(0h1))
node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_259 = and(_res_T_257, _res_T_258)
node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_261 = and(_res_T_260, res_hit_5)
node _res_T_262 = and(_res_T_261, UInt<1>(0h1))
node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_264 = and(_res_T_262, _res_T_263)
node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_266 = and(_res_T_265, UInt<1>(0h1))
node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_268 = and(_res_T_266, _res_T_267)
wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_5, io.pmp[2]
node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5)
node _res_cur_cfg_r_T_11 = and(UInt<1>(0h1), _res_cur_cfg_r_T_10)
connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11
node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5)
node _res_cur_cfg_w_T_11 = and(UInt<1>(0h1), _res_cur_cfg_w_T_10)
connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11
node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5)
node _res_cur_cfg_x_T_11 = and(UInt<1>(0h1), _res_cur_cfg_x_T_10)
connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11
node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224)
node _res_hit_T_156 = bits(io.pmp[1].cfg.a, 1, 1)
node _res_hit_T_157 = shl(io.pmp[1].addr, 2)
node _res_hit_T_158 = not(_res_hit_T_157)
node _res_hit_T_159 = or(_res_hit_T_158, UInt<2>(0h3))
node _res_hit_T_160 = not(_res_hit_T_159)
node _res_hit_T_161 = xor(io.addr, _res_hit_T_160)
node _res_hit_T_162 = not(io.pmp[1].mask)
node _res_hit_T_163 = and(_res_hit_T_161, _res_hit_T_162)
node _res_hit_T_164 = eq(_res_hit_T_163, UInt<1>(0h0))
node _res_hit_T_165 = bits(io.pmp[1].cfg.a, 0, 0)
node _res_hit_T_166 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_167 = bits(_res_hit_T_166, 1, 0)
node _res_hit_T_168 = not(_res_hit_T_167)
node _res_hit_T_169 = shl(io.pmp[0].addr, 2)
node _res_hit_T_170 = not(_res_hit_T_169)
node _res_hit_T_171 = or(_res_hit_T_170, UInt<2>(0h3))
node _res_hit_T_172 = not(_res_hit_T_171)
node _res_hit_T_173 = lt(io.addr, _res_hit_T_172)
node _res_hit_T_174 = eq(_res_hit_T_173, UInt<1>(0h0))
node _res_hit_T_175 = shl(io.pmp[1].addr, 2)
node _res_hit_T_176 = not(_res_hit_T_175)
node _res_hit_T_177 = or(_res_hit_T_176, UInt<2>(0h3))
node _res_hit_T_178 = not(_res_hit_T_177)
node _res_hit_T_179 = lt(io.addr, _res_hit_T_178)
node _res_hit_T_180 = and(_res_hit_T_174, _res_hit_T_179)
node _res_hit_T_181 = and(_res_hit_T_165, _res_hit_T_180)
node res_hit_6 = mux(_res_hit_T_156, _res_hit_T_164, _res_hit_T_181)
node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0))
node res_ignore_6 = and(default, _res_ignore_T_6)
node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0))
node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1))
node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r)
node _res_T_276 = eq(_res_T_275, UInt<1>(0h0))
node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r)
node _res_T_278 = eq(_res_T_277, UInt<1>(0h1))
node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r)
node _res_T_280 = eq(_res_T_279, UInt<2>(0h3))
node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r)
node _res_T_282 = eq(_res_T_281, UInt<3>(0h4))
node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r)
node _res_T_284 = eq(_res_T_283, UInt<3>(0h5))
node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r)
node _res_T_286 = eq(_res_T_285, UInt<3>(0h7))
node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_288 = and(_res_T_287, res_hit_6)
node _res_T_289 = and(_res_T_288, UInt<1>(0h1))
node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_291 = and(_res_T_289, _res_T_290)
node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_293 = and(_res_T_292, UInt<1>(0h1))
node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_295 = and(_res_T_293, _res_T_294)
node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_297 = and(_res_T_296, res_hit_6)
node _res_T_298 = and(_res_T_297, UInt<1>(0h1))
node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_300 = and(_res_T_298, _res_T_299)
node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_302 = and(_res_T_301, UInt<1>(0h1))
node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_304 = and(_res_T_302, _res_T_303)
node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_306 = and(_res_T_305, res_hit_6)
node _res_T_307 = and(_res_T_306, UInt<1>(0h1))
node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_309 = and(_res_T_307, _res_T_308)
node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_311 = and(_res_T_310, UInt<1>(0h1))
node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_313 = and(_res_T_311, _res_T_312)
wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_6, io.pmp[1]
node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6)
node _res_cur_cfg_r_T_13 = and(UInt<1>(0h1), _res_cur_cfg_r_T_12)
connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13
node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6)
node _res_cur_cfg_w_T_13 = and(UInt<1>(0h1), _res_cur_cfg_w_T_12)
connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13
node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6)
node _res_cur_cfg_x_T_13 = and(UInt<1>(0h1), _res_cur_cfg_x_T_12)
connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13
node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269)
node _res_hit_T_182 = bits(io.pmp[0].cfg.a, 1, 1)
node _res_hit_T_183 = shl(io.pmp[0].addr, 2)
node _res_hit_T_184 = not(_res_hit_T_183)
node _res_hit_T_185 = or(_res_hit_T_184, UInt<2>(0h3))
node _res_hit_T_186 = not(_res_hit_T_185)
node _res_hit_T_187 = xor(io.addr, _res_hit_T_186)
node _res_hit_T_188 = not(io.pmp[0].mask)
node _res_hit_T_189 = and(_res_hit_T_187, _res_hit_T_188)
node _res_hit_T_190 = eq(_res_hit_T_189, UInt<1>(0h0))
node _res_hit_T_191 = bits(io.pmp[0].cfg.a, 0, 0)
node _res_hit_T_192 = dshl(UInt<2>(0h3), io.size)
node _res_hit_T_193 = bits(_res_hit_T_192, 1, 0)
node _res_hit_T_194 = not(_res_hit_T_193)
node _res_hit_T_195 = shl(pmp0.addr, 2)
node _res_hit_T_196 = not(_res_hit_T_195)
node _res_hit_T_197 = or(_res_hit_T_196, UInt<2>(0h3))
node _res_hit_T_198 = not(_res_hit_T_197)
node _res_hit_T_199 = lt(io.addr, _res_hit_T_198)
node _res_hit_T_200 = eq(_res_hit_T_199, UInt<1>(0h0))
node _res_hit_T_201 = shl(io.pmp[0].addr, 2)
node _res_hit_T_202 = not(_res_hit_T_201)
node _res_hit_T_203 = or(_res_hit_T_202, UInt<2>(0h3))
node _res_hit_T_204 = not(_res_hit_T_203)
node _res_hit_T_205 = lt(io.addr, _res_hit_T_204)
node _res_hit_T_206 = and(_res_hit_T_200, _res_hit_T_205)
node _res_hit_T_207 = and(_res_hit_T_191, _res_hit_T_206)
node res_hit_7 = mux(_res_hit_T_182, _res_hit_T_190, _res_hit_T_207)
node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0))
node res_ignore_7 = and(default, _res_ignore_T_7)
node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0))
node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1))
node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r)
node _res_T_321 = eq(_res_T_320, UInt<1>(0h0))
node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r)
node _res_T_323 = eq(_res_T_322, UInt<1>(0h1))
node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r)
node _res_T_325 = eq(_res_T_324, UInt<2>(0h3))
node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r)
node _res_T_327 = eq(_res_T_326, UInt<3>(0h4))
node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r)
node _res_T_329 = eq(_res_T_328, UInt<3>(0h5))
node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r)
node _res_T_331 = eq(_res_T_330, UInt<3>(0h7))
node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_333 = and(_res_T_332, res_hit_7)
node _res_T_334 = and(_res_T_333, UInt<1>(0h1))
node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_336 = and(_res_T_334, _res_T_335)
node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_338 = and(_res_T_337, UInt<1>(0h1))
node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_340 = and(_res_T_338, _res_T_339)
node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_342 = and(_res_T_341, res_hit_7)
node _res_T_343 = and(_res_T_342, UInt<1>(0h1))
node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_345 = and(_res_T_343, _res_T_344)
node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_347 = and(_res_T_346, UInt<1>(0h1))
node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_349 = and(_res_T_347, _res_T_348)
node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_351 = and(_res_T_350, res_hit_7)
node _res_T_352 = and(_res_T_351, UInt<1>(0h1))
node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_354 = and(_res_T_352, _res_T_353)
node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_356 = and(_res_T_355, UInt<1>(0h1))
node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_358 = and(_res_T_356, _res_T_357)
wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_7, io.pmp[0]
node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7)
node _res_cur_cfg_r_T_15 = and(UInt<1>(0h1), _res_cur_cfg_r_T_14)
connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15
node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7)
node _res_cur_cfg_w_T_15 = and(UInt<1>(0h1), _res_cur_cfg_w_T_14)
connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15
node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7)
node _res_cur_cfg_x_T_15 = and(UInt<1>(0h1), _res_cur_cfg_x_T_14)
connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15
node res = mux(res_hit_7, res_cur_7, _res_T_314)
connect io.r, res.cfg.r
connect io.w, res.cfg.w
connect io.x, res.cfg.x | module PMPChecker_s2( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_T_196 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_197 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_T_195 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_198 = 32'h0; // @[PMP.scala:60:27]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire _res_hit_T_199 = 1'h0; // @[PMP.scala:77:9]
wire _res_hit_T_200 = 1'h1; // @[PMP.scala:88:5]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_1; // @[PMP.scala:60:36]
assign _res_hit_T_1 = _GEN; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_19; // @[PMP.scala:60:36]
assign _res_hit_T_19 = _GEN; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_2 = ~_res_hit_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_3 = {_res_hit_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_4 = ~_res_hit_T_3; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_5 = io_addr_0 ^ _res_hit_T_4; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_6 = ~io_pmp_7_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_7 = _res_hit_T_5 & _res_hit_T_6; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_8 = _res_hit_T_7 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_9 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [4:0] _GEN_0 = 5'h3 << io_size_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_10; // @[package.scala:243:71]
assign _res_hit_T_10 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_36; // @[package.scala:243:71]
assign _res_hit_T_36 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_62; // @[package.scala:243:71]
assign _res_hit_T_62 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_88; // @[package.scala:243:71]
assign _res_hit_T_88 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_114; // @[package.scala:243:71]
assign _res_hit_T_114 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_140; // @[package.scala:243:71]
assign _res_hit_T_140 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_166; // @[package.scala:243:71]
assign _res_hit_T_166 = _GEN_0; // @[package.scala:243:71]
wire [4:0] _res_hit_T_192; // @[package.scala:243:71]
assign _res_hit_T_192 = _GEN_0; // @[package.scala:243:71]
wire [1:0] _res_hit_T_11 = _res_hit_T_10[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_12 = ~_res_hit_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_13; // @[PMP.scala:60:36]
assign _res_hit_T_13 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_27; // @[PMP.scala:60:36]
assign _res_hit_T_27 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_45; // @[PMP.scala:60:36]
assign _res_hit_T_45 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_14 = ~_res_hit_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_15 = {_res_hit_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_16 = ~_res_hit_T_15; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_17 = io_addr_0 < _res_hit_T_16; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_18 = ~_res_hit_T_17; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_20 = ~_res_hit_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_21 = {_res_hit_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_22 = ~_res_hit_T_21; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_23 = io_addr_0 < _res_hit_T_22; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_24 = _res_hit_T_18 & _res_hit_T_23; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_9 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_8 : _res_hit_T_25; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18; // @[PMP.scala:177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22; // @[PMP.scala:178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27; // @[PMP.scala:177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31; // @[PMP.scala:178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36; // @[PMP.scala:177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40; // @[PMP.scala:178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = _res_cur_cfg_r_T; // @[PMP.scala:182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = _res_cur_cfg_w_T; // @[PMP.scala:183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = _res_cur_cfg_x_T; // @[PMP.scala:184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_28 = ~_res_hit_T_27; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_29 = {_res_hit_T_28[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_30 = ~_res_hit_T_29; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_31 = io_addr_0 ^ _res_hit_T_30; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_32 = ~io_pmp_6_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_33 = _res_hit_T_31 & _res_hit_T_32; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_34 = _res_hit_T_33 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_35 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [1:0] _res_hit_T_37 = _res_hit_T_36[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_38 = ~_res_hit_T_37; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_39; // @[PMP.scala:60:36]
assign _res_hit_T_39 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_53; // @[PMP.scala:60:36]
assign _res_hit_T_53 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_71; // @[PMP.scala:60:36]
assign _res_hit_T_71 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_40 = ~_res_hit_T_39; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_41 = {_res_hit_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_42 = ~_res_hit_T_41; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_43 = io_addr_0 < _res_hit_T_42; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_44 = ~_res_hit_T_43; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_46 = ~_res_hit_T_45; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_47 = {_res_hit_T_46[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_48 = ~_res_hit_T_47; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_49 = io_addr_0 < _res_hit_T_48; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_50 = _res_hit_T_44 & _res_hit_T_49; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_35 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_26 ? _res_hit_T_34 : _res_hit_T_51; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63; // @[PMP.scala:177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67; // @[PMP.scala:178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72; // @[PMP.scala:177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76; // @[PMP.scala:178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81; // @[PMP.scala:177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85; // @[PMP.scala:178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = _res_cur_cfg_r_T_2; // @[PMP.scala:182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = _res_cur_cfg_w_T_2; // @[PMP.scala:183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = _res_cur_cfg_x_T_2; // @[PMP.scala:184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_54 = ~_res_hit_T_53; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_55 = {_res_hit_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_56 = ~_res_hit_T_55; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_57 = io_addr_0 ^ _res_hit_T_56; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_58 = ~io_pmp_5_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_59 = _res_hit_T_57 & _res_hit_T_58; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_60 = _res_hit_T_59 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_61 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [1:0] _res_hit_T_63 = _res_hit_T_62[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_64 = ~_res_hit_T_63; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_65; // @[PMP.scala:60:36]
assign _res_hit_T_65 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_79; // @[PMP.scala:60:36]
assign _res_hit_T_79 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_97; // @[PMP.scala:60:36]
assign _res_hit_T_97 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_66 = ~_res_hit_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_67 = {_res_hit_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_68 = ~_res_hit_T_67; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_69 = io_addr_0 < _res_hit_T_68; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_70 = ~_res_hit_T_69; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_72 = ~_res_hit_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_73 = {_res_hit_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_74 = ~_res_hit_T_73; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_75 = io_addr_0 < _res_hit_T_74; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_76 = _res_hit_T_70 & _res_hit_T_75; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_61 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_52 ? _res_hit_T_60 : _res_hit_T_77; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108; // @[PMP.scala:177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112; // @[PMP.scala:178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117; // @[PMP.scala:177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121; // @[PMP.scala:178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126; // @[PMP.scala:177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130; // @[PMP.scala:178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = _res_cur_cfg_r_T_4; // @[PMP.scala:182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = _res_cur_cfg_w_T_4; // @[PMP.scala:183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = _res_cur_cfg_x_T_4; // @[PMP.scala:184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_80 = ~_res_hit_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_81 = {_res_hit_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_82 = ~_res_hit_T_81; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_83 = io_addr_0 ^ _res_hit_T_82; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_84 = ~io_pmp_4_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_85 = _res_hit_T_83 & _res_hit_T_84; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_86 = _res_hit_T_85 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_87 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [1:0] _res_hit_T_89 = _res_hit_T_88[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_90 = ~_res_hit_T_89; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_91; // @[PMP.scala:60:36]
assign _res_hit_T_91 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_105; // @[PMP.scala:60:36]
assign _res_hit_T_105 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_123; // @[PMP.scala:60:36]
assign _res_hit_T_123 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_92 = ~_res_hit_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_93 = {_res_hit_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_94 = ~_res_hit_T_93; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_95 = io_addr_0 < _res_hit_T_94; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_96 = ~_res_hit_T_95; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_98 = ~_res_hit_T_97; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_99 = {_res_hit_T_98[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_100 = ~_res_hit_T_99; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_101 = io_addr_0 < _res_hit_T_100; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_102 = _res_hit_T_96 & _res_hit_T_101; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_103 = _res_hit_T_87 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_78 ? _res_hit_T_86 : _res_hit_T_103; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153; // @[PMP.scala:177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157; // @[PMP.scala:178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162; // @[PMP.scala:177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166; // @[PMP.scala:178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171; // @[PMP.scala:177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175; // @[PMP.scala:178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = _res_cur_cfg_r_T_6; // @[PMP.scala:182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = _res_cur_cfg_w_T_6; // @[PMP.scala:183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = _res_cur_cfg_x_T_6; // @[PMP.scala:184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_104 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_106 = ~_res_hit_T_105; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_107 = {_res_hit_T_106[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_108 = ~_res_hit_T_107; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_109 = io_addr_0 ^ _res_hit_T_108; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_110 = ~io_pmp_3_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_111 = _res_hit_T_109 & _res_hit_T_110; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_112 = _res_hit_T_111 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_113 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [1:0] _res_hit_T_115 = _res_hit_T_114[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_116 = ~_res_hit_T_115; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_117; // @[PMP.scala:60:36]
assign _res_hit_T_117 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_131; // @[PMP.scala:60:36]
assign _res_hit_T_131 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_149; // @[PMP.scala:60:36]
assign _res_hit_T_149 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_118 = ~_res_hit_T_117; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_119 = {_res_hit_T_118[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_120 = ~_res_hit_T_119; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_121 = io_addr_0 < _res_hit_T_120; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_122 = ~_res_hit_T_121; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_124 = ~_res_hit_T_123; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_125 = {_res_hit_T_124[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_126 = ~_res_hit_T_125; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_127 = io_addr_0 < _res_hit_T_126; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_128 = _res_hit_T_122 & _res_hit_T_127; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_129 = _res_hit_T_113 & _res_hit_T_128; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_104 ? _res_hit_T_112 : _res_hit_T_129; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198; // @[PMP.scala:177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202; // @[PMP.scala:178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207; // @[PMP.scala:177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211; // @[PMP.scala:178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216; // @[PMP.scala:177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220; // @[PMP.scala:178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = _res_cur_cfg_r_T_8; // @[PMP.scala:182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = _res_cur_cfg_w_T_8; // @[PMP.scala:183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = _res_cur_cfg_x_T_8; // @[PMP.scala:184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_130 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_132 = ~_res_hit_T_131; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_133 = {_res_hit_T_132[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_134 = ~_res_hit_T_133; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_135 = io_addr_0 ^ _res_hit_T_134; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_136 = ~io_pmp_2_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_137 = _res_hit_T_135 & _res_hit_T_136; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_138 = _res_hit_T_137 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_139 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [1:0] _res_hit_T_141 = _res_hit_T_140[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_142 = ~_res_hit_T_141; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_143; // @[PMP.scala:60:36]
assign _res_hit_T_143 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_157; // @[PMP.scala:60:36]
assign _res_hit_T_157 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_175; // @[PMP.scala:60:36]
assign _res_hit_T_175 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_144 = ~_res_hit_T_143; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_145 = {_res_hit_T_144[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_146 = ~_res_hit_T_145; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_147 = io_addr_0 < _res_hit_T_146; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_148 = ~_res_hit_T_147; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_150 = ~_res_hit_T_149; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_151 = {_res_hit_T_150[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_152 = ~_res_hit_T_151; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_153 = io_addr_0 < _res_hit_T_152; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_154 = _res_hit_T_148 & _res_hit_T_153; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_155 = _res_hit_T_139 & _res_hit_T_154; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_130 ? _res_hit_T_138 : _res_hit_T_155; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243; // @[PMP.scala:177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247; // @[PMP.scala:178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252; // @[PMP.scala:177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256; // @[PMP.scala:178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261; // @[PMP.scala:177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265; // @[PMP.scala:178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = _res_cur_cfg_r_T_10; // @[PMP.scala:182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = _res_cur_cfg_w_T_10; // @[PMP.scala:183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = _res_cur_cfg_x_T_10; // @[PMP.scala:184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_156 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_158 = ~_res_hit_T_157; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_159 = {_res_hit_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_160 = ~_res_hit_T_159; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_161 = io_addr_0 ^ _res_hit_T_160; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_162 = ~io_pmp_1_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_163 = _res_hit_T_161 & _res_hit_T_162; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_164 = _res_hit_T_163 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_165 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [1:0] _res_hit_T_167 = _res_hit_T_166[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_168 = ~_res_hit_T_167; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_T_169; // @[PMP.scala:60:36]
assign _res_hit_T_169 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_183; // @[PMP.scala:60:36]
assign _res_hit_T_183 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_201; // @[PMP.scala:60:36]
assign _res_hit_T_201 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_T_170 = ~_res_hit_T_169; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_171 = {_res_hit_T_170[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_172 = ~_res_hit_T_171; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_173 = io_addr_0 < _res_hit_T_172; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_174 = ~_res_hit_T_173; // @[PMP.scala:77:9, :88:5]
wire [31:0] _res_hit_T_176 = ~_res_hit_T_175; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_177 = {_res_hit_T_176[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_178 = ~_res_hit_T_177; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_179 = io_addr_0 < _res_hit_T_178; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_180 = _res_hit_T_174 & _res_hit_T_179; // @[PMP.scala:77:9, :88:5, :94:48]
wire _res_hit_T_181 = _res_hit_T_165 & _res_hit_T_180; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_156 ? _res_hit_T_164 : _res_hit_T_181; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288; // @[PMP.scala:177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292; // @[PMP.scala:178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297; // @[PMP.scala:177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301; // @[PMP.scala:178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306; // @[PMP.scala:177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310; // @[PMP.scala:178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = _res_cur_cfg_r_T_12; // @[PMP.scala:182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = _res_cur_cfg_w_T_12; // @[PMP.scala:183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = _res_cur_cfg_x_T_12; // @[PMP.scala:184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_182 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [31:0] _res_hit_T_184 = ~_res_hit_T_183; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_185 = {_res_hit_T_184[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_186 = ~_res_hit_T_185; // @[PMP.scala:60:{27,48}]
wire [31:0] _res_hit_T_187 = io_addr_0 ^ _res_hit_T_186; // @[PMP.scala:60:27, :63:47, :143:7]
wire [31:0] _res_hit_T_188 = ~io_pmp_0_mask_0; // @[PMP.scala:63:54, :143:7]
wire [31:0] _res_hit_T_189 = _res_hit_T_187 & _res_hit_T_188; // @[PMP.scala:63:{47,52,54}]
wire _res_hit_T_190 = _res_hit_T_189 == 32'h0; // @[PMP.scala:63:{52,58}]
wire _res_hit_T_191 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [1:0] _res_hit_T_193 = _res_hit_T_192[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _res_hit_T_194 = ~_res_hit_T_193; // @[package.scala:243:{46,76}]
wire [31:0] _res_hit_T_202 = ~_res_hit_T_201; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_T_203 = {_res_hit_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_T_204 = ~_res_hit_T_203; // @[PMP.scala:60:{27,48}]
wire _res_hit_T_205 = io_addr_0 < _res_hit_T_204; // @[PMP.scala:60:27, :77:9, :143:7]
wire _res_hit_T_206 = _res_hit_T_205; // @[PMP.scala:77:9, :94:48]
wire _res_hit_T_207 = _res_hit_T_191 & _res_hit_T_206; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_182 ? _res_hit_T_190 : _res_hit_T_207; // @[PMP.scala:45:20, :63:58, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[package.scala:243:71]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333; // @[PMP.scala:177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337; // @[PMP.scala:178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342; // @[PMP.scala:177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346; // @[PMP.scala:178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351; // @[PMP.scala:177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355; // @[PMP.scala:178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = _res_cur_cfg_r_T_14; // @[PMP.scala:182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = _res_cur_cfg_w_T_14; // @[PMP.scala:183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = _res_cur_cfg_x_T_14; // @[PMP.scala:184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_187 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_443
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_187( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_443 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<8>[7], flip divs : UInt<11>[7], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}}
inst sourceA of SourceA
connect sourceA.clock, clock
connect sourceA.reset, reset
inst sourceB of SourceB
connect sourceB.clock, clock
connect sourceB.reset, reset
inst sourceC of SourceC
connect sourceC.clock, clock
connect sourceC.reset, reset
inst sourceD of SourceD
connect sourceD.clock, clock
connect sourceD.reset, reset
inst sourceE of SourceE
connect sourceE.clock, clock
connect sourceE.reset, reset
inst sourceX of SourceX
connect sourceX.clock, clock
connect sourceX.reset, reset
connect io.out.a.bits, sourceA.io.a.bits
connect io.out.a.valid, sourceA.io.a.valid
connect sourceA.io.a.ready, io.out.a.ready
connect io.out.c.bits, sourceC.io.c.bits
connect io.out.c.valid, sourceC.io.c.valid
connect sourceC.io.c.ready, io.out.c.ready
connect io.out.e.bits, sourceE.io.e.bits
connect io.out.e.valid, sourceE.io.e.valid
connect sourceE.io.e.ready, io.out.e.ready
connect io.in.b.bits, sourceB.io.b.bits
connect io.in.b.valid, sourceB.io.b.valid
connect sourceB.io.b.ready, io.in.b.ready
connect io.in.d.bits, sourceD.io.d.bits
connect io.in.d.valid, sourceD.io.d.valid
connect sourceD.io.d.ready, io.in.d.ready
connect io.resp.bits, sourceX.io.x.bits
connect io.resp.valid, sourceX.io.x.valid
connect sourceX.io.x.ready, io.resp.ready
inst sinkA of SinkA
connect sinkA.clock, clock
connect sinkA.reset, reset
inst sinkC of SinkC
connect sinkC.clock, clock
connect sinkC.reset, reset
inst sinkD of SinkD
connect sinkD.clock, clock
connect sinkD.reset, reset
inst sinkE of SinkE
connect sinkE.clock, clock
connect sinkE.reset, reset
inst sinkX of SinkX
connect sinkX.clock, clock
connect sinkX.reset, reset
connect sinkA.io.a, io.in.a
connect sinkC.io.c, io.in.c
connect sinkE.io.e, io.in.e
connect sinkD.io.d, io.out.d
connect sinkX.io.x, io.req
connect io.out.b.ready, UInt<1>(0h1)
inst directory of Directory
connect directory.clock, clock
connect directory.reset, reset
inst bankedStore of BankedStore
connect bankedStore.clock, clock
connect bankedStore.reset, reset
inst requests of ListBuffer_QueuedRequest_q36_e28
connect requests.clock, clock
connect requests.reset, reset
inst mshrs_0 of MSHR
connect mshrs_0.clock, clock
connect mshrs_0.reset, reset
inst mshrs_1 of MSHR_1
connect mshrs_1.clock, clock
connect mshrs_1.reset, reset
inst mshrs_2 of MSHR_2
connect mshrs_2.clock, clock
connect mshrs_2.reset, reset
inst mshrs_3 of MSHR_3
connect mshrs_3.clock, clock
connect mshrs_3.reset, reset
inst mshrs_4 of MSHR_4
connect mshrs_4.clock, clock
connect mshrs_4.reset, reset
inst mshrs_5 of MSHR_5
connect mshrs_5.clock, clock
connect mshrs_5.reset, reset
inst mshrs_6 of MSHR_6
connect mshrs_6.clock, clock
connect mshrs_6.reset, reset
inst mshrs_7 of MSHR_7
connect mshrs_7.clock, clock
connect mshrs_7.reset, reset
inst mshrs_8 of MSHR_8
connect mshrs_8.clock, clock
connect mshrs_8.reset, reset
inst mshrs_9 of MSHR_9
connect mshrs_9.clock, clock
connect mshrs_9.reset, reset
inst mshrs_10 of MSHR_10
connect mshrs_10.clock, clock
connect mshrs_10.reset, reset
inst mshrs_11 of MSHR_11
connect mshrs_11.clock, clock
connect mshrs_11.reset, reset
wire nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}
node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set)
node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T)
connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1
node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0))
node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T)
connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1
node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0))
node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T)
connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1
connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_0.io.nestedwb.tag, nestedwb.tag
connect mshrs_0.io.nestedwb.set, nestedwb.set
node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set)
node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T)
connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1
node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1))
node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T)
connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1
node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1))
node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T)
connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1
connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_1.io.nestedwb.tag, nestedwb.tag
connect mshrs_1.io.nestedwb.set, nestedwb.set
node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set)
node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T)
connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1
node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2))
node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T)
connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1
node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2))
node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T)
connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1
connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_2.io.nestedwb.tag, nestedwb.tag
connect mshrs_2.io.nestedwb.set, nestedwb.set
node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set)
node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T)
connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1
node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3))
node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T)
connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1
node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3))
node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T)
connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1
connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_3.io.nestedwb.tag, nestedwb.tag
connect mshrs_3.io.nestedwb.set, nestedwb.set
node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set)
node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T)
connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1
node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4))
node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T)
connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1
node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4))
node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T)
connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1
connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_4.io.nestedwb.tag, nestedwb.tag
connect mshrs_4.io.nestedwb.set, nestedwb.set
node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set)
node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T)
connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1
node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5))
node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T)
connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1
node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5))
node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T)
connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1
connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_5.io.nestedwb.tag, nestedwb.tag
connect mshrs_5.io.nestedwb.set, nestedwb.set
node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set)
node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T)
connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1
node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6))
node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T)
connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1
node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6))
node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T)
connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1
connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_6.io.nestedwb.tag, nestedwb.tag
connect mshrs_6.io.nestedwb.set, nestedwb.set
node _mshrs_7_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_7.io.status.bits.set)
node _mshrs_7_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_7_io_sinkc_valid_T)
connect mshrs_7.io.sinkc.valid, _mshrs_7_io_sinkc_valid_T_1
node _mshrs_7_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h7))
node _mshrs_7_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_7_io_sinkd_valid_T)
connect mshrs_7.io.sinkd.valid, _mshrs_7_io_sinkd_valid_T_1
node _mshrs_7_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h7))
node _mshrs_7_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_7_io_sinke_valid_T)
connect mshrs_7.io.sinke.valid, _mshrs_7_io_sinke_valid_T_1
connect mshrs_7.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_7.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_7.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_7.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_7.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_7.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_7.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_7.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_7.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_7.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_7.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_7.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_7.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_7.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_7.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_7.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_7.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_7.io.nestedwb.tag, nestedwb.tag
connect mshrs_7.io.nestedwb.set, nestedwb.set
node _mshrs_8_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_8.io.status.bits.set)
node _mshrs_8_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_8_io_sinkc_valid_T)
connect mshrs_8.io.sinkc.valid, _mshrs_8_io_sinkc_valid_T_1
node _mshrs_8_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h8))
node _mshrs_8_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_8_io_sinkd_valid_T)
connect mshrs_8.io.sinkd.valid, _mshrs_8_io_sinkd_valid_T_1
node _mshrs_8_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h8))
node _mshrs_8_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_8_io_sinke_valid_T)
connect mshrs_8.io.sinke.valid, _mshrs_8_io_sinke_valid_T_1
connect mshrs_8.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_8.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_8.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_8.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_8.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_8.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_8.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_8.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_8.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_8.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_8.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_8.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_8.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_8.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_8.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_8.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_8.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_8.io.nestedwb.tag, nestedwb.tag
connect mshrs_8.io.nestedwb.set, nestedwb.set
node _mshrs_9_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_9.io.status.bits.set)
node _mshrs_9_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_9_io_sinkc_valid_T)
connect mshrs_9.io.sinkc.valid, _mshrs_9_io_sinkc_valid_T_1
node _mshrs_9_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h9))
node _mshrs_9_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_9_io_sinkd_valid_T)
connect mshrs_9.io.sinkd.valid, _mshrs_9_io_sinkd_valid_T_1
node _mshrs_9_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h9))
node _mshrs_9_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_9_io_sinke_valid_T)
connect mshrs_9.io.sinke.valid, _mshrs_9_io_sinke_valid_T_1
connect mshrs_9.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_9.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_9.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_9.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_9.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_9.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_9.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_9.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_9.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_9.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_9.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_9.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_9.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_9.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_9.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_9.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_9.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_9.io.nestedwb.tag, nestedwb.tag
connect mshrs_9.io.nestedwb.set, nestedwb.set
node _mshrs_10_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_10.io.status.bits.set)
node _mshrs_10_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_10_io_sinkc_valid_T)
connect mshrs_10.io.sinkc.valid, _mshrs_10_io_sinkc_valid_T_1
node _mshrs_10_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0ha))
node _mshrs_10_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_10_io_sinkd_valid_T)
connect mshrs_10.io.sinkd.valid, _mshrs_10_io_sinkd_valid_T_1
node _mshrs_10_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0ha))
node _mshrs_10_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_10_io_sinke_valid_T)
connect mshrs_10.io.sinke.valid, _mshrs_10_io_sinke_valid_T_1
connect mshrs_10.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_10.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_10.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_10.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_10.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_10.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_10.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_10.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_10.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_10.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_10.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_10.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_10.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_10.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_10.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_10.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_10.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_10.io.nestedwb.tag, nestedwb.tag
connect mshrs_10.io.nestedwb.set, nestedwb.set
node _mshrs_11_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_11.io.status.bits.set)
node _mshrs_11_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_11_io_sinkc_valid_T)
connect mshrs_11.io.sinkc.valid, _mshrs_11_io_sinkc_valid_T_1
node _mshrs_11_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0hb))
node _mshrs_11_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_11_io_sinkd_valid_T)
connect mshrs_11.io.sinkd.valid, _mshrs_11_io_sinkd_valid_T_1
node _mshrs_11_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0hb))
node _mshrs_11_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_11_io_sinke_valid_T)
connect mshrs_11.io.sinke.valid, _mshrs_11_io_sinke_valid_T_1
connect mshrs_11.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_11.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_11.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_11.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_11.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_11.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_11.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_11.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_11.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_11.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_11.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_11.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_11.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_11.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_11.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_11.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_11.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_11.io.nestedwb.tag, nestedwb.tag
connect mshrs_11.io.nestedwb.set, nestedwb.set
node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_1 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T)
node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_3 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_2)
node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3)
node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_5 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_4)
node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_7 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_6)
node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7)
node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_9 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_8)
node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_11 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_10)
node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11)
node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_13 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_12)
node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_15 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_14)
node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15)
node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_17 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_16)
node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_19 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_18)
node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19)
node _mshr_stall_abc_T_20 = eq(mshrs_5.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_21 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_20)
node _mshr_stall_abc_T_22 = eq(mshrs_5.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_23 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_22)
node mshr_stall_abc_5 = or(_mshr_stall_abc_T_21, _mshr_stall_abc_T_23)
node _mshr_stall_abc_T_24 = eq(mshrs_6.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_25 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_24)
node _mshr_stall_abc_T_26 = eq(mshrs_6.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_27 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_26)
node mshr_stall_abc_6 = or(_mshr_stall_abc_T_25, _mshr_stall_abc_T_27)
node _mshr_stall_abc_T_28 = eq(mshrs_7.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_29 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_28)
node _mshr_stall_abc_T_30 = eq(mshrs_7.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_31 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_30)
node mshr_stall_abc_7 = or(_mshr_stall_abc_T_29, _mshr_stall_abc_T_31)
node _mshr_stall_abc_T_32 = eq(mshrs_8.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_33 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_32)
node _mshr_stall_abc_T_34 = eq(mshrs_8.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_35 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_34)
node mshr_stall_abc_8 = or(_mshr_stall_abc_T_33, _mshr_stall_abc_T_35)
node _mshr_stall_abc_T_36 = eq(mshrs_9.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_37 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_36)
node _mshr_stall_abc_T_38 = eq(mshrs_9.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_39 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_38)
node mshr_stall_abc_9 = or(_mshr_stall_abc_T_37, _mshr_stall_abc_T_39)
node _mshr_stall_bc_T = eq(mshrs_10.io.status.bits.set, mshrs_11.io.status.bits.set)
node mshr_stall_bc = and(mshrs_11.io.status.valid, _mshr_stall_bc_T)
node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid)
node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid)
node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid)
node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid)
node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid)
node stall_abc_5 = and(mshr_stall_abc_5, mshrs_5.io.status.valid)
node stall_abc_6 = and(mshr_stall_abc_6, mshrs_6.io.status.valid)
node stall_abc_7 = and(mshr_stall_abc_7, mshrs_7.io.status.valid)
node stall_abc_8 = and(mshr_stall_abc_8, mshrs_8.io.status.valid)
node stall_abc_9 = and(mshr_stall_abc_9, mshrs_9.io.status.valid)
node _T = or(stall_abc_0, stall_abc_1)
node _T_1 = or(_T, stall_abc_2)
node _T_2 = or(_T_1, stall_abc_3)
node _T_3 = or(_T_2, stall_abc_4)
node _T_4 = or(_T_3, stall_abc_5)
node _T_5 = or(_T_4, stall_abc_6)
node _T_6 = or(_T_5, stall_abc_7)
node _T_7 = or(_T_6, stall_abc_8)
node _T_8 = or(_T_7, stall_abc_9)
node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0))
node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T)
node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2)
node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3)
node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5)
node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6)
node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8)
node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9)
node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11)
node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12)
node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14)
node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15)
node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17)
node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18)
node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20)
node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21)
node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0))
node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23)
node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25)
node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26)
node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28)
node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29)
node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31)
node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32)
node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34)
node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35)
node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37)
node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38)
node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40)
node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41)
node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43)
node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44)
node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0))
node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46)
node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48)
node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49)
node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51)
node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52)
node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54)
node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55)
node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57)
node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58)
node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60)
node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61)
node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63)
node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64)
node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66)
node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67)
node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0))
node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69)
node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71)
node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72)
node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74)
node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75)
node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77)
node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78)
node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80)
node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81)
node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83)
node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84)
node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86)
node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87)
node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89)
node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90)
node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0))
node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92)
node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94)
node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95)
node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97)
node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98)
node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100)
node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101)
node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103)
node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104)
node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106)
node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107)
node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109)
node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110)
node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112)
node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113)
node _mshr_request_T_115 = eq(mshr_stall_abc_5, UInt<1>(0h0))
node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115)
node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117)
node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118)
node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120)
node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121)
node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123)
node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124)
node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126)
node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127)
node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129)
node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130)
node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132)
node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133)
node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135)
node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136)
node _mshr_request_T_138 = eq(mshr_stall_abc_6, UInt<1>(0h0))
node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138)
node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140)
node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141)
node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143)
node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144)
node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146)
node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147)
node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149)
node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150)
node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152)
node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153)
node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155)
node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156)
node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158)
node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159)
node _mshr_request_T_161 = eq(mshr_stall_abc_7, UInt<1>(0h0))
node _mshr_request_T_162 = and(mshrs_7.io.schedule.valid, _mshr_request_T_161)
node _mshr_request_T_163 = eq(mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_164 = or(sourceA.io.req.ready, _mshr_request_T_163)
node _mshr_request_T_165 = and(_mshr_request_T_162, _mshr_request_T_164)
node _mshr_request_T_166 = eq(mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_167 = or(sourceB.io.req.ready, _mshr_request_T_166)
node _mshr_request_T_168 = and(_mshr_request_T_165, _mshr_request_T_167)
node _mshr_request_T_169 = eq(mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_170 = or(sourceC.io.req.ready, _mshr_request_T_169)
node _mshr_request_T_171 = and(_mshr_request_T_168, _mshr_request_T_170)
node _mshr_request_T_172 = eq(mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_173 = or(sourceD.io.req.ready, _mshr_request_T_172)
node _mshr_request_T_174 = and(_mshr_request_T_171, _mshr_request_T_173)
node _mshr_request_T_175 = eq(mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_176 = or(sourceE.io.req.ready, _mshr_request_T_175)
node _mshr_request_T_177 = and(_mshr_request_T_174, _mshr_request_T_176)
node _mshr_request_T_178 = eq(mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_179 = or(sourceX.io.req.ready, _mshr_request_T_178)
node _mshr_request_T_180 = and(_mshr_request_T_177, _mshr_request_T_179)
node _mshr_request_T_181 = eq(mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_182 = or(directory.io.write.ready, _mshr_request_T_181)
node _mshr_request_T_183 = and(_mshr_request_T_180, _mshr_request_T_182)
node _mshr_request_T_184 = eq(mshr_stall_abc_8, UInt<1>(0h0))
node _mshr_request_T_185 = and(mshrs_8.io.schedule.valid, _mshr_request_T_184)
node _mshr_request_T_186 = eq(mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_187 = or(sourceA.io.req.ready, _mshr_request_T_186)
node _mshr_request_T_188 = and(_mshr_request_T_185, _mshr_request_T_187)
node _mshr_request_T_189 = eq(mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_190 = or(sourceB.io.req.ready, _mshr_request_T_189)
node _mshr_request_T_191 = and(_mshr_request_T_188, _mshr_request_T_190)
node _mshr_request_T_192 = eq(mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_193 = or(sourceC.io.req.ready, _mshr_request_T_192)
node _mshr_request_T_194 = and(_mshr_request_T_191, _mshr_request_T_193)
node _mshr_request_T_195 = eq(mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_196 = or(sourceD.io.req.ready, _mshr_request_T_195)
node _mshr_request_T_197 = and(_mshr_request_T_194, _mshr_request_T_196)
node _mshr_request_T_198 = eq(mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_199 = or(sourceE.io.req.ready, _mshr_request_T_198)
node _mshr_request_T_200 = and(_mshr_request_T_197, _mshr_request_T_199)
node _mshr_request_T_201 = eq(mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_202 = or(sourceX.io.req.ready, _mshr_request_T_201)
node _mshr_request_T_203 = and(_mshr_request_T_200, _mshr_request_T_202)
node _mshr_request_T_204 = eq(mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_205 = or(directory.io.write.ready, _mshr_request_T_204)
node _mshr_request_T_206 = and(_mshr_request_T_203, _mshr_request_T_205)
node _mshr_request_T_207 = eq(mshr_stall_abc_9, UInt<1>(0h0))
node _mshr_request_T_208 = and(mshrs_9.io.schedule.valid, _mshr_request_T_207)
node _mshr_request_T_209 = eq(mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_210 = or(sourceA.io.req.ready, _mshr_request_T_209)
node _mshr_request_T_211 = and(_mshr_request_T_208, _mshr_request_T_210)
node _mshr_request_T_212 = eq(mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_213 = or(sourceB.io.req.ready, _mshr_request_T_212)
node _mshr_request_T_214 = and(_mshr_request_T_211, _mshr_request_T_213)
node _mshr_request_T_215 = eq(mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_216 = or(sourceC.io.req.ready, _mshr_request_T_215)
node _mshr_request_T_217 = and(_mshr_request_T_214, _mshr_request_T_216)
node _mshr_request_T_218 = eq(mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_219 = or(sourceD.io.req.ready, _mshr_request_T_218)
node _mshr_request_T_220 = and(_mshr_request_T_217, _mshr_request_T_219)
node _mshr_request_T_221 = eq(mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_222 = or(sourceE.io.req.ready, _mshr_request_T_221)
node _mshr_request_T_223 = and(_mshr_request_T_220, _mshr_request_T_222)
node _mshr_request_T_224 = eq(mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_225 = or(sourceX.io.req.ready, _mshr_request_T_224)
node _mshr_request_T_226 = and(_mshr_request_T_223, _mshr_request_T_225)
node _mshr_request_T_227 = eq(mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_228 = or(directory.io.write.ready, _mshr_request_T_227)
node _mshr_request_T_229 = and(_mshr_request_T_226, _mshr_request_T_228)
node _mshr_request_T_230 = eq(mshr_stall_bc, UInt<1>(0h0))
node _mshr_request_T_231 = and(mshrs_10.io.schedule.valid, _mshr_request_T_230)
node _mshr_request_T_232 = eq(mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_233 = or(sourceA.io.req.ready, _mshr_request_T_232)
node _mshr_request_T_234 = and(_mshr_request_T_231, _mshr_request_T_233)
node _mshr_request_T_235 = eq(mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_236 = or(sourceB.io.req.ready, _mshr_request_T_235)
node _mshr_request_T_237 = and(_mshr_request_T_234, _mshr_request_T_236)
node _mshr_request_T_238 = eq(mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_239 = or(sourceC.io.req.ready, _mshr_request_T_238)
node _mshr_request_T_240 = and(_mshr_request_T_237, _mshr_request_T_239)
node _mshr_request_T_241 = eq(mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_242 = or(sourceD.io.req.ready, _mshr_request_T_241)
node _mshr_request_T_243 = and(_mshr_request_T_240, _mshr_request_T_242)
node _mshr_request_T_244 = eq(mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_245 = or(sourceE.io.req.ready, _mshr_request_T_244)
node _mshr_request_T_246 = and(_mshr_request_T_243, _mshr_request_T_245)
node _mshr_request_T_247 = eq(mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_248 = or(sourceX.io.req.ready, _mshr_request_T_247)
node _mshr_request_T_249 = and(_mshr_request_T_246, _mshr_request_T_248)
node _mshr_request_T_250 = eq(mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_251 = or(directory.io.write.ready, _mshr_request_T_250)
node _mshr_request_T_252 = and(_mshr_request_T_249, _mshr_request_T_251)
node _mshr_request_T_253 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _mshr_request_T_254 = and(mshrs_11.io.schedule.valid, _mshr_request_T_253)
node _mshr_request_T_255 = eq(mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_256 = or(sourceA.io.req.ready, _mshr_request_T_255)
node _mshr_request_T_257 = and(_mshr_request_T_254, _mshr_request_T_256)
node _mshr_request_T_258 = eq(mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_259 = or(sourceB.io.req.ready, _mshr_request_T_258)
node _mshr_request_T_260 = and(_mshr_request_T_257, _mshr_request_T_259)
node _mshr_request_T_261 = eq(mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_262 = or(sourceC.io.req.ready, _mshr_request_T_261)
node _mshr_request_T_263 = and(_mshr_request_T_260, _mshr_request_T_262)
node _mshr_request_T_264 = eq(mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_265 = or(sourceD.io.req.ready, _mshr_request_T_264)
node _mshr_request_T_266 = and(_mshr_request_T_263, _mshr_request_T_265)
node _mshr_request_T_267 = eq(mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_268 = or(sourceE.io.req.ready, _mshr_request_T_267)
node _mshr_request_T_269 = and(_mshr_request_T_266, _mshr_request_T_268)
node _mshr_request_T_270 = eq(mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_271 = or(sourceX.io.req.ready, _mshr_request_T_270)
node _mshr_request_T_272 = and(_mshr_request_T_269, _mshr_request_T_271)
node _mshr_request_T_273 = eq(mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_274 = or(directory.io.write.ready, _mshr_request_T_273)
node _mshr_request_T_275 = and(_mshr_request_T_272, _mshr_request_T_274)
node mshr_request_lo_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45)
node mshr_request_lo_lo = cat(mshr_request_lo_lo_hi, _mshr_request_T_22)
node mshr_request_lo_hi_hi = cat(_mshr_request_T_137, _mshr_request_T_114)
node mshr_request_lo_hi = cat(mshr_request_lo_hi_hi, _mshr_request_T_91)
node mshr_request_lo = cat(mshr_request_lo_hi, mshr_request_lo_lo)
node mshr_request_hi_lo_hi = cat(_mshr_request_T_206, _mshr_request_T_183)
node mshr_request_hi_lo = cat(mshr_request_hi_lo_hi, _mshr_request_T_160)
node mshr_request_hi_hi_hi = cat(_mshr_request_T_275, _mshr_request_T_252)
node mshr_request_hi_hi = cat(mshr_request_hi_hi_hi, _mshr_request_T_229)
node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo)
node mshr_request = cat(mshr_request_hi, mshr_request_lo)
regreset robin_filter : UInt<12>, clock, reset, UInt<12>(0h0)
node _robin_request_T = and(mshr_request, robin_filter)
node robin_request = cat(mshr_request, _robin_request_T)
node _mshr_selectOH2_T = shl(robin_request, 1)
node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 23, 0)
node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1)
node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2)
node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 23, 0)
node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4)
node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4)
node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 23, 0)
node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7)
node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8)
node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 23, 0)
node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10)
node _mshr_selectOH2_T_12 = shl(_mshr_selectOH2_T_11, 16)
node _mshr_selectOH2_T_13 = bits(_mshr_selectOH2_T_12, 23, 0)
node _mshr_selectOH2_T_14 = or(_mshr_selectOH2_T_11, _mshr_selectOH2_T_13)
node _mshr_selectOH2_T_15 = bits(_mshr_selectOH2_T_14, 23, 0)
node _mshr_selectOH2_T_16 = shl(_mshr_selectOH2_T_15, 1)
node _mshr_selectOH2_T_17 = not(_mshr_selectOH2_T_16)
node mshr_selectOH2 = and(_mshr_selectOH2_T_17, robin_request)
node _mshr_selectOH_T = bits(mshr_selectOH2, 23, 12)
node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 11, 0)
node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1)
node mshr_select_hi = bits(mshr_selectOH, 11, 8)
node mshr_select_lo = bits(mshr_selectOH, 7, 0)
node _mshr_select_T = orr(mshr_select_hi)
node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo)
node mshr_select_hi_1 = bits(_mshr_select_T_1, 7, 4)
node mshr_select_lo_1 = bits(_mshr_select_T_1, 3, 0)
node _mshr_select_T_2 = orr(mshr_select_hi_1)
node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1)
node mshr_select_hi_2 = bits(_mshr_select_T_3, 3, 2)
node mshr_select_lo_2 = bits(_mshr_select_T_3, 1, 0)
node _mshr_select_T_4 = orr(mshr_select_hi_2)
node _mshr_select_T_5 = or(mshr_select_hi_2, mshr_select_lo_2)
node _mshr_select_T_6 = bits(_mshr_select_T_5, 1, 1)
node _mshr_select_T_7 = cat(_mshr_select_T_4, _mshr_select_T_6)
node _mshr_select_T_8 = cat(_mshr_select_T_2, _mshr_select_T_7)
node mshr_select = cat(_mshr_select_T, _mshr_select_T_8)
node _schedule_T = bits(mshr_selectOH, 0, 0)
node _schedule_T_1 = bits(mshr_selectOH, 1, 1)
node _schedule_T_2 = bits(mshr_selectOH, 2, 2)
node _schedule_T_3 = bits(mshr_selectOH, 3, 3)
node _schedule_T_4 = bits(mshr_selectOH, 4, 4)
node _schedule_T_5 = bits(mshr_selectOH, 5, 5)
node _schedule_T_6 = bits(mshr_selectOH, 6, 6)
node _schedule_T_7 = bits(mshr_selectOH, 7, 7)
node _schedule_T_8 = bits(mshr_selectOH, 8, 8)
node _schedule_T_9 = bits(mshr_selectOH, 9, 9)
node _schedule_T_10 = bits(mshr_selectOH, 10, 10)
node _schedule_T_11 = bits(mshr_selectOH, 11, 11)
wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}
node _schedule_T_12 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_13 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_14 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_15 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_16 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_17 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_18 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_19 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_20 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_21 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_22 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_23 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_24 = or(_schedule_T_12, _schedule_T_13)
node _schedule_T_25 = or(_schedule_T_24, _schedule_T_14)
node _schedule_T_26 = or(_schedule_T_25, _schedule_T_15)
node _schedule_T_27 = or(_schedule_T_26, _schedule_T_16)
node _schedule_T_28 = or(_schedule_T_27, _schedule_T_17)
node _schedule_T_29 = or(_schedule_T_28, _schedule_T_18)
node _schedule_T_30 = or(_schedule_T_29, _schedule_T_19)
node _schedule_T_31 = or(_schedule_T_30, _schedule_T_20)
node _schedule_T_32 = or(_schedule_T_31, _schedule_T_21)
node _schedule_T_33 = or(_schedule_T_32, _schedule_T_22)
node _schedule_T_34 = or(_schedule_T_33, _schedule_T_23)
wire _schedule_WIRE : UInt<1>
connect _schedule_WIRE, _schedule_T_34
connect schedule.reload, _schedule_WIRE
wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}
wire _schedule_WIRE_2 : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}
wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
node _schedule_T_35 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_36 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_37 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_38 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_39 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_40 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_41 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_42 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_43 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_44 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_45 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_46 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_47 = or(_schedule_T_35, _schedule_T_36)
node _schedule_T_48 = or(_schedule_T_47, _schedule_T_37)
node _schedule_T_49 = or(_schedule_T_48, _schedule_T_38)
node _schedule_T_50 = or(_schedule_T_49, _schedule_T_39)
node _schedule_T_51 = or(_schedule_T_50, _schedule_T_40)
node _schedule_T_52 = or(_schedule_T_51, _schedule_T_41)
node _schedule_T_53 = or(_schedule_T_52, _schedule_T_42)
node _schedule_T_54 = or(_schedule_T_53, _schedule_T_43)
node _schedule_T_55 = or(_schedule_T_54, _schedule_T_44)
node _schedule_T_56 = or(_schedule_T_55, _schedule_T_45)
node _schedule_T_57 = or(_schedule_T_56, _schedule_T_46)
wire _schedule_WIRE_4 : UInt<13>
connect _schedule_WIRE_4, _schedule_T_57
connect _schedule_WIRE_3.tag, _schedule_WIRE_4
node _schedule_T_58 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_59 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_60 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_61 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_62 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_63 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_64 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_65 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_66 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_67 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_68 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_69 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_70 = or(_schedule_T_58, _schedule_T_59)
node _schedule_T_71 = or(_schedule_T_70, _schedule_T_60)
node _schedule_T_72 = or(_schedule_T_71, _schedule_T_61)
node _schedule_T_73 = or(_schedule_T_72, _schedule_T_62)
node _schedule_T_74 = or(_schedule_T_73, _schedule_T_63)
node _schedule_T_75 = or(_schedule_T_74, _schedule_T_64)
node _schedule_T_76 = or(_schedule_T_75, _schedule_T_65)
node _schedule_T_77 = or(_schedule_T_76, _schedule_T_66)
node _schedule_T_78 = or(_schedule_T_77, _schedule_T_67)
node _schedule_T_79 = or(_schedule_T_78, _schedule_T_68)
node _schedule_T_80 = or(_schedule_T_79, _schedule_T_69)
wire _schedule_WIRE_5 : UInt<1>
connect _schedule_WIRE_5, _schedule_T_80
connect _schedule_WIRE_3.clients, _schedule_WIRE_5
node _schedule_T_81 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_82 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_83 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_84 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_85 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_86 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_87 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_88 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_89 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_90 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_91 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_92 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_93 = or(_schedule_T_81, _schedule_T_82)
node _schedule_T_94 = or(_schedule_T_93, _schedule_T_83)
node _schedule_T_95 = or(_schedule_T_94, _schedule_T_84)
node _schedule_T_96 = or(_schedule_T_95, _schedule_T_85)
node _schedule_T_97 = or(_schedule_T_96, _schedule_T_86)
node _schedule_T_98 = or(_schedule_T_97, _schedule_T_87)
node _schedule_T_99 = or(_schedule_T_98, _schedule_T_88)
node _schedule_T_100 = or(_schedule_T_99, _schedule_T_89)
node _schedule_T_101 = or(_schedule_T_100, _schedule_T_90)
node _schedule_T_102 = or(_schedule_T_101, _schedule_T_91)
node _schedule_T_103 = or(_schedule_T_102, _schedule_T_92)
wire _schedule_WIRE_6 : UInt<2>
connect _schedule_WIRE_6, _schedule_T_103
connect _schedule_WIRE_3.state, _schedule_WIRE_6
node _schedule_T_104 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_105 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_106 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_107 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_108 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_109 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_110 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_111 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_112 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_113 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_114 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_115 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_116 = or(_schedule_T_104, _schedule_T_105)
node _schedule_T_117 = or(_schedule_T_116, _schedule_T_106)
node _schedule_T_118 = or(_schedule_T_117, _schedule_T_107)
node _schedule_T_119 = or(_schedule_T_118, _schedule_T_108)
node _schedule_T_120 = or(_schedule_T_119, _schedule_T_109)
node _schedule_T_121 = or(_schedule_T_120, _schedule_T_110)
node _schedule_T_122 = or(_schedule_T_121, _schedule_T_111)
node _schedule_T_123 = or(_schedule_T_122, _schedule_T_112)
node _schedule_T_124 = or(_schedule_T_123, _schedule_T_113)
node _schedule_T_125 = or(_schedule_T_124, _schedule_T_114)
node _schedule_T_126 = or(_schedule_T_125, _schedule_T_115)
wire _schedule_WIRE_7 : UInt<1>
connect _schedule_WIRE_7, _schedule_T_126
connect _schedule_WIRE_3.dirty, _schedule_WIRE_7
connect _schedule_WIRE_2.data, _schedule_WIRE_3
node _schedule_T_127 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_128 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_129 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_130 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_131 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_132 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_133 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_134 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_135 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_136 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_137 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_138 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_139 = or(_schedule_T_127, _schedule_T_128)
node _schedule_T_140 = or(_schedule_T_139, _schedule_T_129)
node _schedule_T_141 = or(_schedule_T_140, _schedule_T_130)
node _schedule_T_142 = or(_schedule_T_141, _schedule_T_131)
node _schedule_T_143 = or(_schedule_T_142, _schedule_T_132)
node _schedule_T_144 = or(_schedule_T_143, _schedule_T_133)
node _schedule_T_145 = or(_schedule_T_144, _schedule_T_134)
node _schedule_T_146 = or(_schedule_T_145, _schedule_T_135)
node _schedule_T_147 = or(_schedule_T_146, _schedule_T_136)
node _schedule_T_148 = or(_schedule_T_147, _schedule_T_137)
node _schedule_T_149 = or(_schedule_T_148, _schedule_T_138)
wire _schedule_WIRE_8 : UInt<3>
connect _schedule_WIRE_8, _schedule_T_149
connect _schedule_WIRE_2.way, _schedule_WIRE_8
node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_157 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_158 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_159 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_160 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_161 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_162 = or(_schedule_T_150, _schedule_T_151)
node _schedule_T_163 = or(_schedule_T_162, _schedule_T_152)
node _schedule_T_164 = or(_schedule_T_163, _schedule_T_153)
node _schedule_T_165 = or(_schedule_T_164, _schedule_T_154)
node _schedule_T_166 = or(_schedule_T_165, _schedule_T_155)
node _schedule_T_167 = or(_schedule_T_166, _schedule_T_156)
node _schedule_T_168 = or(_schedule_T_167, _schedule_T_157)
node _schedule_T_169 = or(_schedule_T_168, _schedule_T_158)
node _schedule_T_170 = or(_schedule_T_169, _schedule_T_159)
node _schedule_T_171 = or(_schedule_T_170, _schedule_T_160)
node _schedule_T_172 = or(_schedule_T_171, _schedule_T_161)
wire _schedule_WIRE_9 : UInt<10>
connect _schedule_WIRE_9, _schedule_T_172
connect _schedule_WIRE_2.set, _schedule_WIRE_9
connect _schedule_WIRE_1.bits, _schedule_WIRE_2
node _schedule_T_173 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_174 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_175 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_176 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_177 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_178 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_179 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_180 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_181 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_182 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_183 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_184 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_185 = or(_schedule_T_173, _schedule_T_174)
node _schedule_T_186 = or(_schedule_T_185, _schedule_T_175)
node _schedule_T_187 = or(_schedule_T_186, _schedule_T_176)
node _schedule_T_188 = or(_schedule_T_187, _schedule_T_177)
node _schedule_T_189 = or(_schedule_T_188, _schedule_T_178)
node _schedule_T_190 = or(_schedule_T_189, _schedule_T_179)
node _schedule_T_191 = or(_schedule_T_190, _schedule_T_180)
node _schedule_T_192 = or(_schedule_T_191, _schedule_T_181)
node _schedule_T_193 = or(_schedule_T_192, _schedule_T_182)
node _schedule_T_194 = or(_schedule_T_193, _schedule_T_183)
node _schedule_T_195 = or(_schedule_T_194, _schedule_T_184)
wire _schedule_WIRE_10 : UInt<1>
connect _schedule_WIRE_10, _schedule_T_195
connect _schedule_WIRE_1.valid, _schedule_WIRE_10
connect schedule.dir, _schedule_WIRE_1
wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}}
wire _schedule_WIRE_12 : { fail : UInt<1>}
node _schedule_T_196 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_197 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_198 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_199 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_200 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_201 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_202 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_203 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_204 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_205 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_206 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_207 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_208 = or(_schedule_T_196, _schedule_T_197)
node _schedule_T_209 = or(_schedule_T_208, _schedule_T_198)
node _schedule_T_210 = or(_schedule_T_209, _schedule_T_199)
node _schedule_T_211 = or(_schedule_T_210, _schedule_T_200)
node _schedule_T_212 = or(_schedule_T_211, _schedule_T_201)
node _schedule_T_213 = or(_schedule_T_212, _schedule_T_202)
node _schedule_T_214 = or(_schedule_T_213, _schedule_T_203)
node _schedule_T_215 = or(_schedule_T_214, _schedule_T_204)
node _schedule_T_216 = or(_schedule_T_215, _schedule_T_205)
node _schedule_T_217 = or(_schedule_T_216, _schedule_T_206)
node _schedule_T_218 = or(_schedule_T_217, _schedule_T_207)
wire _schedule_WIRE_13 : UInt<1>
connect _schedule_WIRE_13, _schedule_T_218
connect _schedule_WIRE_12.fail, _schedule_WIRE_13
connect _schedule_WIRE_11.bits, _schedule_WIRE_12
node _schedule_T_219 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_220 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_221 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_222 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_223 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_224 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_225 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_226 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_227 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_228 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_229 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_230 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_231 = or(_schedule_T_219, _schedule_T_220)
node _schedule_T_232 = or(_schedule_T_231, _schedule_T_221)
node _schedule_T_233 = or(_schedule_T_232, _schedule_T_222)
node _schedule_T_234 = or(_schedule_T_233, _schedule_T_223)
node _schedule_T_235 = or(_schedule_T_234, _schedule_T_224)
node _schedule_T_236 = or(_schedule_T_235, _schedule_T_225)
node _schedule_T_237 = or(_schedule_T_236, _schedule_T_226)
node _schedule_T_238 = or(_schedule_T_237, _schedule_T_227)
node _schedule_T_239 = or(_schedule_T_238, _schedule_T_228)
node _schedule_T_240 = or(_schedule_T_239, _schedule_T_229)
node _schedule_T_241 = or(_schedule_T_240, _schedule_T_230)
wire _schedule_WIRE_14 : UInt<1>
connect _schedule_WIRE_14, _schedule_T_241
connect _schedule_WIRE_11.valid, _schedule_WIRE_14
connect schedule.x, _schedule_WIRE_11
wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}}
wire _schedule_WIRE_16 : { sink : UInt<3>}
node _schedule_T_242 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_243 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_244 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_245 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_246 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_247 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_248 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_249 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_250 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_251 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_252 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_253 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_254 = or(_schedule_T_242, _schedule_T_243)
node _schedule_T_255 = or(_schedule_T_254, _schedule_T_244)
node _schedule_T_256 = or(_schedule_T_255, _schedule_T_245)
node _schedule_T_257 = or(_schedule_T_256, _schedule_T_246)
node _schedule_T_258 = or(_schedule_T_257, _schedule_T_247)
node _schedule_T_259 = or(_schedule_T_258, _schedule_T_248)
node _schedule_T_260 = or(_schedule_T_259, _schedule_T_249)
node _schedule_T_261 = or(_schedule_T_260, _schedule_T_250)
node _schedule_T_262 = or(_schedule_T_261, _schedule_T_251)
node _schedule_T_263 = or(_schedule_T_262, _schedule_T_252)
node _schedule_T_264 = or(_schedule_T_263, _schedule_T_253)
wire _schedule_WIRE_17 : UInt<3>
connect _schedule_WIRE_17, _schedule_T_264
connect _schedule_WIRE_16.sink, _schedule_WIRE_17
connect _schedule_WIRE_15.bits, _schedule_WIRE_16
node _schedule_T_265 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_266 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_267 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_268 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_269 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_270 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_271 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_272 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_273 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_274 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_275 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_276 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_277 = or(_schedule_T_265, _schedule_T_266)
node _schedule_T_278 = or(_schedule_T_277, _schedule_T_267)
node _schedule_T_279 = or(_schedule_T_278, _schedule_T_268)
node _schedule_T_280 = or(_schedule_T_279, _schedule_T_269)
node _schedule_T_281 = or(_schedule_T_280, _schedule_T_270)
node _schedule_T_282 = or(_schedule_T_281, _schedule_T_271)
node _schedule_T_283 = or(_schedule_T_282, _schedule_T_272)
node _schedule_T_284 = or(_schedule_T_283, _schedule_T_273)
node _schedule_T_285 = or(_schedule_T_284, _schedule_T_274)
node _schedule_T_286 = or(_schedule_T_285, _schedule_T_275)
node _schedule_T_287 = or(_schedule_T_286, _schedule_T_276)
wire _schedule_WIRE_18 : UInt<1>
connect _schedule_WIRE_18, _schedule_T_287
connect _schedule_WIRE_15.valid, _schedule_WIRE_18
connect schedule.e, _schedule_WIRE_15
wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}
wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}
node _schedule_T_288 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_289 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_290 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_291 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_292 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_293 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_294 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_295 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_296 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_297 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_298 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_299 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_300 = or(_schedule_T_288, _schedule_T_289)
node _schedule_T_301 = or(_schedule_T_300, _schedule_T_290)
node _schedule_T_302 = or(_schedule_T_301, _schedule_T_291)
node _schedule_T_303 = or(_schedule_T_302, _schedule_T_292)
node _schedule_T_304 = or(_schedule_T_303, _schedule_T_293)
node _schedule_T_305 = or(_schedule_T_304, _schedule_T_294)
node _schedule_T_306 = or(_schedule_T_305, _schedule_T_295)
node _schedule_T_307 = or(_schedule_T_306, _schedule_T_296)
node _schedule_T_308 = or(_schedule_T_307, _schedule_T_297)
node _schedule_T_309 = or(_schedule_T_308, _schedule_T_298)
node _schedule_T_310 = or(_schedule_T_309, _schedule_T_299)
wire _schedule_WIRE_21 : UInt<1>
connect _schedule_WIRE_21, _schedule_T_310
connect _schedule_WIRE_20.bad, _schedule_WIRE_21
node _schedule_T_311 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_312 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_313 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_314 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_315 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_316 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_317 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_318 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_319 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_320 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_321 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_322 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_323 = or(_schedule_T_311, _schedule_T_312)
node _schedule_T_324 = or(_schedule_T_323, _schedule_T_313)
node _schedule_T_325 = or(_schedule_T_324, _schedule_T_314)
node _schedule_T_326 = or(_schedule_T_325, _schedule_T_315)
node _schedule_T_327 = or(_schedule_T_326, _schedule_T_316)
node _schedule_T_328 = or(_schedule_T_327, _schedule_T_317)
node _schedule_T_329 = or(_schedule_T_328, _schedule_T_318)
node _schedule_T_330 = or(_schedule_T_329, _schedule_T_319)
node _schedule_T_331 = or(_schedule_T_330, _schedule_T_320)
node _schedule_T_332 = or(_schedule_T_331, _schedule_T_321)
node _schedule_T_333 = or(_schedule_T_332, _schedule_T_322)
wire _schedule_WIRE_22 : UInt<3>
connect _schedule_WIRE_22, _schedule_T_333
connect _schedule_WIRE_20.way, _schedule_WIRE_22
node _schedule_T_334 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_335 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_336 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_337 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_338 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_339 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_340 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_341 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_342 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_343 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_344 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_345 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_346 = or(_schedule_T_334, _schedule_T_335)
node _schedule_T_347 = or(_schedule_T_346, _schedule_T_336)
node _schedule_T_348 = or(_schedule_T_347, _schedule_T_337)
node _schedule_T_349 = or(_schedule_T_348, _schedule_T_338)
node _schedule_T_350 = or(_schedule_T_349, _schedule_T_339)
node _schedule_T_351 = or(_schedule_T_350, _schedule_T_340)
node _schedule_T_352 = or(_schedule_T_351, _schedule_T_341)
node _schedule_T_353 = or(_schedule_T_352, _schedule_T_342)
node _schedule_T_354 = or(_schedule_T_353, _schedule_T_343)
node _schedule_T_355 = or(_schedule_T_354, _schedule_T_344)
node _schedule_T_356 = or(_schedule_T_355, _schedule_T_345)
wire _schedule_WIRE_23 : UInt<4>
connect _schedule_WIRE_23, _schedule_T_356
connect _schedule_WIRE_20.sink, _schedule_WIRE_23
node _schedule_T_357 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_358 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_359 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_360 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_361 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_362 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_363 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_364 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_365 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_366 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_367 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_368 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_369 = or(_schedule_T_357, _schedule_T_358)
node _schedule_T_370 = or(_schedule_T_369, _schedule_T_359)
node _schedule_T_371 = or(_schedule_T_370, _schedule_T_360)
node _schedule_T_372 = or(_schedule_T_371, _schedule_T_361)
node _schedule_T_373 = or(_schedule_T_372, _schedule_T_362)
node _schedule_T_374 = or(_schedule_T_373, _schedule_T_363)
node _schedule_T_375 = or(_schedule_T_374, _schedule_T_364)
node _schedule_T_376 = or(_schedule_T_375, _schedule_T_365)
node _schedule_T_377 = or(_schedule_T_376, _schedule_T_366)
node _schedule_T_378 = or(_schedule_T_377, _schedule_T_367)
node _schedule_T_379 = or(_schedule_T_378, _schedule_T_368)
wire _schedule_WIRE_24 : UInt<10>
connect _schedule_WIRE_24, _schedule_T_379
connect _schedule_WIRE_20.set, _schedule_WIRE_24
node _schedule_T_380 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_381 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_382 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_383 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_384 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_385 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_386 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_387 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_388 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_389 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_390 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_391 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_392 = or(_schedule_T_380, _schedule_T_381)
node _schedule_T_393 = or(_schedule_T_392, _schedule_T_382)
node _schedule_T_394 = or(_schedule_T_393, _schedule_T_383)
node _schedule_T_395 = or(_schedule_T_394, _schedule_T_384)
node _schedule_T_396 = or(_schedule_T_395, _schedule_T_385)
node _schedule_T_397 = or(_schedule_T_396, _schedule_T_386)
node _schedule_T_398 = or(_schedule_T_397, _schedule_T_387)
node _schedule_T_399 = or(_schedule_T_398, _schedule_T_388)
node _schedule_T_400 = or(_schedule_T_399, _schedule_T_389)
node _schedule_T_401 = or(_schedule_T_400, _schedule_T_390)
node _schedule_T_402 = or(_schedule_T_401, _schedule_T_391)
wire _schedule_WIRE_25 : UInt<6>
connect _schedule_WIRE_25, _schedule_T_402
connect _schedule_WIRE_20.put, _schedule_WIRE_25
node _schedule_T_403 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_404 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_405 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_406 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_407 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_408 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_409 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_410 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_411 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_412 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_413 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_414 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_415 = or(_schedule_T_403, _schedule_T_404)
node _schedule_T_416 = or(_schedule_T_415, _schedule_T_405)
node _schedule_T_417 = or(_schedule_T_416, _schedule_T_406)
node _schedule_T_418 = or(_schedule_T_417, _schedule_T_407)
node _schedule_T_419 = or(_schedule_T_418, _schedule_T_408)
node _schedule_T_420 = or(_schedule_T_419, _schedule_T_409)
node _schedule_T_421 = or(_schedule_T_420, _schedule_T_410)
node _schedule_T_422 = or(_schedule_T_421, _schedule_T_411)
node _schedule_T_423 = or(_schedule_T_422, _schedule_T_412)
node _schedule_T_424 = or(_schedule_T_423, _schedule_T_413)
node _schedule_T_425 = or(_schedule_T_424, _schedule_T_414)
wire _schedule_WIRE_26 : UInt<6>
connect _schedule_WIRE_26, _schedule_T_425
connect _schedule_WIRE_20.offset, _schedule_WIRE_26
node _schedule_T_426 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_427 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_428 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_429 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_430 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_431 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_432 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_433 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_434 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_435 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_436 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_437 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_438 = or(_schedule_T_426, _schedule_T_427)
node _schedule_T_439 = or(_schedule_T_438, _schedule_T_428)
node _schedule_T_440 = or(_schedule_T_439, _schedule_T_429)
node _schedule_T_441 = or(_schedule_T_440, _schedule_T_430)
node _schedule_T_442 = or(_schedule_T_441, _schedule_T_431)
node _schedule_T_443 = or(_schedule_T_442, _schedule_T_432)
node _schedule_T_444 = or(_schedule_T_443, _schedule_T_433)
node _schedule_T_445 = or(_schedule_T_444, _schedule_T_434)
node _schedule_T_446 = or(_schedule_T_445, _schedule_T_435)
node _schedule_T_447 = or(_schedule_T_446, _schedule_T_436)
node _schedule_T_448 = or(_schedule_T_447, _schedule_T_437)
wire _schedule_WIRE_27 : UInt<13>
connect _schedule_WIRE_27, _schedule_T_448
connect _schedule_WIRE_20.tag, _schedule_WIRE_27
node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_456 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_457 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_458 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_459 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_460 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_461 = or(_schedule_T_449, _schedule_T_450)
node _schedule_T_462 = or(_schedule_T_461, _schedule_T_451)
node _schedule_T_463 = or(_schedule_T_462, _schedule_T_452)
node _schedule_T_464 = or(_schedule_T_463, _schedule_T_453)
node _schedule_T_465 = or(_schedule_T_464, _schedule_T_454)
node _schedule_T_466 = or(_schedule_T_465, _schedule_T_455)
node _schedule_T_467 = or(_schedule_T_466, _schedule_T_456)
node _schedule_T_468 = or(_schedule_T_467, _schedule_T_457)
node _schedule_T_469 = or(_schedule_T_468, _schedule_T_458)
node _schedule_T_470 = or(_schedule_T_469, _schedule_T_459)
node _schedule_T_471 = or(_schedule_T_470, _schedule_T_460)
wire _schedule_WIRE_28 : UInt<6>
connect _schedule_WIRE_28, _schedule_T_471
connect _schedule_WIRE_20.source, _schedule_WIRE_28
node _schedule_T_472 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_473 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_474 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_475 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_476 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_477 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_478 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_479 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_480 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_481 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_482 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_483 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_484 = or(_schedule_T_472, _schedule_T_473)
node _schedule_T_485 = or(_schedule_T_484, _schedule_T_474)
node _schedule_T_486 = or(_schedule_T_485, _schedule_T_475)
node _schedule_T_487 = or(_schedule_T_486, _schedule_T_476)
node _schedule_T_488 = or(_schedule_T_487, _schedule_T_477)
node _schedule_T_489 = or(_schedule_T_488, _schedule_T_478)
node _schedule_T_490 = or(_schedule_T_489, _schedule_T_479)
node _schedule_T_491 = or(_schedule_T_490, _schedule_T_480)
node _schedule_T_492 = or(_schedule_T_491, _schedule_T_481)
node _schedule_T_493 = or(_schedule_T_492, _schedule_T_482)
node _schedule_T_494 = or(_schedule_T_493, _schedule_T_483)
wire _schedule_WIRE_29 : UInt<3>
connect _schedule_WIRE_29, _schedule_T_494
connect _schedule_WIRE_20.size, _schedule_WIRE_29
node _schedule_T_495 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_496 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_497 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_498 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_499 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_500 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_501 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_502 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_503 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_504 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_505 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_506 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_507 = or(_schedule_T_495, _schedule_T_496)
node _schedule_T_508 = or(_schedule_T_507, _schedule_T_497)
node _schedule_T_509 = or(_schedule_T_508, _schedule_T_498)
node _schedule_T_510 = or(_schedule_T_509, _schedule_T_499)
node _schedule_T_511 = or(_schedule_T_510, _schedule_T_500)
node _schedule_T_512 = or(_schedule_T_511, _schedule_T_501)
node _schedule_T_513 = or(_schedule_T_512, _schedule_T_502)
node _schedule_T_514 = or(_schedule_T_513, _schedule_T_503)
node _schedule_T_515 = or(_schedule_T_514, _schedule_T_504)
node _schedule_T_516 = or(_schedule_T_515, _schedule_T_505)
node _schedule_T_517 = or(_schedule_T_516, _schedule_T_506)
wire _schedule_WIRE_30 : UInt<3>
connect _schedule_WIRE_30, _schedule_T_517
connect _schedule_WIRE_20.param, _schedule_WIRE_30
node _schedule_T_518 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_519 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_520 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_521 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_522 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_523 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_524 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_525 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_526 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_527 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_528 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_529 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_530 = or(_schedule_T_518, _schedule_T_519)
node _schedule_T_531 = or(_schedule_T_530, _schedule_T_520)
node _schedule_T_532 = or(_schedule_T_531, _schedule_T_521)
node _schedule_T_533 = or(_schedule_T_532, _schedule_T_522)
node _schedule_T_534 = or(_schedule_T_533, _schedule_T_523)
node _schedule_T_535 = or(_schedule_T_534, _schedule_T_524)
node _schedule_T_536 = or(_schedule_T_535, _schedule_T_525)
node _schedule_T_537 = or(_schedule_T_536, _schedule_T_526)
node _schedule_T_538 = or(_schedule_T_537, _schedule_T_527)
node _schedule_T_539 = or(_schedule_T_538, _schedule_T_528)
node _schedule_T_540 = or(_schedule_T_539, _schedule_T_529)
wire _schedule_WIRE_31 : UInt<3>
connect _schedule_WIRE_31, _schedule_T_540
connect _schedule_WIRE_20.opcode, _schedule_WIRE_31
node _schedule_T_541 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_542 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_543 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_544 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_545 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_546 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_547 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_548 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_549 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_550 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_551 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_552 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_553 = or(_schedule_T_541, _schedule_T_542)
node _schedule_T_554 = or(_schedule_T_553, _schedule_T_543)
node _schedule_T_555 = or(_schedule_T_554, _schedule_T_544)
node _schedule_T_556 = or(_schedule_T_555, _schedule_T_545)
node _schedule_T_557 = or(_schedule_T_556, _schedule_T_546)
node _schedule_T_558 = or(_schedule_T_557, _schedule_T_547)
node _schedule_T_559 = or(_schedule_T_558, _schedule_T_548)
node _schedule_T_560 = or(_schedule_T_559, _schedule_T_549)
node _schedule_T_561 = or(_schedule_T_560, _schedule_T_550)
node _schedule_T_562 = or(_schedule_T_561, _schedule_T_551)
node _schedule_T_563 = or(_schedule_T_562, _schedule_T_552)
wire _schedule_WIRE_32 : UInt<1>
connect _schedule_WIRE_32, _schedule_T_563
connect _schedule_WIRE_20.control, _schedule_WIRE_32
wire _schedule_WIRE_33 : UInt<1>[3]
node _schedule_T_564 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_565 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_566 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_567 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_568 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_569 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_570 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_571 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_572 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_573 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_574 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_575 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_576 = or(_schedule_T_564, _schedule_T_565)
node _schedule_T_577 = or(_schedule_T_576, _schedule_T_566)
node _schedule_T_578 = or(_schedule_T_577, _schedule_T_567)
node _schedule_T_579 = or(_schedule_T_578, _schedule_T_568)
node _schedule_T_580 = or(_schedule_T_579, _schedule_T_569)
node _schedule_T_581 = or(_schedule_T_580, _schedule_T_570)
node _schedule_T_582 = or(_schedule_T_581, _schedule_T_571)
node _schedule_T_583 = or(_schedule_T_582, _schedule_T_572)
node _schedule_T_584 = or(_schedule_T_583, _schedule_T_573)
node _schedule_T_585 = or(_schedule_T_584, _schedule_T_574)
node _schedule_T_586 = or(_schedule_T_585, _schedule_T_575)
wire _schedule_WIRE_34 : UInt<1>
connect _schedule_WIRE_34, _schedule_T_586
connect _schedule_WIRE_33[0], _schedule_WIRE_34
node _schedule_T_587 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_588 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_589 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_590 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_591 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_592 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_593 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_594 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_595 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_596 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_597 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_598 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_599 = or(_schedule_T_587, _schedule_T_588)
node _schedule_T_600 = or(_schedule_T_599, _schedule_T_589)
node _schedule_T_601 = or(_schedule_T_600, _schedule_T_590)
node _schedule_T_602 = or(_schedule_T_601, _schedule_T_591)
node _schedule_T_603 = or(_schedule_T_602, _schedule_T_592)
node _schedule_T_604 = or(_schedule_T_603, _schedule_T_593)
node _schedule_T_605 = or(_schedule_T_604, _schedule_T_594)
node _schedule_T_606 = or(_schedule_T_605, _schedule_T_595)
node _schedule_T_607 = or(_schedule_T_606, _schedule_T_596)
node _schedule_T_608 = or(_schedule_T_607, _schedule_T_597)
node _schedule_T_609 = or(_schedule_T_608, _schedule_T_598)
wire _schedule_WIRE_35 : UInt<1>
connect _schedule_WIRE_35, _schedule_T_609
connect _schedule_WIRE_33[1], _schedule_WIRE_35
node _schedule_T_610 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_611 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_612 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_613 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_614 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_615 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_616 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_617 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_618 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_619 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_620 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_621 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_622 = or(_schedule_T_610, _schedule_T_611)
node _schedule_T_623 = or(_schedule_T_622, _schedule_T_612)
node _schedule_T_624 = or(_schedule_T_623, _schedule_T_613)
node _schedule_T_625 = or(_schedule_T_624, _schedule_T_614)
node _schedule_T_626 = or(_schedule_T_625, _schedule_T_615)
node _schedule_T_627 = or(_schedule_T_626, _schedule_T_616)
node _schedule_T_628 = or(_schedule_T_627, _schedule_T_617)
node _schedule_T_629 = or(_schedule_T_628, _schedule_T_618)
node _schedule_T_630 = or(_schedule_T_629, _schedule_T_619)
node _schedule_T_631 = or(_schedule_T_630, _schedule_T_620)
node _schedule_T_632 = or(_schedule_T_631, _schedule_T_621)
wire _schedule_WIRE_36 : UInt<1>
connect _schedule_WIRE_36, _schedule_T_632
connect _schedule_WIRE_33[2], _schedule_WIRE_36
connect _schedule_WIRE_20.prio, _schedule_WIRE_33
connect _schedule_WIRE_19.bits, _schedule_WIRE_20
node _schedule_T_633 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_634 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_635 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_636 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_637 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_638 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_639 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_640 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_641 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_642 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_643 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_644 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_645 = or(_schedule_T_633, _schedule_T_634)
node _schedule_T_646 = or(_schedule_T_645, _schedule_T_635)
node _schedule_T_647 = or(_schedule_T_646, _schedule_T_636)
node _schedule_T_648 = or(_schedule_T_647, _schedule_T_637)
node _schedule_T_649 = or(_schedule_T_648, _schedule_T_638)
node _schedule_T_650 = or(_schedule_T_649, _schedule_T_639)
node _schedule_T_651 = or(_schedule_T_650, _schedule_T_640)
node _schedule_T_652 = or(_schedule_T_651, _schedule_T_641)
node _schedule_T_653 = or(_schedule_T_652, _schedule_T_642)
node _schedule_T_654 = or(_schedule_T_653, _schedule_T_643)
node _schedule_T_655 = or(_schedule_T_654, _schedule_T_644)
wire _schedule_WIRE_37 : UInt<1>
connect _schedule_WIRE_37, _schedule_T_655
connect _schedule_WIRE_19.valid, _schedule_WIRE_37
connect schedule.d, _schedule_WIRE_19
wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}
wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}
node _schedule_T_656 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_657 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_658 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_659 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_660 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_661 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_662 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_663 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_664 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_665 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_666 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_667 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_668 = or(_schedule_T_656, _schedule_T_657)
node _schedule_T_669 = or(_schedule_T_668, _schedule_T_658)
node _schedule_T_670 = or(_schedule_T_669, _schedule_T_659)
node _schedule_T_671 = or(_schedule_T_670, _schedule_T_660)
node _schedule_T_672 = or(_schedule_T_671, _schedule_T_661)
node _schedule_T_673 = or(_schedule_T_672, _schedule_T_662)
node _schedule_T_674 = or(_schedule_T_673, _schedule_T_663)
node _schedule_T_675 = or(_schedule_T_674, _schedule_T_664)
node _schedule_T_676 = or(_schedule_T_675, _schedule_T_665)
node _schedule_T_677 = or(_schedule_T_676, _schedule_T_666)
node _schedule_T_678 = or(_schedule_T_677, _schedule_T_667)
wire _schedule_WIRE_40 : UInt<1>
connect _schedule_WIRE_40, _schedule_T_678
connect _schedule_WIRE_39.dirty, _schedule_WIRE_40
node _schedule_T_679 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_680 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_681 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_682 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_683 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_684 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_685 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_686 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_687 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_688 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_689 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_690 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_691 = or(_schedule_T_679, _schedule_T_680)
node _schedule_T_692 = or(_schedule_T_691, _schedule_T_681)
node _schedule_T_693 = or(_schedule_T_692, _schedule_T_682)
node _schedule_T_694 = or(_schedule_T_693, _schedule_T_683)
node _schedule_T_695 = or(_schedule_T_694, _schedule_T_684)
node _schedule_T_696 = or(_schedule_T_695, _schedule_T_685)
node _schedule_T_697 = or(_schedule_T_696, _schedule_T_686)
node _schedule_T_698 = or(_schedule_T_697, _schedule_T_687)
node _schedule_T_699 = or(_schedule_T_698, _schedule_T_688)
node _schedule_T_700 = or(_schedule_T_699, _schedule_T_689)
node _schedule_T_701 = or(_schedule_T_700, _schedule_T_690)
wire _schedule_WIRE_41 : UInt<3>
connect _schedule_WIRE_41, _schedule_T_701
connect _schedule_WIRE_39.way, _schedule_WIRE_41
node _schedule_T_702 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_703 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_704 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_705 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_706 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_707 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_708 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_709 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_710 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_711 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_712 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_713 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_714 = or(_schedule_T_702, _schedule_T_703)
node _schedule_T_715 = or(_schedule_T_714, _schedule_T_704)
node _schedule_T_716 = or(_schedule_T_715, _schedule_T_705)
node _schedule_T_717 = or(_schedule_T_716, _schedule_T_706)
node _schedule_T_718 = or(_schedule_T_717, _schedule_T_707)
node _schedule_T_719 = or(_schedule_T_718, _schedule_T_708)
node _schedule_T_720 = or(_schedule_T_719, _schedule_T_709)
node _schedule_T_721 = or(_schedule_T_720, _schedule_T_710)
node _schedule_T_722 = or(_schedule_T_721, _schedule_T_711)
node _schedule_T_723 = or(_schedule_T_722, _schedule_T_712)
node _schedule_T_724 = or(_schedule_T_723, _schedule_T_713)
wire _schedule_WIRE_42 : UInt<10>
connect _schedule_WIRE_42, _schedule_T_724
connect _schedule_WIRE_39.set, _schedule_WIRE_42
node _schedule_T_725 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_726 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_727 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_728 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_729 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_730 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_731 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_732 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_733 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_734 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_735 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_736 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_737 = or(_schedule_T_725, _schedule_T_726)
node _schedule_T_738 = or(_schedule_T_737, _schedule_T_727)
node _schedule_T_739 = or(_schedule_T_738, _schedule_T_728)
node _schedule_T_740 = or(_schedule_T_739, _schedule_T_729)
node _schedule_T_741 = or(_schedule_T_740, _schedule_T_730)
node _schedule_T_742 = or(_schedule_T_741, _schedule_T_731)
node _schedule_T_743 = or(_schedule_T_742, _schedule_T_732)
node _schedule_T_744 = or(_schedule_T_743, _schedule_T_733)
node _schedule_T_745 = or(_schedule_T_744, _schedule_T_734)
node _schedule_T_746 = or(_schedule_T_745, _schedule_T_735)
node _schedule_T_747 = or(_schedule_T_746, _schedule_T_736)
wire _schedule_WIRE_43 : UInt<13>
connect _schedule_WIRE_43, _schedule_T_747
connect _schedule_WIRE_39.tag, _schedule_WIRE_43
node _schedule_T_748 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_749 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_750 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_751 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_752 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_753 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_754 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_755 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_756 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_757 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_758 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_759 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_760 = or(_schedule_T_748, _schedule_T_749)
node _schedule_T_761 = or(_schedule_T_760, _schedule_T_750)
node _schedule_T_762 = or(_schedule_T_761, _schedule_T_751)
node _schedule_T_763 = or(_schedule_T_762, _schedule_T_752)
node _schedule_T_764 = or(_schedule_T_763, _schedule_T_753)
node _schedule_T_765 = or(_schedule_T_764, _schedule_T_754)
node _schedule_T_766 = or(_schedule_T_765, _schedule_T_755)
node _schedule_T_767 = or(_schedule_T_766, _schedule_T_756)
node _schedule_T_768 = or(_schedule_T_767, _schedule_T_757)
node _schedule_T_769 = or(_schedule_T_768, _schedule_T_758)
node _schedule_T_770 = or(_schedule_T_769, _schedule_T_759)
wire _schedule_WIRE_44 : UInt<4>
connect _schedule_WIRE_44, _schedule_T_770
connect _schedule_WIRE_39.source, _schedule_WIRE_44
node _schedule_T_771 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_772 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_773 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_774 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_775 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_776 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_777 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_778 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_779 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_780 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_781 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_782 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_783 = or(_schedule_T_771, _schedule_T_772)
node _schedule_T_784 = or(_schedule_T_783, _schedule_T_773)
node _schedule_T_785 = or(_schedule_T_784, _schedule_T_774)
node _schedule_T_786 = or(_schedule_T_785, _schedule_T_775)
node _schedule_T_787 = or(_schedule_T_786, _schedule_T_776)
node _schedule_T_788 = or(_schedule_T_787, _schedule_T_777)
node _schedule_T_789 = or(_schedule_T_788, _schedule_T_778)
node _schedule_T_790 = or(_schedule_T_789, _schedule_T_779)
node _schedule_T_791 = or(_schedule_T_790, _schedule_T_780)
node _schedule_T_792 = or(_schedule_T_791, _schedule_T_781)
node _schedule_T_793 = or(_schedule_T_792, _schedule_T_782)
wire _schedule_WIRE_45 : UInt<3>
connect _schedule_WIRE_45, _schedule_T_793
connect _schedule_WIRE_39.param, _schedule_WIRE_45
node _schedule_T_794 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_795 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_796 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_797 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_798 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_799 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_800 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_801 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_802 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_803 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_804 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_805 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_806 = or(_schedule_T_794, _schedule_T_795)
node _schedule_T_807 = or(_schedule_T_806, _schedule_T_796)
node _schedule_T_808 = or(_schedule_T_807, _schedule_T_797)
node _schedule_T_809 = or(_schedule_T_808, _schedule_T_798)
node _schedule_T_810 = or(_schedule_T_809, _schedule_T_799)
node _schedule_T_811 = or(_schedule_T_810, _schedule_T_800)
node _schedule_T_812 = or(_schedule_T_811, _schedule_T_801)
node _schedule_T_813 = or(_schedule_T_812, _schedule_T_802)
node _schedule_T_814 = or(_schedule_T_813, _schedule_T_803)
node _schedule_T_815 = or(_schedule_T_814, _schedule_T_804)
node _schedule_T_816 = or(_schedule_T_815, _schedule_T_805)
wire _schedule_WIRE_46 : UInt<3>
connect _schedule_WIRE_46, _schedule_T_816
connect _schedule_WIRE_39.opcode, _schedule_WIRE_46
connect _schedule_WIRE_38.bits, _schedule_WIRE_39
node _schedule_T_817 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_818 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_819 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_820 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_821 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_822 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_823 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_824 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_825 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_826 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_827 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_828 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_829 = or(_schedule_T_817, _schedule_T_818)
node _schedule_T_830 = or(_schedule_T_829, _schedule_T_819)
node _schedule_T_831 = or(_schedule_T_830, _schedule_T_820)
node _schedule_T_832 = or(_schedule_T_831, _schedule_T_821)
node _schedule_T_833 = or(_schedule_T_832, _schedule_T_822)
node _schedule_T_834 = or(_schedule_T_833, _schedule_T_823)
node _schedule_T_835 = or(_schedule_T_834, _schedule_T_824)
node _schedule_T_836 = or(_schedule_T_835, _schedule_T_825)
node _schedule_T_837 = or(_schedule_T_836, _schedule_T_826)
node _schedule_T_838 = or(_schedule_T_837, _schedule_T_827)
node _schedule_T_839 = or(_schedule_T_838, _schedule_T_828)
wire _schedule_WIRE_47 : UInt<1>
connect _schedule_WIRE_47, _schedule_T_839
connect _schedule_WIRE_38.valid, _schedule_WIRE_47
connect schedule.c, _schedule_WIRE_38
wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}
wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}
node _schedule_T_840 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_841 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_842 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_843 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_844 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_845 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_846 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_847 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_848 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_849 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_850 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_851 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_852 = or(_schedule_T_840, _schedule_T_841)
node _schedule_T_853 = or(_schedule_T_852, _schedule_T_842)
node _schedule_T_854 = or(_schedule_T_853, _schedule_T_843)
node _schedule_T_855 = or(_schedule_T_854, _schedule_T_844)
node _schedule_T_856 = or(_schedule_T_855, _schedule_T_845)
node _schedule_T_857 = or(_schedule_T_856, _schedule_T_846)
node _schedule_T_858 = or(_schedule_T_857, _schedule_T_847)
node _schedule_T_859 = or(_schedule_T_858, _schedule_T_848)
node _schedule_T_860 = or(_schedule_T_859, _schedule_T_849)
node _schedule_T_861 = or(_schedule_T_860, _schedule_T_850)
node _schedule_T_862 = or(_schedule_T_861, _schedule_T_851)
wire _schedule_WIRE_50 : UInt<1>
connect _schedule_WIRE_50, _schedule_T_862
connect _schedule_WIRE_49.clients, _schedule_WIRE_50
node _schedule_T_863 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_864 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_865 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_866 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_867 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_868 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_869 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_870 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_871 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_872 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_873 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_874 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_875 = or(_schedule_T_863, _schedule_T_864)
node _schedule_T_876 = or(_schedule_T_875, _schedule_T_865)
node _schedule_T_877 = or(_schedule_T_876, _schedule_T_866)
node _schedule_T_878 = or(_schedule_T_877, _schedule_T_867)
node _schedule_T_879 = or(_schedule_T_878, _schedule_T_868)
node _schedule_T_880 = or(_schedule_T_879, _schedule_T_869)
node _schedule_T_881 = or(_schedule_T_880, _schedule_T_870)
node _schedule_T_882 = or(_schedule_T_881, _schedule_T_871)
node _schedule_T_883 = or(_schedule_T_882, _schedule_T_872)
node _schedule_T_884 = or(_schedule_T_883, _schedule_T_873)
node _schedule_T_885 = or(_schedule_T_884, _schedule_T_874)
wire _schedule_WIRE_51 : UInt<10>
connect _schedule_WIRE_51, _schedule_T_885
connect _schedule_WIRE_49.set, _schedule_WIRE_51
node _schedule_T_886 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_887 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_888 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_889 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_890 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_891 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_892 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_893 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_894 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_895 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_896 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_897 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_898 = or(_schedule_T_886, _schedule_T_887)
node _schedule_T_899 = or(_schedule_T_898, _schedule_T_888)
node _schedule_T_900 = or(_schedule_T_899, _schedule_T_889)
node _schedule_T_901 = or(_schedule_T_900, _schedule_T_890)
node _schedule_T_902 = or(_schedule_T_901, _schedule_T_891)
node _schedule_T_903 = or(_schedule_T_902, _schedule_T_892)
node _schedule_T_904 = or(_schedule_T_903, _schedule_T_893)
node _schedule_T_905 = or(_schedule_T_904, _schedule_T_894)
node _schedule_T_906 = or(_schedule_T_905, _schedule_T_895)
node _schedule_T_907 = or(_schedule_T_906, _schedule_T_896)
node _schedule_T_908 = or(_schedule_T_907, _schedule_T_897)
wire _schedule_WIRE_52 : UInt<13>
connect _schedule_WIRE_52, _schedule_T_908
connect _schedule_WIRE_49.tag, _schedule_WIRE_52
node _schedule_T_909 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_910 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_911 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_912 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_913 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_914 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_915 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_916 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_917 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_918 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_919 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_920 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_921 = or(_schedule_T_909, _schedule_T_910)
node _schedule_T_922 = or(_schedule_T_921, _schedule_T_911)
node _schedule_T_923 = or(_schedule_T_922, _schedule_T_912)
node _schedule_T_924 = or(_schedule_T_923, _schedule_T_913)
node _schedule_T_925 = or(_schedule_T_924, _schedule_T_914)
node _schedule_T_926 = or(_schedule_T_925, _schedule_T_915)
node _schedule_T_927 = or(_schedule_T_926, _schedule_T_916)
node _schedule_T_928 = or(_schedule_T_927, _schedule_T_917)
node _schedule_T_929 = or(_schedule_T_928, _schedule_T_918)
node _schedule_T_930 = or(_schedule_T_929, _schedule_T_919)
node _schedule_T_931 = or(_schedule_T_930, _schedule_T_920)
wire _schedule_WIRE_53 : UInt<3>
connect _schedule_WIRE_53, _schedule_T_931
connect _schedule_WIRE_49.param, _schedule_WIRE_53
connect _schedule_WIRE_48.bits, _schedule_WIRE_49
node _schedule_T_932 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_933 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_934 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_935 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_936 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_937 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_938 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_939 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_940 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_941 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_942 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_943 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_944 = or(_schedule_T_932, _schedule_T_933)
node _schedule_T_945 = or(_schedule_T_944, _schedule_T_934)
node _schedule_T_946 = or(_schedule_T_945, _schedule_T_935)
node _schedule_T_947 = or(_schedule_T_946, _schedule_T_936)
node _schedule_T_948 = or(_schedule_T_947, _schedule_T_937)
node _schedule_T_949 = or(_schedule_T_948, _schedule_T_938)
node _schedule_T_950 = or(_schedule_T_949, _schedule_T_939)
node _schedule_T_951 = or(_schedule_T_950, _schedule_T_940)
node _schedule_T_952 = or(_schedule_T_951, _schedule_T_941)
node _schedule_T_953 = or(_schedule_T_952, _schedule_T_942)
node _schedule_T_954 = or(_schedule_T_953, _schedule_T_943)
wire _schedule_WIRE_54 : UInt<1>
connect _schedule_WIRE_54, _schedule_T_954
connect _schedule_WIRE_48.valid, _schedule_WIRE_54
connect schedule.b, _schedule_WIRE_48
wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}
wire _schedule_WIRE_56 : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}
node _schedule_T_955 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_956 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_957 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_958 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_959 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_960 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_961 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_962 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_963 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_964 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_965 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_966 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_967 = or(_schedule_T_955, _schedule_T_956)
node _schedule_T_968 = or(_schedule_T_967, _schedule_T_957)
node _schedule_T_969 = or(_schedule_T_968, _schedule_T_958)
node _schedule_T_970 = or(_schedule_T_969, _schedule_T_959)
node _schedule_T_971 = or(_schedule_T_970, _schedule_T_960)
node _schedule_T_972 = or(_schedule_T_971, _schedule_T_961)
node _schedule_T_973 = or(_schedule_T_972, _schedule_T_962)
node _schedule_T_974 = or(_schedule_T_973, _schedule_T_963)
node _schedule_T_975 = or(_schedule_T_974, _schedule_T_964)
node _schedule_T_976 = or(_schedule_T_975, _schedule_T_965)
node _schedule_T_977 = or(_schedule_T_976, _schedule_T_966)
wire _schedule_WIRE_57 : UInt<1>
connect _schedule_WIRE_57, _schedule_T_977
connect _schedule_WIRE_56.block, _schedule_WIRE_57
node _schedule_T_978 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_979 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_980 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_981 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_982 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_983 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_984 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_985 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_986 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_987 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_988 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_989 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_990 = or(_schedule_T_978, _schedule_T_979)
node _schedule_T_991 = or(_schedule_T_990, _schedule_T_980)
node _schedule_T_992 = or(_schedule_T_991, _schedule_T_981)
node _schedule_T_993 = or(_schedule_T_992, _schedule_T_982)
node _schedule_T_994 = or(_schedule_T_993, _schedule_T_983)
node _schedule_T_995 = or(_schedule_T_994, _schedule_T_984)
node _schedule_T_996 = or(_schedule_T_995, _schedule_T_985)
node _schedule_T_997 = or(_schedule_T_996, _schedule_T_986)
node _schedule_T_998 = or(_schedule_T_997, _schedule_T_987)
node _schedule_T_999 = or(_schedule_T_998, _schedule_T_988)
node _schedule_T_1000 = or(_schedule_T_999, _schedule_T_989)
wire _schedule_WIRE_58 : UInt<4>
connect _schedule_WIRE_58, _schedule_T_1000
connect _schedule_WIRE_56.source, _schedule_WIRE_58
node _schedule_T_1001 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1002 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1003 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1004 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1005 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1006 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1007 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1008 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1009 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1010 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1011 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1012 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1013 = or(_schedule_T_1001, _schedule_T_1002)
node _schedule_T_1014 = or(_schedule_T_1013, _schedule_T_1003)
node _schedule_T_1015 = or(_schedule_T_1014, _schedule_T_1004)
node _schedule_T_1016 = or(_schedule_T_1015, _schedule_T_1005)
node _schedule_T_1017 = or(_schedule_T_1016, _schedule_T_1006)
node _schedule_T_1018 = or(_schedule_T_1017, _schedule_T_1007)
node _schedule_T_1019 = or(_schedule_T_1018, _schedule_T_1008)
node _schedule_T_1020 = or(_schedule_T_1019, _schedule_T_1009)
node _schedule_T_1021 = or(_schedule_T_1020, _schedule_T_1010)
node _schedule_T_1022 = or(_schedule_T_1021, _schedule_T_1011)
node _schedule_T_1023 = or(_schedule_T_1022, _schedule_T_1012)
wire _schedule_WIRE_59 : UInt<3>
connect _schedule_WIRE_59, _schedule_T_1023
connect _schedule_WIRE_56.param, _schedule_WIRE_59
node _schedule_T_1024 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1025 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1026 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1027 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1028 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1029 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1030 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1031 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1032 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1033 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1034 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1035 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1036 = or(_schedule_T_1024, _schedule_T_1025)
node _schedule_T_1037 = or(_schedule_T_1036, _schedule_T_1026)
node _schedule_T_1038 = or(_schedule_T_1037, _schedule_T_1027)
node _schedule_T_1039 = or(_schedule_T_1038, _schedule_T_1028)
node _schedule_T_1040 = or(_schedule_T_1039, _schedule_T_1029)
node _schedule_T_1041 = or(_schedule_T_1040, _schedule_T_1030)
node _schedule_T_1042 = or(_schedule_T_1041, _schedule_T_1031)
node _schedule_T_1043 = or(_schedule_T_1042, _schedule_T_1032)
node _schedule_T_1044 = or(_schedule_T_1043, _schedule_T_1033)
node _schedule_T_1045 = or(_schedule_T_1044, _schedule_T_1034)
node _schedule_T_1046 = or(_schedule_T_1045, _schedule_T_1035)
wire _schedule_WIRE_60 : UInt<10>
connect _schedule_WIRE_60, _schedule_T_1046
connect _schedule_WIRE_56.set, _schedule_WIRE_60
node _schedule_T_1047 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1048 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1049 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1050 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1051 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1052 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1053 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1054 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1055 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1056 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1057 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1058 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1059 = or(_schedule_T_1047, _schedule_T_1048)
node _schedule_T_1060 = or(_schedule_T_1059, _schedule_T_1049)
node _schedule_T_1061 = or(_schedule_T_1060, _schedule_T_1050)
node _schedule_T_1062 = or(_schedule_T_1061, _schedule_T_1051)
node _schedule_T_1063 = or(_schedule_T_1062, _schedule_T_1052)
node _schedule_T_1064 = or(_schedule_T_1063, _schedule_T_1053)
node _schedule_T_1065 = or(_schedule_T_1064, _schedule_T_1054)
node _schedule_T_1066 = or(_schedule_T_1065, _schedule_T_1055)
node _schedule_T_1067 = or(_schedule_T_1066, _schedule_T_1056)
node _schedule_T_1068 = or(_schedule_T_1067, _schedule_T_1057)
node _schedule_T_1069 = or(_schedule_T_1068, _schedule_T_1058)
wire _schedule_WIRE_61 : UInt<13>
connect _schedule_WIRE_61, _schedule_T_1069
connect _schedule_WIRE_56.tag, _schedule_WIRE_61
connect _schedule_WIRE_55.bits, _schedule_WIRE_56
node _schedule_T_1070 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1071 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1072 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1073 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1074 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1075 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1076 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1077 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1078 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1079 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1080 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1081 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1082 = or(_schedule_T_1070, _schedule_T_1071)
node _schedule_T_1083 = or(_schedule_T_1082, _schedule_T_1072)
node _schedule_T_1084 = or(_schedule_T_1083, _schedule_T_1073)
node _schedule_T_1085 = or(_schedule_T_1084, _schedule_T_1074)
node _schedule_T_1086 = or(_schedule_T_1085, _schedule_T_1075)
node _schedule_T_1087 = or(_schedule_T_1086, _schedule_T_1076)
node _schedule_T_1088 = or(_schedule_T_1087, _schedule_T_1077)
node _schedule_T_1089 = or(_schedule_T_1088, _schedule_T_1078)
node _schedule_T_1090 = or(_schedule_T_1089, _schedule_T_1079)
node _schedule_T_1091 = or(_schedule_T_1090, _schedule_T_1080)
node _schedule_T_1092 = or(_schedule_T_1091, _schedule_T_1081)
wire _schedule_WIRE_62 : UInt<1>
connect _schedule_WIRE_62, _schedule_T_1092
connect _schedule_WIRE_55.valid, _schedule_WIRE_62
connect schedule.a, _schedule_WIRE_55
node _scheduleTag_T = bits(mshr_selectOH, 0, 0)
node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleTag_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleTag_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleTag_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleTag_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleTag_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleTag_T_12 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_13 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_14 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_15 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_16 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_17 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_18 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_19 = mux(_scheduleTag_T_7, mshrs_7.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_20 = mux(_scheduleTag_T_8, mshrs_8.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_21 = mux(_scheduleTag_T_9, mshrs_9.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_22 = mux(_scheduleTag_T_10, mshrs_10.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_23 = mux(_scheduleTag_T_11, mshrs_11.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_24 = or(_scheduleTag_T_12, _scheduleTag_T_13)
node _scheduleTag_T_25 = or(_scheduleTag_T_24, _scheduleTag_T_14)
node _scheduleTag_T_26 = or(_scheduleTag_T_25, _scheduleTag_T_15)
node _scheduleTag_T_27 = or(_scheduleTag_T_26, _scheduleTag_T_16)
node _scheduleTag_T_28 = or(_scheduleTag_T_27, _scheduleTag_T_17)
node _scheduleTag_T_29 = or(_scheduleTag_T_28, _scheduleTag_T_18)
node _scheduleTag_T_30 = or(_scheduleTag_T_29, _scheduleTag_T_19)
node _scheduleTag_T_31 = or(_scheduleTag_T_30, _scheduleTag_T_20)
node _scheduleTag_T_32 = or(_scheduleTag_T_31, _scheduleTag_T_21)
node _scheduleTag_T_33 = or(_scheduleTag_T_32, _scheduleTag_T_22)
node _scheduleTag_T_34 = or(_scheduleTag_T_33, _scheduleTag_T_23)
wire scheduleTag : UInt<13>
connect scheduleTag, _scheduleTag_T_34
node _scheduleSet_T = bits(mshr_selectOH, 0, 0)
node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleSet_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleSet_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleSet_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleSet_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleSet_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleSet_T_12 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_13 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_14 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_15 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_16 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_17 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_18 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_19 = mux(_scheduleSet_T_7, mshrs_7.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_20 = mux(_scheduleSet_T_8, mshrs_8.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_21 = mux(_scheduleSet_T_9, mshrs_9.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_22 = mux(_scheduleSet_T_10, mshrs_10.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_23 = mux(_scheduleSet_T_11, mshrs_11.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_24 = or(_scheduleSet_T_12, _scheduleSet_T_13)
node _scheduleSet_T_25 = or(_scheduleSet_T_24, _scheduleSet_T_14)
node _scheduleSet_T_26 = or(_scheduleSet_T_25, _scheduleSet_T_15)
node _scheduleSet_T_27 = or(_scheduleSet_T_26, _scheduleSet_T_16)
node _scheduleSet_T_28 = or(_scheduleSet_T_27, _scheduleSet_T_17)
node _scheduleSet_T_29 = or(_scheduleSet_T_28, _scheduleSet_T_18)
node _scheduleSet_T_30 = or(_scheduleSet_T_29, _scheduleSet_T_19)
node _scheduleSet_T_31 = or(_scheduleSet_T_30, _scheduleSet_T_20)
node _scheduleSet_T_32 = or(_scheduleSet_T_31, _scheduleSet_T_21)
node _scheduleSet_T_33 = or(_scheduleSet_T_32, _scheduleSet_T_22)
node _scheduleSet_T_34 = or(_scheduleSet_T_33, _scheduleSet_T_23)
wire scheduleSet : UInt<10>
connect scheduleSet, _scheduleSet_T_34
node _T_9 = orr(mshr_request)
when _T_9 :
node _robin_filter_T = shr(mshr_selectOH, 1)
node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T)
node _robin_filter_T_2 = shr(_robin_filter_T_1, 2)
node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2)
node _robin_filter_T_4 = shr(_robin_filter_T_3, 4)
node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4)
node _robin_filter_T_6 = shr(_robin_filter_T_5, 8)
node _robin_filter_T_7 = or(_robin_filter_T_5, _robin_filter_T_6)
node _robin_filter_T_8 = bits(_robin_filter_T_7, 11, 0)
node _robin_filter_T_9 = not(_robin_filter_T_8)
connect robin_filter, _robin_filter_T_9
connect schedule.a.bits.source, mshr_select
node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1)
node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0))
connect schedule.c.bits.source, _schedule_c_bits_source_T_1
connect schedule.d.bits.sink, mshr_select
connect sourceA.io.req.valid, schedule.a.valid
connect sourceB.io.req.valid, schedule.b.valid
connect sourceC.io.req.valid, schedule.c.valid
connect sourceD.io.req.valid, schedule.d.valid
connect sourceE.io.req.valid, schedule.e.valid
connect sourceX.io.req.valid, schedule.x.valid
connect sourceA.io.req.bits.block, schedule.a.bits.block
connect sourceA.io.req.bits.source, schedule.a.bits.source
connect sourceA.io.req.bits.param, schedule.a.bits.param
connect sourceA.io.req.bits.set, schedule.a.bits.set
connect sourceA.io.req.bits.tag, schedule.a.bits.tag
connect sourceB.io.req.bits.clients, schedule.b.bits.clients
connect sourceB.io.req.bits.set, schedule.b.bits.set
connect sourceB.io.req.bits.tag, schedule.b.bits.tag
connect sourceB.io.req.bits.param, schedule.b.bits.param
connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty
connect sourceC.io.req.bits.way, schedule.c.bits.way
connect sourceC.io.req.bits.set, schedule.c.bits.set
connect sourceC.io.req.bits.tag, schedule.c.bits.tag
connect sourceC.io.req.bits.source, schedule.c.bits.source
connect sourceC.io.req.bits.param, schedule.c.bits.param
connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode
connect sourceD.io.req.bits.bad, schedule.d.bits.bad
connect sourceD.io.req.bits.way, schedule.d.bits.way
connect sourceD.io.req.bits.sink, schedule.d.bits.sink
connect sourceD.io.req.bits.set, schedule.d.bits.set
connect sourceD.io.req.bits.put, schedule.d.bits.put
connect sourceD.io.req.bits.offset, schedule.d.bits.offset
connect sourceD.io.req.bits.tag, schedule.d.bits.tag
connect sourceD.io.req.bits.source, schedule.d.bits.source
connect sourceD.io.req.bits.size, schedule.d.bits.size
connect sourceD.io.req.bits.param, schedule.d.bits.param
connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode
connect sourceD.io.req.bits.control, schedule.d.bits.control
connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0]
connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1]
connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2]
connect sourceE.io.req.bits.sink, schedule.e.bits.sink
connect sourceX.io.req.bits.fail, schedule.x.bits.fail
connect directory.io.write.valid, schedule.dir.valid
connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag
connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients
connect directory.io.write.bits.data.state, schedule.dir.bits.data.state
connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty
connect directory.io.write.bits.way, schedule.dir.bits.way
connect directory.io.write.bits.set, schedule.dir.bits.set
node select_c = bits(mshr_selectOH, 11, 11)
node select_bc = bits(mshr_selectOH, 10, 10)
node _nestedwb_set_T = mux(select_c, mshrs_11.io.status.bits.set, mshrs_10.io.status.bits.set)
connect nestedwb.set, _nestedwb_set_T
node _nestedwb_tag_T = mux(select_c, mshrs_11.io.status.bits.tag, mshrs_10.io.status.bits.tag)
connect nestedwb.tag, _nestedwb_tag_T
node _nestedwb_b_toN_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toN_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0))
node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1)
connect nestedwb.b_toN, _nestedwb_b_toN_T_2
node _nestedwb_b_toB_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toB_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1))
node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1)
connect nestedwb.b_toB, _nestedwb_b_toB_T_2
node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T
node _nestedwb_c_set_dirty_T = and(select_c, mshrs_11.io.schedule.bits.dir.valid)
node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_11.io.schedule.bits.dir.bits.data.dirty)
connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1
wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}}
node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid)
node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid)
node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1)
connect request.valid, _request_valid_T_2
node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits)
node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T)
connect request.bits, _request_bits_T_1
node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready)
connect sinkC.io.req.ready, _sinkC_io_req_ready_T
node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1)
connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2
node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1)
node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3)
connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4
node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set)
node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T)
node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set)
node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2)
node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set)
node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4)
node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set)
node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6)
node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set)
node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8)
node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set)
node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10)
node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set)
node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12)
node _setMatches_T_14 = eq(mshrs_7.io.status.bits.set, request.bits.set)
node _setMatches_T_15 = and(mshrs_7.io.status.valid, _setMatches_T_14)
node _setMatches_T_16 = eq(mshrs_8.io.status.bits.set, request.bits.set)
node _setMatches_T_17 = and(mshrs_8.io.status.valid, _setMatches_T_16)
node _setMatches_T_18 = eq(mshrs_9.io.status.bits.set, request.bits.set)
node _setMatches_T_19 = and(mshrs_9.io.status.valid, _setMatches_T_18)
node _setMatches_T_20 = eq(mshrs_10.io.status.bits.set, request.bits.set)
node _setMatches_T_21 = and(mshrs_10.io.status.valid, _setMatches_T_20)
node _setMatches_T_22 = eq(mshrs_11.io.status.bits.set, request.bits.set)
node _setMatches_T_23 = and(mshrs_11.io.status.valid, _setMatches_T_22)
node setMatches_lo_lo_hi = cat(_setMatches_T_5, _setMatches_T_3)
node setMatches_lo_lo = cat(setMatches_lo_lo_hi, _setMatches_T_1)
node setMatches_lo_hi_hi = cat(_setMatches_T_11, _setMatches_T_9)
node setMatches_lo_hi = cat(setMatches_lo_hi_hi, _setMatches_T_7)
node setMatches_lo = cat(setMatches_lo_hi, setMatches_lo_lo)
node setMatches_hi_lo_hi = cat(_setMatches_T_17, _setMatches_T_15)
node setMatches_hi_lo = cat(setMatches_hi_lo_hi, _setMatches_T_13)
node setMatches_hi_hi_hi = cat(_setMatches_T_23, _setMatches_T_21)
node setMatches_hi_hi = cat(setMatches_hi_hi_hi, _setMatches_T_19)
node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo)
node setMatches = cat(setMatches_hi, setMatches_lo)
node _alloc_T = orr(setMatches)
node alloc = eq(_alloc_T, UInt<1>(0h0))
node _blockB_T = bits(setMatches, 0, 0)
node _blockB_T_1 = bits(setMatches, 1, 1)
node _blockB_T_2 = bits(setMatches, 2, 2)
node _blockB_T_3 = bits(setMatches, 3, 3)
node _blockB_T_4 = bits(setMatches, 4, 4)
node _blockB_T_5 = bits(setMatches, 5, 5)
node _blockB_T_6 = bits(setMatches, 6, 6)
node _blockB_T_7 = bits(setMatches, 7, 7)
node _blockB_T_8 = bits(setMatches, 8, 8)
node _blockB_T_9 = bits(setMatches, 9, 9)
node _blockB_T_10 = bits(setMatches, 10, 10)
node _blockB_T_11 = bits(setMatches, 11, 11)
node _blockB_T_12 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_13 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_14 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_15 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_16 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_17 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_18 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_19 = mux(_blockB_T_7, mshrs_7.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_20 = mux(_blockB_T_8, mshrs_8.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_21 = mux(_blockB_T_9, mshrs_9.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_22 = mux(_blockB_T_10, mshrs_10.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_23 = mux(_blockB_T_11, mshrs_11.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_24 = or(_blockB_T_12, _blockB_T_13)
node _blockB_T_25 = or(_blockB_T_24, _blockB_T_14)
node _blockB_T_26 = or(_blockB_T_25, _blockB_T_15)
node _blockB_T_27 = or(_blockB_T_26, _blockB_T_16)
node _blockB_T_28 = or(_blockB_T_27, _blockB_T_17)
node _blockB_T_29 = or(_blockB_T_28, _blockB_T_18)
node _blockB_T_30 = or(_blockB_T_29, _blockB_T_19)
node _blockB_T_31 = or(_blockB_T_30, _blockB_T_20)
node _blockB_T_32 = or(_blockB_T_31, _blockB_T_21)
node _blockB_T_33 = or(_blockB_T_32, _blockB_T_22)
node _blockB_T_34 = or(_blockB_T_33, _blockB_T_23)
wire _blockB_WIRE : UInt<1>
connect _blockB_WIRE, _blockB_T_34
node blockB = and(_blockB_WIRE, request.bits.prio[1])
node _blockC_T = bits(setMatches, 0, 0)
node _blockC_T_1 = bits(setMatches, 1, 1)
node _blockC_T_2 = bits(setMatches, 2, 2)
node _blockC_T_3 = bits(setMatches, 3, 3)
node _blockC_T_4 = bits(setMatches, 4, 4)
node _blockC_T_5 = bits(setMatches, 5, 5)
node _blockC_T_6 = bits(setMatches, 6, 6)
node _blockC_T_7 = bits(setMatches, 7, 7)
node _blockC_T_8 = bits(setMatches, 8, 8)
node _blockC_T_9 = bits(setMatches, 9, 9)
node _blockC_T_10 = bits(setMatches, 10, 10)
node _blockC_T_11 = bits(setMatches, 11, 11)
node _blockC_T_12 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_13 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_14 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_15 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_16 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_17 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_18 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_19 = mux(_blockC_T_7, mshrs_7.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_20 = mux(_blockC_T_8, mshrs_8.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_21 = mux(_blockC_T_9, mshrs_9.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_22 = mux(_blockC_T_10, mshrs_10.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_23 = mux(_blockC_T_11, mshrs_11.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_24 = or(_blockC_T_12, _blockC_T_13)
node _blockC_T_25 = or(_blockC_T_24, _blockC_T_14)
node _blockC_T_26 = or(_blockC_T_25, _blockC_T_15)
node _blockC_T_27 = or(_blockC_T_26, _blockC_T_16)
node _blockC_T_28 = or(_blockC_T_27, _blockC_T_17)
node _blockC_T_29 = or(_blockC_T_28, _blockC_T_18)
node _blockC_T_30 = or(_blockC_T_29, _blockC_T_19)
node _blockC_T_31 = or(_blockC_T_30, _blockC_T_20)
node _blockC_T_32 = or(_blockC_T_31, _blockC_T_21)
node _blockC_T_33 = or(_blockC_T_32, _blockC_T_22)
node _blockC_T_34 = or(_blockC_T_33, _blockC_T_23)
wire _blockC_WIRE : UInt<1>
connect _blockC_WIRE, _blockC_T_34
node blockC = and(_blockC_WIRE, request.bits.prio[2])
node _nestB_T = bits(setMatches, 0, 0)
node _nestB_T_1 = bits(setMatches, 1, 1)
node _nestB_T_2 = bits(setMatches, 2, 2)
node _nestB_T_3 = bits(setMatches, 3, 3)
node _nestB_T_4 = bits(setMatches, 4, 4)
node _nestB_T_5 = bits(setMatches, 5, 5)
node _nestB_T_6 = bits(setMatches, 6, 6)
node _nestB_T_7 = bits(setMatches, 7, 7)
node _nestB_T_8 = bits(setMatches, 8, 8)
node _nestB_T_9 = bits(setMatches, 9, 9)
node _nestB_T_10 = bits(setMatches, 10, 10)
node _nestB_T_11 = bits(setMatches, 11, 11)
node _nestB_T_12 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_13 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_14 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_15 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_16 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_17 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_18 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_19 = mux(_nestB_T_7, mshrs_7.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_20 = mux(_nestB_T_8, mshrs_8.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_21 = mux(_nestB_T_9, mshrs_9.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_22 = mux(_nestB_T_10, mshrs_10.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_23 = mux(_nestB_T_11, mshrs_11.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_24 = or(_nestB_T_12, _nestB_T_13)
node _nestB_T_25 = or(_nestB_T_24, _nestB_T_14)
node _nestB_T_26 = or(_nestB_T_25, _nestB_T_15)
node _nestB_T_27 = or(_nestB_T_26, _nestB_T_16)
node _nestB_T_28 = or(_nestB_T_27, _nestB_T_17)
node _nestB_T_29 = or(_nestB_T_28, _nestB_T_18)
node _nestB_T_30 = or(_nestB_T_29, _nestB_T_19)
node _nestB_T_31 = or(_nestB_T_30, _nestB_T_20)
node _nestB_T_32 = or(_nestB_T_31, _nestB_T_21)
node _nestB_T_33 = or(_nestB_T_32, _nestB_T_22)
node _nestB_T_34 = or(_nestB_T_33, _nestB_T_23)
wire _nestB_WIRE : UInt<1>
connect _nestB_WIRE, _nestB_T_34
node nestB = and(_nestB_WIRE, request.bits.prio[1])
node _nestC_T = bits(setMatches, 0, 0)
node _nestC_T_1 = bits(setMatches, 1, 1)
node _nestC_T_2 = bits(setMatches, 2, 2)
node _nestC_T_3 = bits(setMatches, 3, 3)
node _nestC_T_4 = bits(setMatches, 4, 4)
node _nestC_T_5 = bits(setMatches, 5, 5)
node _nestC_T_6 = bits(setMatches, 6, 6)
node _nestC_T_7 = bits(setMatches, 7, 7)
node _nestC_T_8 = bits(setMatches, 8, 8)
node _nestC_T_9 = bits(setMatches, 9, 9)
node _nestC_T_10 = bits(setMatches, 10, 10)
node _nestC_T_11 = bits(setMatches, 11, 11)
node _nestC_T_12 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_13 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_14 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_15 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_16 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_17 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_18 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_19 = mux(_nestC_T_7, mshrs_7.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_20 = mux(_nestC_T_8, mshrs_8.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_21 = mux(_nestC_T_9, mshrs_9.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_22 = mux(_nestC_T_10, mshrs_10.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_23 = mux(_nestC_T_11, mshrs_11.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_24 = or(_nestC_T_12, _nestC_T_13)
node _nestC_T_25 = or(_nestC_T_24, _nestC_T_14)
node _nestC_T_26 = or(_nestC_T_25, _nestC_T_15)
node _nestC_T_27 = or(_nestC_T_26, _nestC_T_16)
node _nestC_T_28 = or(_nestC_T_27, _nestC_T_17)
node _nestC_T_29 = or(_nestC_T_28, _nestC_T_18)
node _nestC_T_30 = or(_nestC_T_29, _nestC_T_19)
node _nestC_T_31 = or(_nestC_T_30, _nestC_T_20)
node _nestC_T_32 = or(_nestC_T_31, _nestC_T_21)
node _nestC_T_33 = or(_nestC_T_32, _nestC_T_22)
node _nestC_T_34 = or(_nestC_T_33, _nestC_T_23)
wire _nestC_WIRE : UInt<1>
connect _nestC_WIRE, _nestC_T_34
node nestC = and(_nestC_WIRE, request.bits.prio[2])
node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0))
node _prioFilter_T_1 = not(UInt<10>(0h0))
node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T)
node prioFilter = cat(prioFilter_hi, _prioFilter_T_1)
node lowerMatches = and(setMatches, prioFilter)
node _queue_T = orr(lowerMatches)
node _queue_T_1 = eq(nestB, UInt<1>(0h0))
node _queue_T_2 = and(_queue_T, _queue_T_1)
node _queue_T_3 = eq(nestC, UInt<1>(0h0))
node _queue_T_4 = and(_queue_T_2, _queue_T_3)
node _queue_T_5 = eq(blockB, UInt<1>(0h0))
node _queue_T_6 = and(_queue_T_4, _queue_T_5)
node _queue_T_7 = eq(blockC, UInt<1>(0h0))
node queue = and(_queue_T_6, _queue_T_7)
node _T_10 = and(request.valid, blockC)
node _T_11 = and(request.valid, nestC)
node _T_12 = and(request.valid, queue)
node _lowerMatches1_T = bits(lowerMatches, 11, 11)
node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 11)
node _lowerMatches1_T_2 = bits(lowerMatches, 10, 10)
node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 10)
node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches)
node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4)
node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH)
node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH)
node selected_requests = and(_selected_requests_T, requests.io.valid)
node _a_pop_T = bits(selected_requests, 11, 0)
node a_pop = orr(_a_pop_T)
node _b_pop_T = bits(selected_requests, 23, 12)
node b_pop = orr(_b_pop_T)
node _c_pop_T = bits(selected_requests, 35, 24)
node c_pop = orr(_c_pop_T)
node _bypassMatches_T = and(mshr_selectOH, lowerMatches1)
node _bypassMatches_T_1 = orr(_bypassMatches_T)
node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2])
node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0))
node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1])
node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0))
node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0))
node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6)
node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7)
node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8)
node _may_pop_T = or(a_pop, b_pop)
node may_pop = or(_may_pop_T, c_pop)
node _bypass_T = and(request.valid, queue)
node bypass = and(_bypass_T, bypassMatches)
node _will_reload_T = or(may_pop, bypass)
node will_reload = and(schedule.reload, _will_reload_T)
node _will_pop_T = and(schedule.reload, may_pop)
node _will_pop_T_1 = eq(bypass, UInt<1>(0h0))
node will_pop = and(_will_pop_T, _will_pop_T_1)
node _T_13 = orr(mshr_selectOH)
node _T_14 = and(_T_13, bypass)
node _T_15 = orr(mshr_selectOH)
node _T_16 = and(_T_15, will_reload)
node _T_17 = orr(mshr_selectOH)
node _T_18 = and(_T_17, will_pop)
node sel = bits(mshr_selectOH, 0, 0)
connect mshrs_0.io.schedule.ready, sel
node a_pop_1 = bits(requests.io.valid, 0, 0)
node b_pop_1 = bits(requests.io.valid, 12, 12)
node c_pop_1 = bits(requests.io.valid, 24, 24)
node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0)
node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2])
node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0))
node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1])
node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0))
node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0))
node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14)
node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15)
node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16)
node _may_pop_T_1 = or(a_pop_1, b_pop_1)
node may_pop_1 = or(_may_pop_T_1, c_pop_1)
node _bypass_T_1 = and(request.valid, queue)
node bypass_1 = and(_bypass_T_1, bypassMatches_1)
node _will_reload_T_1 = or(may_pop_1, bypass_1)
node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1)
wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE.put, request.bits.put
connect _view__WIRE.offset, request.bits.offset
connect _view__WIRE.tag, request.bits.tag
connect _view__WIRE.source, request.bits.source
connect _view__WIRE.size, request.bits.size
connect _view__WIRE.param, request.bits.param
connect _view__WIRE.opcode, request.bits.opcode
connect _view__WIRE.control, request.bits.control
connect _view__WIRE.prio, request.bits.prio
node _view__T = mux(bypass_1, _view__WIRE, requests.io.data)
connect mshrs_0.io.allocate.bits.put, _view__T.put
connect mshrs_0.io.allocate.bits.offset, _view__T.offset
connect mshrs_0.io.allocate.bits.tag, _view__T.tag
connect mshrs_0.io.allocate.bits.source, _view__T.source
connect mshrs_0.io.allocate.bits.size, _view__T.size
connect mshrs_0.io.allocate.bits.param, _view__T.param
connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode
connect mshrs_0.io.allocate.bits.control, _view__T.control
connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2]
connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set
node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag)
connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T
node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1)
connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T
node sel_1 = bits(mshr_selectOH, 1, 1)
connect mshrs_1.io.schedule.ready, sel_1
node a_pop_2 = bits(requests.io.valid, 1, 1)
node b_pop_2 = bits(requests.io.valid, 13, 13)
node c_pop_2 = bits(requests.io.valid, 25, 25)
node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1)
node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2])
node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0))
node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1])
node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0))
node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0))
node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22)
node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23)
node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24)
node _may_pop_T_2 = or(a_pop_2, b_pop_2)
node may_pop_2 = or(_may_pop_T_2, c_pop_2)
node _bypass_T_2 = and(request.valid, queue)
node bypass_2 = and(_bypass_T_2, bypassMatches_2)
node _will_reload_T_2 = or(may_pop_2, bypass_2)
node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2)
wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_1.put, request.bits.put
connect _view__WIRE_1.offset, request.bits.offset
connect _view__WIRE_1.tag, request.bits.tag
connect _view__WIRE_1.source, request.bits.source
connect _view__WIRE_1.size, request.bits.size
connect _view__WIRE_1.param, request.bits.param
connect _view__WIRE_1.opcode, request.bits.opcode
connect _view__WIRE_1.control, request.bits.control
connect _view__WIRE_1.prio, request.bits.prio
node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data)
connect mshrs_1.io.allocate.bits.put, _view__T_1.put
connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset
connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag
connect mshrs_1.io.allocate.bits.source, _view__T_1.source
connect mshrs_1.io.allocate.bits.size, _view__T_1.size
connect mshrs_1.io.allocate.bits.param, _view__T_1.param
connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode
connect mshrs_1.io.allocate.bits.control, _view__T_1.control
connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2]
connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set
node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag)
connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T
node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2)
connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T
node sel_2 = bits(mshr_selectOH, 2, 2)
connect mshrs_2.io.schedule.ready, sel_2
node a_pop_3 = bits(requests.io.valid, 2, 2)
node b_pop_3 = bits(requests.io.valid, 14, 14)
node c_pop_3 = bits(requests.io.valid, 26, 26)
node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2)
node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2])
node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0))
node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1])
node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0))
node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0))
node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30)
node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31)
node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32)
node _may_pop_T_3 = or(a_pop_3, b_pop_3)
node may_pop_3 = or(_may_pop_T_3, c_pop_3)
node _bypass_T_3 = and(request.valid, queue)
node bypass_3 = and(_bypass_T_3, bypassMatches_3)
node _will_reload_T_3 = or(may_pop_3, bypass_3)
node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3)
wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_2.put, request.bits.put
connect _view__WIRE_2.offset, request.bits.offset
connect _view__WIRE_2.tag, request.bits.tag
connect _view__WIRE_2.source, request.bits.source
connect _view__WIRE_2.size, request.bits.size
connect _view__WIRE_2.param, request.bits.param
connect _view__WIRE_2.opcode, request.bits.opcode
connect _view__WIRE_2.control, request.bits.control
connect _view__WIRE_2.prio, request.bits.prio
node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data)
connect mshrs_2.io.allocate.bits.put, _view__T_2.put
connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset
connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag
connect mshrs_2.io.allocate.bits.source, _view__T_2.source
connect mshrs_2.io.allocate.bits.size, _view__T_2.size
connect mshrs_2.io.allocate.bits.param, _view__T_2.param
connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode
connect mshrs_2.io.allocate.bits.control, _view__T_2.control
connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2]
connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set
node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag)
connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T
node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3)
connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T
node sel_3 = bits(mshr_selectOH, 3, 3)
connect mshrs_3.io.schedule.ready, sel_3
node a_pop_4 = bits(requests.io.valid, 3, 3)
node b_pop_4 = bits(requests.io.valid, 15, 15)
node c_pop_4 = bits(requests.io.valid, 27, 27)
node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3)
node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2])
node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0))
node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1])
node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0))
node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0))
node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38)
node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39)
node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40)
node _may_pop_T_4 = or(a_pop_4, b_pop_4)
node may_pop_4 = or(_may_pop_T_4, c_pop_4)
node _bypass_T_4 = and(request.valid, queue)
node bypass_4 = and(_bypass_T_4, bypassMatches_4)
node _will_reload_T_4 = or(may_pop_4, bypass_4)
node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4)
wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_3.put, request.bits.put
connect _view__WIRE_3.offset, request.bits.offset
connect _view__WIRE_3.tag, request.bits.tag
connect _view__WIRE_3.source, request.bits.source
connect _view__WIRE_3.size, request.bits.size
connect _view__WIRE_3.param, request.bits.param
connect _view__WIRE_3.opcode, request.bits.opcode
connect _view__WIRE_3.control, request.bits.control
connect _view__WIRE_3.prio, request.bits.prio
node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data)
connect mshrs_3.io.allocate.bits.put, _view__T_3.put
connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset
connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag
connect mshrs_3.io.allocate.bits.source, _view__T_3.source
connect mshrs_3.io.allocate.bits.size, _view__T_3.size
connect mshrs_3.io.allocate.bits.param, _view__T_3.param
connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode
connect mshrs_3.io.allocate.bits.control, _view__T_3.control
connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2]
connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set
node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag)
connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T
node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4)
connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T
node sel_4 = bits(mshr_selectOH, 4, 4)
connect mshrs_4.io.schedule.ready, sel_4
node a_pop_5 = bits(requests.io.valid, 4, 4)
node b_pop_5 = bits(requests.io.valid, 16, 16)
node c_pop_5 = bits(requests.io.valid, 28, 28)
node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4)
node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2])
node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0))
node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1])
node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0))
node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0))
node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46)
node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47)
node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48)
node _may_pop_T_5 = or(a_pop_5, b_pop_5)
node may_pop_5 = or(_may_pop_T_5, c_pop_5)
node _bypass_T_5 = and(request.valid, queue)
node bypass_5 = and(_bypass_T_5, bypassMatches_5)
node _will_reload_T_5 = or(may_pop_5, bypass_5)
node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5)
wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_4.put, request.bits.put
connect _view__WIRE_4.offset, request.bits.offset
connect _view__WIRE_4.tag, request.bits.tag
connect _view__WIRE_4.source, request.bits.source
connect _view__WIRE_4.size, request.bits.size
connect _view__WIRE_4.param, request.bits.param
connect _view__WIRE_4.opcode, request.bits.opcode
connect _view__WIRE_4.control, request.bits.control
connect _view__WIRE_4.prio, request.bits.prio
node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data)
connect mshrs_4.io.allocate.bits.put, _view__T_4.put
connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset
connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag
connect mshrs_4.io.allocate.bits.source, _view__T_4.source
connect mshrs_4.io.allocate.bits.size, _view__T_4.size
connect mshrs_4.io.allocate.bits.param, _view__T_4.param
connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode
connect mshrs_4.io.allocate.bits.control, _view__T_4.control
connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2]
connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set
node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag)
connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T
node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5)
connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T
node sel_5 = bits(mshr_selectOH, 5, 5)
connect mshrs_5.io.schedule.ready, sel_5
node a_pop_6 = bits(requests.io.valid, 5, 5)
node b_pop_6 = bits(requests.io.valid, 17, 17)
node c_pop_6 = bits(requests.io.valid, 29, 29)
node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5)
node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2])
node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0))
node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1])
node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0))
node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0))
node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54)
node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55)
node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56)
node _may_pop_T_6 = or(a_pop_6, b_pop_6)
node may_pop_6 = or(_may_pop_T_6, c_pop_6)
node _bypass_T_6 = and(request.valid, queue)
node bypass_6 = and(_bypass_T_6, bypassMatches_6)
node _will_reload_T_6 = or(may_pop_6, bypass_6)
node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6)
wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_5.put, request.bits.put
connect _view__WIRE_5.offset, request.bits.offset
connect _view__WIRE_5.tag, request.bits.tag
connect _view__WIRE_5.source, request.bits.source
connect _view__WIRE_5.size, request.bits.size
connect _view__WIRE_5.param, request.bits.param
connect _view__WIRE_5.opcode, request.bits.opcode
connect _view__WIRE_5.control, request.bits.control
connect _view__WIRE_5.prio, request.bits.prio
node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data)
connect mshrs_5.io.allocate.bits.put, _view__T_5.put
connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset
connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag
connect mshrs_5.io.allocate.bits.source, _view__T_5.source
connect mshrs_5.io.allocate.bits.size, _view__T_5.size
connect mshrs_5.io.allocate.bits.param, _view__T_5.param
connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode
connect mshrs_5.io.allocate.bits.control, _view__T_5.control
connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2]
connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set
node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag)
connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T
node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6)
connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T
node sel_6 = bits(mshr_selectOH, 6, 6)
connect mshrs_6.io.schedule.ready, sel_6
node a_pop_7 = bits(requests.io.valid, 6, 6)
node b_pop_7 = bits(requests.io.valid, 18, 18)
node c_pop_7 = bits(requests.io.valid, 30, 30)
node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6)
node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2])
node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0))
node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1])
node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0))
node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0))
node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62)
node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63)
node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64)
node _may_pop_T_7 = or(a_pop_7, b_pop_7)
node may_pop_7 = or(_may_pop_T_7, c_pop_7)
node _bypass_T_7 = and(request.valid, queue)
node bypass_7 = and(_bypass_T_7, bypassMatches_7)
node _will_reload_T_7 = or(may_pop_7, bypass_7)
node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7)
wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_6.put, request.bits.put
connect _view__WIRE_6.offset, request.bits.offset
connect _view__WIRE_6.tag, request.bits.tag
connect _view__WIRE_6.source, request.bits.source
connect _view__WIRE_6.size, request.bits.size
connect _view__WIRE_6.param, request.bits.param
connect _view__WIRE_6.opcode, request.bits.opcode
connect _view__WIRE_6.control, request.bits.control
connect _view__WIRE_6.prio, request.bits.prio
node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data)
connect mshrs_6.io.allocate.bits.put, _view__T_6.put
connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset
connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag
connect mshrs_6.io.allocate.bits.source, _view__T_6.source
connect mshrs_6.io.allocate.bits.size, _view__T_6.size
connect mshrs_6.io.allocate.bits.param, _view__T_6.param
connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode
connect mshrs_6.io.allocate.bits.control, _view__T_6.control
connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2]
connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set
node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag)
connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T
node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7)
connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T
node sel_7 = bits(mshr_selectOH, 7, 7)
connect mshrs_7.io.schedule.ready, sel_7
node a_pop_8 = bits(requests.io.valid, 7, 7)
node b_pop_8 = bits(requests.io.valid, 19, 19)
node c_pop_8 = bits(requests.io.valid, 31, 31)
node _bypassMatches_T_65 = bits(lowerMatches1, 7, 7)
node _bypassMatches_T_66 = or(c_pop_8, request.bits.prio[2])
node _bypassMatches_T_67 = eq(c_pop_8, UInt<1>(0h0))
node _bypassMatches_T_68 = or(b_pop_8, request.bits.prio[1])
node _bypassMatches_T_69 = eq(b_pop_8, UInt<1>(0h0))
node _bypassMatches_T_70 = eq(a_pop_8, UInt<1>(0h0))
node _bypassMatches_T_71 = mux(_bypassMatches_T_68, _bypassMatches_T_69, _bypassMatches_T_70)
node _bypassMatches_T_72 = mux(_bypassMatches_T_66, _bypassMatches_T_67, _bypassMatches_T_71)
node bypassMatches_8 = and(_bypassMatches_T_65, _bypassMatches_T_72)
node _may_pop_T_8 = or(a_pop_8, b_pop_8)
node may_pop_8 = or(_may_pop_T_8, c_pop_8)
node _bypass_T_8 = and(request.valid, queue)
node bypass_8 = and(_bypass_T_8, bypassMatches_8)
node _will_reload_T_8 = or(may_pop_8, bypass_8)
node will_reload_8 = and(mshrs_7.io.schedule.bits.reload, _will_reload_T_8)
wire _view__WIRE_7 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_7.put, request.bits.put
connect _view__WIRE_7.offset, request.bits.offset
connect _view__WIRE_7.tag, request.bits.tag
connect _view__WIRE_7.source, request.bits.source
connect _view__WIRE_7.size, request.bits.size
connect _view__WIRE_7.param, request.bits.param
connect _view__WIRE_7.opcode, request.bits.opcode
connect _view__WIRE_7.control, request.bits.control
connect _view__WIRE_7.prio, request.bits.prio
node _view__T_7 = mux(bypass_8, _view__WIRE_7, requests.io.data)
connect mshrs_7.io.allocate.bits.put, _view__T_7.put
connect mshrs_7.io.allocate.bits.offset, _view__T_7.offset
connect mshrs_7.io.allocate.bits.tag, _view__T_7.tag
connect mshrs_7.io.allocate.bits.source, _view__T_7.source
connect mshrs_7.io.allocate.bits.size, _view__T_7.size
connect mshrs_7.io.allocate.bits.param, _view__T_7.param
connect mshrs_7.io.allocate.bits.opcode, _view__T_7.opcode
connect mshrs_7.io.allocate.bits.control, _view__T_7.control
connect mshrs_7.io.allocate.bits.prio[0], _view__T_7.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], _view__T_7.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], _view__T_7.prio[2]
connect mshrs_7.io.allocate.bits.set, mshrs_7.io.status.bits.set
node _mshrs_7_io_allocate_bits_repeat_T = eq(mshrs_7.io.allocate.bits.tag, mshrs_7.io.status.bits.tag)
connect mshrs_7.io.allocate.bits.repeat, _mshrs_7_io_allocate_bits_repeat_T
node _mshrs_7_io_allocate_valid_T = and(sel_7, will_reload_8)
connect mshrs_7.io.allocate.valid, _mshrs_7_io_allocate_valid_T
node sel_8 = bits(mshr_selectOH, 8, 8)
connect mshrs_8.io.schedule.ready, sel_8
node a_pop_9 = bits(requests.io.valid, 8, 8)
node b_pop_9 = bits(requests.io.valid, 20, 20)
node c_pop_9 = bits(requests.io.valid, 32, 32)
node _bypassMatches_T_73 = bits(lowerMatches1, 8, 8)
node _bypassMatches_T_74 = or(c_pop_9, request.bits.prio[2])
node _bypassMatches_T_75 = eq(c_pop_9, UInt<1>(0h0))
node _bypassMatches_T_76 = or(b_pop_9, request.bits.prio[1])
node _bypassMatches_T_77 = eq(b_pop_9, UInt<1>(0h0))
node _bypassMatches_T_78 = eq(a_pop_9, UInt<1>(0h0))
node _bypassMatches_T_79 = mux(_bypassMatches_T_76, _bypassMatches_T_77, _bypassMatches_T_78)
node _bypassMatches_T_80 = mux(_bypassMatches_T_74, _bypassMatches_T_75, _bypassMatches_T_79)
node bypassMatches_9 = and(_bypassMatches_T_73, _bypassMatches_T_80)
node _may_pop_T_9 = or(a_pop_9, b_pop_9)
node may_pop_9 = or(_may_pop_T_9, c_pop_9)
node _bypass_T_9 = and(request.valid, queue)
node bypass_9 = and(_bypass_T_9, bypassMatches_9)
node _will_reload_T_9 = or(may_pop_9, bypass_9)
node will_reload_9 = and(mshrs_8.io.schedule.bits.reload, _will_reload_T_9)
wire _view__WIRE_8 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_8.put, request.bits.put
connect _view__WIRE_8.offset, request.bits.offset
connect _view__WIRE_8.tag, request.bits.tag
connect _view__WIRE_8.source, request.bits.source
connect _view__WIRE_8.size, request.bits.size
connect _view__WIRE_8.param, request.bits.param
connect _view__WIRE_8.opcode, request.bits.opcode
connect _view__WIRE_8.control, request.bits.control
connect _view__WIRE_8.prio, request.bits.prio
node _view__T_8 = mux(bypass_9, _view__WIRE_8, requests.io.data)
connect mshrs_8.io.allocate.bits.put, _view__T_8.put
connect mshrs_8.io.allocate.bits.offset, _view__T_8.offset
connect mshrs_8.io.allocate.bits.tag, _view__T_8.tag
connect mshrs_8.io.allocate.bits.source, _view__T_8.source
connect mshrs_8.io.allocate.bits.size, _view__T_8.size
connect mshrs_8.io.allocate.bits.param, _view__T_8.param
connect mshrs_8.io.allocate.bits.opcode, _view__T_8.opcode
connect mshrs_8.io.allocate.bits.control, _view__T_8.control
connect mshrs_8.io.allocate.bits.prio[0], _view__T_8.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], _view__T_8.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], _view__T_8.prio[2]
connect mshrs_8.io.allocate.bits.set, mshrs_8.io.status.bits.set
node _mshrs_8_io_allocate_bits_repeat_T = eq(mshrs_8.io.allocate.bits.tag, mshrs_8.io.status.bits.tag)
connect mshrs_8.io.allocate.bits.repeat, _mshrs_8_io_allocate_bits_repeat_T
node _mshrs_8_io_allocate_valid_T = and(sel_8, will_reload_9)
connect mshrs_8.io.allocate.valid, _mshrs_8_io_allocate_valid_T
node sel_9 = bits(mshr_selectOH, 9, 9)
connect mshrs_9.io.schedule.ready, sel_9
node a_pop_10 = bits(requests.io.valid, 9, 9)
node b_pop_10 = bits(requests.io.valid, 21, 21)
node c_pop_10 = bits(requests.io.valid, 33, 33)
node _bypassMatches_T_81 = bits(lowerMatches1, 9, 9)
node _bypassMatches_T_82 = or(c_pop_10, request.bits.prio[2])
node _bypassMatches_T_83 = eq(c_pop_10, UInt<1>(0h0))
node _bypassMatches_T_84 = or(b_pop_10, request.bits.prio[1])
node _bypassMatches_T_85 = eq(b_pop_10, UInt<1>(0h0))
node _bypassMatches_T_86 = eq(a_pop_10, UInt<1>(0h0))
node _bypassMatches_T_87 = mux(_bypassMatches_T_84, _bypassMatches_T_85, _bypassMatches_T_86)
node _bypassMatches_T_88 = mux(_bypassMatches_T_82, _bypassMatches_T_83, _bypassMatches_T_87)
node bypassMatches_10 = and(_bypassMatches_T_81, _bypassMatches_T_88)
node _may_pop_T_10 = or(a_pop_10, b_pop_10)
node may_pop_10 = or(_may_pop_T_10, c_pop_10)
node _bypass_T_10 = and(request.valid, queue)
node bypass_10 = and(_bypass_T_10, bypassMatches_10)
node _will_reload_T_10 = or(may_pop_10, bypass_10)
node will_reload_10 = and(mshrs_9.io.schedule.bits.reload, _will_reload_T_10)
wire _view__WIRE_9 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_9.put, request.bits.put
connect _view__WIRE_9.offset, request.bits.offset
connect _view__WIRE_9.tag, request.bits.tag
connect _view__WIRE_9.source, request.bits.source
connect _view__WIRE_9.size, request.bits.size
connect _view__WIRE_9.param, request.bits.param
connect _view__WIRE_9.opcode, request.bits.opcode
connect _view__WIRE_9.control, request.bits.control
connect _view__WIRE_9.prio, request.bits.prio
node _view__T_9 = mux(bypass_10, _view__WIRE_9, requests.io.data)
connect mshrs_9.io.allocate.bits.put, _view__T_9.put
connect mshrs_9.io.allocate.bits.offset, _view__T_9.offset
connect mshrs_9.io.allocate.bits.tag, _view__T_9.tag
connect mshrs_9.io.allocate.bits.source, _view__T_9.source
connect mshrs_9.io.allocate.bits.size, _view__T_9.size
connect mshrs_9.io.allocate.bits.param, _view__T_9.param
connect mshrs_9.io.allocate.bits.opcode, _view__T_9.opcode
connect mshrs_9.io.allocate.bits.control, _view__T_9.control
connect mshrs_9.io.allocate.bits.prio[0], _view__T_9.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], _view__T_9.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], _view__T_9.prio[2]
connect mshrs_9.io.allocate.bits.set, mshrs_9.io.status.bits.set
node _mshrs_9_io_allocate_bits_repeat_T = eq(mshrs_9.io.allocate.bits.tag, mshrs_9.io.status.bits.tag)
connect mshrs_9.io.allocate.bits.repeat, _mshrs_9_io_allocate_bits_repeat_T
node _mshrs_9_io_allocate_valid_T = and(sel_9, will_reload_10)
connect mshrs_9.io.allocate.valid, _mshrs_9_io_allocate_valid_T
node sel_10 = bits(mshr_selectOH, 10, 10)
connect mshrs_10.io.schedule.ready, sel_10
node a_pop_11 = bits(requests.io.valid, 10, 10)
node b_pop_11 = bits(requests.io.valid, 22, 22)
node c_pop_11 = bits(requests.io.valid, 34, 34)
node _bypassMatches_T_89 = bits(lowerMatches1, 10, 10)
node _bypassMatches_T_90 = or(c_pop_11, request.bits.prio[2])
node _bypassMatches_T_91 = eq(c_pop_11, UInt<1>(0h0))
node _bypassMatches_T_92 = or(b_pop_11, request.bits.prio[1])
node _bypassMatches_T_93 = eq(b_pop_11, UInt<1>(0h0))
node _bypassMatches_T_94 = eq(a_pop_11, UInt<1>(0h0))
node _bypassMatches_T_95 = mux(_bypassMatches_T_92, _bypassMatches_T_93, _bypassMatches_T_94)
node _bypassMatches_T_96 = mux(_bypassMatches_T_90, _bypassMatches_T_91, _bypassMatches_T_95)
node bypassMatches_11 = and(_bypassMatches_T_89, _bypassMatches_T_96)
node _may_pop_T_11 = or(a_pop_11, b_pop_11)
node may_pop_11 = or(_may_pop_T_11, c_pop_11)
node _bypass_T_11 = and(request.valid, queue)
node bypass_11 = and(_bypass_T_11, bypassMatches_11)
node _will_reload_T_11 = or(may_pop_11, bypass_11)
node will_reload_11 = and(mshrs_10.io.schedule.bits.reload, _will_reload_T_11)
wire _view__WIRE_10 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_10.put, request.bits.put
connect _view__WIRE_10.offset, request.bits.offset
connect _view__WIRE_10.tag, request.bits.tag
connect _view__WIRE_10.source, request.bits.source
connect _view__WIRE_10.size, request.bits.size
connect _view__WIRE_10.param, request.bits.param
connect _view__WIRE_10.opcode, request.bits.opcode
connect _view__WIRE_10.control, request.bits.control
connect _view__WIRE_10.prio, request.bits.prio
node _view__T_10 = mux(bypass_11, _view__WIRE_10, requests.io.data)
connect mshrs_10.io.allocate.bits.put, _view__T_10.put
connect mshrs_10.io.allocate.bits.offset, _view__T_10.offset
connect mshrs_10.io.allocate.bits.tag, _view__T_10.tag
connect mshrs_10.io.allocate.bits.source, _view__T_10.source
connect mshrs_10.io.allocate.bits.size, _view__T_10.size
connect mshrs_10.io.allocate.bits.param, _view__T_10.param
connect mshrs_10.io.allocate.bits.opcode, _view__T_10.opcode
connect mshrs_10.io.allocate.bits.control, _view__T_10.control
connect mshrs_10.io.allocate.bits.prio[0], _view__T_10.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], _view__T_10.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], _view__T_10.prio[2]
connect mshrs_10.io.allocate.bits.set, mshrs_10.io.status.bits.set
node _mshrs_10_io_allocate_bits_repeat_T = eq(mshrs_10.io.allocate.bits.tag, mshrs_10.io.status.bits.tag)
connect mshrs_10.io.allocate.bits.repeat, _mshrs_10_io_allocate_bits_repeat_T
node _mshrs_10_io_allocate_valid_T = and(sel_10, will_reload_11)
connect mshrs_10.io.allocate.valid, _mshrs_10_io_allocate_valid_T
node sel_11 = bits(mshr_selectOH, 11, 11)
connect mshrs_11.io.schedule.ready, sel_11
node a_pop_12 = bits(requests.io.valid, 11, 11)
node b_pop_12 = bits(requests.io.valid, 23, 23)
node c_pop_12 = bits(requests.io.valid, 35, 35)
node _bypassMatches_T_97 = bits(lowerMatches1, 11, 11)
node _bypassMatches_T_98 = or(c_pop_12, request.bits.prio[2])
node _bypassMatches_T_99 = eq(c_pop_12, UInt<1>(0h0))
node _bypassMatches_T_100 = or(b_pop_12, request.bits.prio[1])
node _bypassMatches_T_101 = eq(b_pop_12, UInt<1>(0h0))
node _bypassMatches_T_102 = eq(a_pop_12, UInt<1>(0h0))
node _bypassMatches_T_103 = mux(_bypassMatches_T_100, _bypassMatches_T_101, _bypassMatches_T_102)
node _bypassMatches_T_104 = mux(_bypassMatches_T_98, _bypassMatches_T_99, _bypassMatches_T_103)
node bypassMatches_12 = and(_bypassMatches_T_97, _bypassMatches_T_104)
node _may_pop_T_12 = or(a_pop_12, b_pop_12)
node may_pop_12 = or(_may_pop_T_12, c_pop_12)
node _bypass_T_12 = and(request.valid, queue)
node bypass_12 = and(_bypass_T_12, bypassMatches_12)
node _will_reload_T_12 = or(may_pop_12, bypass_12)
node will_reload_12 = and(mshrs_11.io.schedule.bits.reload, _will_reload_T_12)
wire _view__WIRE_11 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_11.put, request.bits.put
connect _view__WIRE_11.offset, request.bits.offset
connect _view__WIRE_11.tag, request.bits.tag
connect _view__WIRE_11.source, request.bits.source
connect _view__WIRE_11.size, request.bits.size
connect _view__WIRE_11.param, request.bits.param
connect _view__WIRE_11.opcode, request.bits.opcode
connect _view__WIRE_11.control, request.bits.control
connect _view__WIRE_11.prio, request.bits.prio
node _view__T_11 = mux(bypass_12, _view__WIRE_11, requests.io.data)
connect mshrs_11.io.allocate.bits.put, _view__T_11.put
connect mshrs_11.io.allocate.bits.offset, _view__T_11.offset
connect mshrs_11.io.allocate.bits.tag, _view__T_11.tag
connect mshrs_11.io.allocate.bits.source, _view__T_11.source
connect mshrs_11.io.allocate.bits.size, _view__T_11.size
connect mshrs_11.io.allocate.bits.param, _view__T_11.param
connect mshrs_11.io.allocate.bits.opcode, _view__T_11.opcode
connect mshrs_11.io.allocate.bits.control, _view__T_11.control
connect mshrs_11.io.allocate.bits.prio[0], _view__T_11.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], _view__T_11.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], _view__T_11.prio[2]
connect mshrs_11.io.allocate.bits.set, mshrs_11.io.status.bits.set
node _mshrs_11_io_allocate_bits_repeat_T = eq(mshrs_11.io.allocate.bits.tag, mshrs_11.io.status.bits.tag)
connect mshrs_11.io.allocate.bits.repeat, _mshrs_11_io_allocate_bits_repeat_T
node _mshrs_11_io_allocate_valid_T = and(sel_11, will_reload_12)
connect mshrs_11.io.allocate.valid, _mshrs_11_io_allocate_valid_T
node _prio_requests_T = not(requests.io.valid)
node _prio_requests_T_1 = shr(requests.io.valid, 12)
node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1)
node _prio_requests_T_3 = shr(requests.io.valid, 24)
node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3)
node prio_requests = not(_prio_requests_T_4)
node pop_index_hi = cat(mshr_selectOH, mshr_selectOH)
node _pop_index_T = cat(pop_index_hi, mshr_selectOH)
node _pop_index_T_1 = and(_pop_index_T, prio_requests)
node pop_index_hi_1 = bits(_pop_index_T_1, 35, 32)
node pop_index_lo = bits(_pop_index_T_1, 31, 0)
node _pop_index_T_2 = orr(pop_index_hi_1)
node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo)
node pop_index_hi_2 = bits(_pop_index_T_3, 31, 16)
node pop_index_lo_1 = bits(_pop_index_T_3, 15, 0)
node _pop_index_T_4 = orr(pop_index_hi_2)
node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1)
node pop_index_hi_3 = bits(_pop_index_T_5, 15, 8)
node pop_index_lo_2 = bits(_pop_index_T_5, 7, 0)
node _pop_index_T_6 = orr(pop_index_hi_3)
node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2)
node pop_index_hi_4 = bits(_pop_index_T_7, 7, 4)
node pop_index_lo_3 = bits(_pop_index_T_7, 3, 0)
node _pop_index_T_8 = orr(pop_index_hi_4)
node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3)
node pop_index_hi_5 = bits(_pop_index_T_9, 3, 2)
node pop_index_lo_4 = bits(_pop_index_T_9, 1, 0)
node _pop_index_T_10 = orr(pop_index_hi_5)
node _pop_index_T_11 = or(pop_index_hi_5, pop_index_lo_4)
node _pop_index_T_12 = bits(_pop_index_T_11, 1, 1)
node _pop_index_T_13 = cat(_pop_index_T_10, _pop_index_T_12)
node _pop_index_T_14 = cat(_pop_index_T_8, _pop_index_T_13)
node _pop_index_T_15 = cat(_pop_index_T_6, _pop_index_T_14)
node _pop_index_T_16 = cat(_pop_index_T_4, _pop_index_T_15)
node pop_index = cat(_pop_index_T_2, _pop_index_T_16)
connect requests.io.pop.valid, will_pop
connect requests.io.pop.bits, pop_index
node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag)
node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop)
node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch)
node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch)
node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag)
node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T)
node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1)
node mshr_validOH_lo_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid)
node mshr_validOH_lo_lo = cat(mshr_validOH_lo_lo_hi, mshrs_0.io.status.valid)
node mshr_validOH_lo_hi_hi = cat(mshrs_5.io.status.valid, mshrs_4.io.status.valid)
node mshr_validOH_lo_hi = cat(mshr_validOH_lo_hi_hi, mshrs_3.io.status.valid)
node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshr_validOH_lo_lo)
node mshr_validOH_hi_lo_hi = cat(mshrs_8.io.status.valid, mshrs_7.io.status.valid)
node mshr_validOH_hi_lo = cat(mshr_validOH_hi_lo_hi, mshrs_6.io.status.valid)
node mshr_validOH_hi_hi_hi = cat(mshrs_11.io.status.valid, mshrs_10.io.status.valid)
node mshr_validOH_hi_hi = cat(mshr_validOH_hi_hi_hi, mshrs_9.io.status.valid)
node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo)
node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo)
node _mshr_free_T = not(mshr_validOH)
node _mshr_free_T_1 = and(_mshr_free_T, prioFilter)
node mshr_free = orr(_mshr_free_T_1)
node bypassQueue = and(schedule.reload, bypassMatches)
node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T)
node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free)
node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3)
node _request_alloc_cases_T_5 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5)
node _request_alloc_cases_T_7 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7)
node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8)
node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10)
node _request_alloc_cases_T_12 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12)
node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13)
node _request_ready_T = or(bypassQueue, requests.io.push.ready)
node _request_ready_T_1 = and(queue, _request_ready_T)
node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1)
connect request.ready, _request_ready_T_2
node alloc_uses_directory = and(request.valid, request_alloc_cases)
node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory)
connect directory.io.read.valid, _directory_io_read_valid_T
node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set)
connect directory.io.read.bits.set, _directory_io_read_bits_set_T
node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag)
connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T
node _requests_io_push_valid_T = and(request.valid, queue)
node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0))
node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1)
connect requests.io.push.valid, _requests_io_push_valid_T_2
connect requests.io.push.bits.data.put, request.bits.put
connect requests.io.push.bits.data.offset, request.bits.offset
connect requests.io.push.bits.data.tag, request.bits.tag
connect requests.io.push.bits.data.source, request.bits.source
connect requests.io.push.bits.data.size, request.bits.size
connect requests.io.push.bits.data.param, request.bits.param
connect requests.io.push.bits.data.opcode, request.bits.opcode
connect requests.io.push.bits.data.control, request.bits.control
connect requests.io.push.bits.data.prio[0], request.bits.prio[0]
connect requests.io.push.bits.data.prio[1], request.bits.prio[1]
connect requests.io.push.bits.data.prio[2], request.bits.prio[2]
node _requests_io_push_bits_index_T = shl(lowerMatches1, 0)
node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 11, 8)
node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 7, 0)
node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi)
node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo)
node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 7, 4)
node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 3, 0)
node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1)
node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1)
node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_4, 3, 2)
node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_4, 1, 0)
node _requests_io_push_bits_index_T_5 = orr(requests_io_push_bits_index_hi_2)
node _requests_io_push_bits_index_T_6 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2)
node _requests_io_push_bits_index_T_7 = bits(_requests_io_push_bits_index_T_6, 1, 1)
node _requests_io_push_bits_index_T_8 = cat(_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7)
node _requests_io_push_bits_index_T_9 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8)
node _requests_io_push_bits_index_T_10 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9)
node _requests_io_push_bits_index_T_11 = shl(lowerMatches1, 12)
node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_11, 23, 16)
node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_11, 15, 0)
node _requests_io_push_bits_index_T_12 = orr(requests_io_push_bits_index_hi_3)
node _requests_io_push_bits_index_T_13 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3)
node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_13, 15, 8)
node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_13, 7, 0)
node _requests_io_push_bits_index_T_14 = orr(requests_io_push_bits_index_hi_4)
node _requests_io_push_bits_index_T_15 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4)
node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_15, 7, 4)
node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_15, 3, 0)
node _requests_io_push_bits_index_T_16 = orr(requests_io_push_bits_index_hi_5)
node _requests_io_push_bits_index_T_17 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5)
node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_17, 3, 2)
node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_17, 1, 0)
node _requests_io_push_bits_index_T_18 = orr(requests_io_push_bits_index_hi_6)
node _requests_io_push_bits_index_T_19 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6)
node _requests_io_push_bits_index_T_20 = bits(_requests_io_push_bits_index_T_19, 1, 1)
node _requests_io_push_bits_index_T_21 = cat(_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20)
node _requests_io_push_bits_index_T_22 = cat(_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21)
node _requests_io_push_bits_index_T_23 = cat(_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22)
node _requests_io_push_bits_index_T_24 = cat(_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23)
node _requests_io_push_bits_index_T_25 = shl(lowerMatches1, 24)
node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_25, 35, 32)
node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_25, 31, 0)
node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_7)
node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7)
node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_27, 31, 16)
node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_27, 15, 0)
node _requests_io_push_bits_index_T_28 = orr(requests_io_push_bits_index_hi_8)
node _requests_io_push_bits_index_T_29 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8)
node requests_io_push_bits_index_hi_9 = bits(_requests_io_push_bits_index_T_29, 15, 8)
node requests_io_push_bits_index_lo_9 = bits(_requests_io_push_bits_index_T_29, 7, 0)
node _requests_io_push_bits_index_T_30 = orr(requests_io_push_bits_index_hi_9)
node _requests_io_push_bits_index_T_31 = or(requests_io_push_bits_index_hi_9, requests_io_push_bits_index_lo_9)
node requests_io_push_bits_index_hi_10 = bits(_requests_io_push_bits_index_T_31, 7, 4)
node requests_io_push_bits_index_lo_10 = bits(_requests_io_push_bits_index_T_31, 3, 0)
node _requests_io_push_bits_index_T_32 = orr(requests_io_push_bits_index_hi_10)
node _requests_io_push_bits_index_T_33 = or(requests_io_push_bits_index_hi_10, requests_io_push_bits_index_lo_10)
node requests_io_push_bits_index_hi_11 = bits(_requests_io_push_bits_index_T_33, 3, 2)
node requests_io_push_bits_index_lo_11 = bits(_requests_io_push_bits_index_T_33, 1, 0)
node _requests_io_push_bits_index_T_34 = orr(requests_io_push_bits_index_hi_11)
node _requests_io_push_bits_index_T_35 = or(requests_io_push_bits_index_hi_11, requests_io_push_bits_index_lo_11)
node _requests_io_push_bits_index_T_36 = bits(_requests_io_push_bits_index_T_35, 1, 1)
node _requests_io_push_bits_index_T_37 = cat(_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36)
node _requests_io_push_bits_index_T_38 = cat(_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37)
node _requests_io_push_bits_index_T_39 = cat(_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38)
node _requests_io_push_bits_index_T_40 = cat(_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39)
node _requests_io_push_bits_index_T_41 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40)
node _requests_io_push_bits_index_T_42 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_10, UInt<1>(0h0))
node _requests_io_push_bits_index_T_43 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_24, UInt<1>(0h0))
node _requests_io_push_bits_index_T_44 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_41, UInt<1>(0h0))
node _requests_io_push_bits_index_T_45 = or(_requests_io_push_bits_index_T_42, _requests_io_push_bits_index_T_43)
node _requests_io_push_bits_index_T_46 = or(_requests_io_push_bits_index_T_45, _requests_io_push_bits_index_T_44)
wire _requests_io_push_bits_index_WIRE : UInt<6>
connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_46
connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE
node _mshr_insertOH_T = not(mshr_validOH)
node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1)
node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 11, 0)
node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2)
node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2)
node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 11, 0)
node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5)
node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4)
node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 11, 0)
node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8)
node _mshr_insertOH_T_10 = shl(_mshr_insertOH_T_9, 8)
node _mshr_insertOH_T_11 = bits(_mshr_insertOH_T_10, 11, 0)
node _mshr_insertOH_T_12 = or(_mshr_insertOH_T_9, _mshr_insertOH_T_11)
node _mshr_insertOH_T_13 = bits(_mshr_insertOH_T_12, 11, 0)
node _mshr_insertOH_T_14 = shl(_mshr_insertOH_T_13, 1)
node _mshr_insertOH_T_15 = not(_mshr_insertOH_T_14)
node _mshr_insertOH_T_16 = not(mshr_validOH)
node _mshr_insertOH_T_17 = and(_mshr_insertOH_T_15, _mshr_insertOH_T_16)
node mshr_insertOH = and(_mshr_insertOH_T_17, prioFilter)
node _T_19 = bits(mshr_insertOH, 0, 0)
node _T_20 = bits(mshr_insertOH, 1, 1)
node _T_21 = bits(mshr_insertOH, 2, 2)
node _T_22 = bits(mshr_insertOH, 3, 3)
node _T_23 = bits(mshr_insertOH, 4, 4)
node _T_24 = bits(mshr_insertOH, 5, 5)
node _T_25 = bits(mshr_insertOH, 6, 6)
node _T_26 = bits(mshr_insertOH, 7, 7)
node _T_27 = bits(mshr_insertOH, 8, 8)
node _T_28 = bits(mshr_insertOH, 9, 9)
node _T_29 = bits(mshr_insertOH, 10, 10)
node _T_30 = bits(mshr_insertOH, 11, 11)
node _T_31 = bits(mshr_insertOH, 12, 12)
node _T_32 = and(request.valid, alloc)
node _T_33 = and(_T_32, _T_19)
node _T_34 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_35 = and(_T_33, _T_34)
when _T_35 :
connect mshrs_0.io.allocate.valid, UInt<1>(0h1)
connect mshrs_0.io.allocate.bits.set, request.bits.set
connect mshrs_0.io.allocate.bits.put, request.bits.put
connect mshrs_0.io.allocate.bits.offset, request.bits.offset
connect mshrs_0.io.allocate.bits.tag, request.bits.tag
connect mshrs_0.io.allocate.bits.source, request.bits.source
connect mshrs_0.io.allocate.bits.size, request.bits.size
connect mshrs_0.io.allocate.bits.param, request.bits.param
connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_0.io.allocate.bits.control, request.bits.control
connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_36 = and(request.valid, alloc)
node _T_37 = and(_T_36, _T_20)
node _T_38 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect mshrs_1.io.allocate.valid, UInt<1>(0h1)
connect mshrs_1.io.allocate.bits.set, request.bits.set
connect mshrs_1.io.allocate.bits.put, request.bits.put
connect mshrs_1.io.allocate.bits.offset, request.bits.offset
connect mshrs_1.io.allocate.bits.tag, request.bits.tag
connect mshrs_1.io.allocate.bits.source, request.bits.source
connect mshrs_1.io.allocate.bits.size, request.bits.size
connect mshrs_1.io.allocate.bits.param, request.bits.param
connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_1.io.allocate.bits.control, request.bits.control
connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_40 = and(request.valid, alloc)
node _T_41 = and(_T_40, _T_21)
node _T_42 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
when _T_43 :
connect mshrs_2.io.allocate.valid, UInt<1>(0h1)
connect mshrs_2.io.allocate.bits.set, request.bits.set
connect mshrs_2.io.allocate.bits.put, request.bits.put
connect mshrs_2.io.allocate.bits.offset, request.bits.offset
connect mshrs_2.io.allocate.bits.tag, request.bits.tag
connect mshrs_2.io.allocate.bits.source, request.bits.source
connect mshrs_2.io.allocate.bits.size, request.bits.size
connect mshrs_2.io.allocate.bits.param, request.bits.param
connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_2.io.allocate.bits.control, request.bits.control
connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_44 = and(request.valid, alloc)
node _T_45 = and(_T_44, _T_22)
node _T_46 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
when _T_47 :
connect mshrs_3.io.allocate.valid, UInt<1>(0h1)
connect mshrs_3.io.allocate.bits.set, request.bits.set
connect mshrs_3.io.allocate.bits.put, request.bits.put
connect mshrs_3.io.allocate.bits.offset, request.bits.offset
connect mshrs_3.io.allocate.bits.tag, request.bits.tag
connect mshrs_3.io.allocate.bits.source, request.bits.source
connect mshrs_3.io.allocate.bits.size, request.bits.size
connect mshrs_3.io.allocate.bits.param, request.bits.param
connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_3.io.allocate.bits.control, request.bits.control
connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_48 = and(request.valid, alloc)
node _T_49 = and(_T_48, _T_23)
node _T_50 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect mshrs_4.io.allocate.valid, UInt<1>(0h1)
connect mshrs_4.io.allocate.bits.set, request.bits.set
connect mshrs_4.io.allocate.bits.put, request.bits.put
connect mshrs_4.io.allocate.bits.offset, request.bits.offset
connect mshrs_4.io.allocate.bits.tag, request.bits.tag
connect mshrs_4.io.allocate.bits.source, request.bits.source
connect mshrs_4.io.allocate.bits.size, request.bits.size
connect mshrs_4.io.allocate.bits.param, request.bits.param
connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_4.io.allocate.bits.control, request.bits.control
connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_52 = and(request.valid, alloc)
node _T_53 = and(_T_52, _T_24)
node _T_54 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect mshrs_5.io.allocate.valid, UInt<1>(0h1)
connect mshrs_5.io.allocate.bits.set, request.bits.set
connect mshrs_5.io.allocate.bits.put, request.bits.put
connect mshrs_5.io.allocate.bits.offset, request.bits.offset
connect mshrs_5.io.allocate.bits.tag, request.bits.tag
connect mshrs_5.io.allocate.bits.source, request.bits.source
connect mshrs_5.io.allocate.bits.size, request.bits.size
connect mshrs_5.io.allocate.bits.param, request.bits.param
connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_5.io.allocate.bits.control, request.bits.control
connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_56 = and(request.valid, alloc)
node _T_57 = and(_T_56, _T_25)
node _T_58 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
when _T_59 :
connect mshrs_6.io.allocate.valid, UInt<1>(0h1)
connect mshrs_6.io.allocate.bits.set, request.bits.set
connect mshrs_6.io.allocate.bits.put, request.bits.put
connect mshrs_6.io.allocate.bits.offset, request.bits.offset
connect mshrs_6.io.allocate.bits.tag, request.bits.tag
connect mshrs_6.io.allocate.bits.source, request.bits.source
connect mshrs_6.io.allocate.bits.size, request.bits.size
connect mshrs_6.io.allocate.bits.param, request.bits.param
connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_6.io.allocate.bits.control, request.bits.control
connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_60 = and(request.valid, alloc)
node _T_61 = and(_T_60, _T_26)
node _T_62 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect mshrs_7.io.allocate.valid, UInt<1>(0h1)
connect mshrs_7.io.allocate.bits.set, request.bits.set
connect mshrs_7.io.allocate.bits.put, request.bits.put
connect mshrs_7.io.allocate.bits.offset, request.bits.offset
connect mshrs_7.io.allocate.bits.tag, request.bits.tag
connect mshrs_7.io.allocate.bits.source, request.bits.source
connect mshrs_7.io.allocate.bits.size, request.bits.size
connect mshrs_7.io.allocate.bits.param, request.bits.param
connect mshrs_7.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_7.io.allocate.bits.control, request.bits.control
connect mshrs_7.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_7.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_64 = and(request.valid, alloc)
node _T_65 = and(_T_64, _T_27)
node _T_66 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_67 = and(_T_65, _T_66)
when _T_67 :
connect mshrs_8.io.allocate.valid, UInt<1>(0h1)
connect mshrs_8.io.allocate.bits.set, request.bits.set
connect mshrs_8.io.allocate.bits.put, request.bits.put
connect mshrs_8.io.allocate.bits.offset, request.bits.offset
connect mshrs_8.io.allocate.bits.tag, request.bits.tag
connect mshrs_8.io.allocate.bits.source, request.bits.source
connect mshrs_8.io.allocate.bits.size, request.bits.size
connect mshrs_8.io.allocate.bits.param, request.bits.param
connect mshrs_8.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_8.io.allocate.bits.control, request.bits.control
connect mshrs_8.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_8.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_68 = and(request.valid, alloc)
node _T_69 = and(_T_68, _T_28)
node _T_70 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_71 = and(_T_69, _T_70)
when _T_71 :
connect mshrs_9.io.allocate.valid, UInt<1>(0h1)
connect mshrs_9.io.allocate.bits.set, request.bits.set
connect mshrs_9.io.allocate.bits.put, request.bits.put
connect mshrs_9.io.allocate.bits.offset, request.bits.offset
connect mshrs_9.io.allocate.bits.tag, request.bits.tag
connect mshrs_9.io.allocate.bits.source, request.bits.source
connect mshrs_9.io.allocate.bits.size, request.bits.size
connect mshrs_9.io.allocate.bits.param, request.bits.param
connect mshrs_9.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_9.io.allocate.bits.control, request.bits.control
connect mshrs_9.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_9.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_72 = and(request.valid, alloc)
node _T_73 = and(_T_72, _T_29)
node _T_74 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_75 = and(_T_73, _T_74)
when _T_75 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_76 = and(request.valid, alloc)
node _T_77 = and(_T_76, _T_30)
node _T_78 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_79 = and(_T_77, _T_78)
when _T_79 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_80 = and(request.valid, nestB)
node _T_81 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_84 = and(_T_82, _T_83)
node _T_85 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_86 = and(_T_84, _T_85)
when _T_86 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_87 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf
assert(clock, _T_87, UInt<1>(0h1), "") : assert
connect mshrs_10.io.allocate.bits.prio[0], UInt<1>(0h0)
node _T_91 = and(request.valid, nestC)
node _T_92 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
when _T_95 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_96 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1
assert(clock, _T_96, UInt<1>(0h1), "") : assert_1
node _T_100 = eq(request.bits.prio[1], UInt<1>(0h0))
node _T_101 = asUInt(reset)
node _T_102 = eq(_T_101, UInt<1>(0h0))
when _T_102 :
node _T_103 = eq(_T_100, UInt<1>(0h0))
when _T_103 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2
assert(clock, _T_100, UInt<1>(0h1), "") : assert_2
connect mshrs_11.io.allocate.bits.prio[0], UInt<1>(0h0)
connect mshrs_11.io.allocate.bits.prio[1], UInt<1>(0h0)
node _dirTarget_T = mux(nestB, UInt<11>(0h400), UInt<12>(0h800))
node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T)
node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0))
node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T)
reg directoryFanout : UInt, clock
connect directoryFanout, _directoryFanout_T_1
node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0)
connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T
connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1)
connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T
connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2)
connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T
connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3)
connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T
connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4)
connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T
connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5)
connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T
connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6)
connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T
connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_7_io_directory_valid_T = bits(directoryFanout, 7, 7)
connect mshrs_7.io.directory.valid, _mshrs_7_io_directory_valid_T
connect mshrs_7.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_7.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_7.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_7.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_7.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_7.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_8_io_directory_valid_T = bits(directoryFanout, 8, 8)
connect mshrs_8.io.directory.valid, _mshrs_8_io_directory_valid_T
connect mshrs_8.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_8.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_8.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_8.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_8.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_8.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_9_io_directory_valid_T = bits(directoryFanout, 9, 9)
connect mshrs_9.io.directory.valid, _mshrs_9_io_directory_valid_T
connect mshrs_9.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_9.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_9.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_9.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_9.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_9.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_10_io_directory_valid_T = bits(directoryFanout, 10, 10)
connect mshrs_10.io.directory.valid, _mshrs_10_io_directory_valid_T
connect mshrs_10.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_10.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_10.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_10.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_10.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_10.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_11_io_directory_valid_T = bits(directoryFanout, 11, 11)
connect mshrs_11.io.directory.valid, _mshrs_11_io_directory_valid_T
connect mshrs_11.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_11.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_11.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_11.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_11.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_11.io.directory.bits.dirty, directory.io.result.bits.dirty
node _sinkC_io_way_T = eq(mshrs_10.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_1 = and(mshrs_10.io.status.valid, _sinkC_io_way_T)
node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2)
node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4)
node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6)
node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8)
node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10)
node _sinkC_io_way_T_12 = eq(mshrs_5.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_13 = and(mshrs_5.io.status.valid, _sinkC_io_way_T_12)
node _sinkC_io_way_T_14 = eq(mshrs_6.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_15 = and(mshrs_6.io.status.valid, _sinkC_io_way_T_14)
node _sinkC_io_way_T_16 = eq(mshrs_7.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_17 = and(mshrs_7.io.status.valid, _sinkC_io_way_T_16)
node _sinkC_io_way_T_18 = eq(mshrs_8.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_19 = and(mshrs_8.io.status.valid, _sinkC_io_way_T_18)
node _sinkC_io_way_T_20 = eq(mshrs_9.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_21 = and(mshrs_9.io.status.valid, _sinkC_io_way_T_20)
node _sinkC_io_way_T_22 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_23 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_24 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_25 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_26 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_27 = mux(_sinkC_io_way_T_13, mshrs_5.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_28 = mux(_sinkC_io_way_T_15, mshrs_6.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_29 = mux(_sinkC_io_way_T_17, mshrs_7.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_30 = mux(_sinkC_io_way_T_19, mshrs_8.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_31 = mux(_sinkC_io_way_T_21, mshrs_9.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_32 = or(_sinkC_io_way_T_22, _sinkC_io_way_T_23)
node _sinkC_io_way_T_33 = or(_sinkC_io_way_T_32, _sinkC_io_way_T_24)
node _sinkC_io_way_T_34 = or(_sinkC_io_way_T_33, _sinkC_io_way_T_25)
node _sinkC_io_way_T_35 = or(_sinkC_io_way_T_34, _sinkC_io_way_T_26)
node _sinkC_io_way_T_36 = or(_sinkC_io_way_T_35, _sinkC_io_way_T_27)
node _sinkC_io_way_T_37 = or(_sinkC_io_way_T_36, _sinkC_io_way_T_28)
node _sinkC_io_way_T_38 = or(_sinkC_io_way_T_37, _sinkC_io_way_T_29)
node _sinkC_io_way_T_39 = or(_sinkC_io_way_T_38, _sinkC_io_way_T_30)
node _sinkC_io_way_T_40 = or(_sinkC_io_way_T_39, _sinkC_io_way_T_31)
wire _sinkC_io_way_WIRE : UInt<3>
connect _sinkC_io_way_WIRE, _sinkC_io_way_T_40
node _sinkC_io_way_T_41 = mux(_sinkC_io_way_T_1, mshrs_10.io.status.bits.way, _sinkC_io_way_WIRE)
connect sinkC.io.way, _sinkC_io_way_T_41
wire _sinkD_io_way_WIRE : UInt<3>[12]
connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way
connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way
connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way
connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way
connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way
connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way
connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way
connect _sinkD_io_way_WIRE[7], mshrs_7.io.status.bits.way
connect _sinkD_io_way_WIRE[8], mshrs_8.io.status.bits.way
connect _sinkD_io_way_WIRE[9], mshrs_9.io.status.bits.way
connect _sinkD_io_way_WIRE[10], mshrs_10.io.status.bits.way
connect _sinkD_io_way_WIRE[11], mshrs_11.io.status.bits.way
connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source]
wire _sinkD_io_set_WIRE : UInt<10>[12]
connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set
connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set
connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set
connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set
connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set
connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set
connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set
connect _sinkD_io_set_WIRE[7], mshrs_7.io.status.bits.set
connect _sinkD_io_set_WIRE[8], mshrs_8.io.status.bits.set
connect _sinkD_io_set_WIRE[9], mshrs_9.io.status.bits.set
connect _sinkD_io_set_WIRE[10], mshrs_10.io.status.bits.set
connect _sinkD_io_set_WIRE[11], mshrs_11.io.status.bits.set
connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source]
connect sinkA.io.pb_pop, sourceD.io.pb_pop
connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt
connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask
connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data
connect sinkC.io.rel_pop, sourceD.io.rel_pop
connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt
connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data
connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr
connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data
connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr
connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data
connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr
connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr
connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr
connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data
connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data
connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data
connect sourceD.io.evict_req.way, sourceC.io.evict_req.way
connect sourceD.io.evict_req.set, sourceC.io.evict_req.set
connect sourceD.io.grant_req.way, sinkD.io.grant_req.way
connect sourceD.io.grant_req.set, sinkD.io.grant_req.set
connect sourceC.io.evict_safe, sourceD.io.evict_safe
connect sinkD.io.grant_safe, sourceD.io.grant_safe | module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7]
input clock, // @[Scheduler.scala:27:7]
input reset, // @[Scheduler.scala:27:7]
output io_in_a_ready, // @[Scheduler.scala:29:14]
input io_in_a_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14]
input [15:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14]
input [127:0] io_in_a_bits_data, // @[Scheduler.scala:29:14]
input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_b_ready, // @[Scheduler.scala:29:14]
output io_in_b_valid, // @[Scheduler.scala:29:14]
output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14]
output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14]
output io_in_c_ready, // @[Scheduler.scala:29:14]
input io_in_c_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14]
input [127:0] io_in_c_bits_data, // @[Scheduler.scala:29:14]
input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_d_ready, // @[Scheduler.scala:29:14]
output io_in_d_valid, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14]
output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14]
output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14]
output [3:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14]
output io_in_d_bits_denied, // @[Scheduler.scala:29:14]
output [127:0] io_in_d_bits_data, // @[Scheduler.scala:29:14]
output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_e_valid, // @[Scheduler.scala:29:14]
input [3:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14]
input io_out_a_ready, // @[Scheduler.scala:29:14]
output io_out_a_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_a_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14]
output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14]
output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14]
output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_out_c_ready, // @[Scheduler.scala:29:14]
output io_out_c_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_c_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14]
output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14]
output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_d_ready, // @[Scheduler.scala:29:14]
input io_out_d_valid, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14]
input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14]
input [3:0] io_out_d_bits_source, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14]
input io_out_d_bits_denied, // @[Scheduler.scala:29:14]
input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14]
input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_e_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14]
output io_req_ready, // @[Scheduler.scala:29:14]
input io_req_valid, // @[Scheduler.scala:29:14]
input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14]
output io_resp_valid // @[Scheduler.scala:29:14]
);
wire [12:0] mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73]
wire [12:0] mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74]
wire [12:0] mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [5:0] request_bits_put; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21]
wire [12:0] request_bits_tag; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_source; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_size; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_param; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21]
wire request_bits_control; // @[Scheduler.scala:163:21]
wire request_bits_prio_2; // @[Scheduler.scala:163:21]
wire request_bits_prio_0; // @[Scheduler.scala:163:21]
wire _mshrs_11_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _requests_io_push_ready; // @[Scheduler.scala:70:24]
wire [35:0] _requests_io_valid; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24]
wire _requests_io_data_control; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24]
wire [12:0] _requests_io_data_tag; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24]
wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27]
wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27]
wire [127:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27]
wire _directory_io_write_ready; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25]
wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25]
wire [12:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25]
wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25]
wire _directory_io_ready; // @[Scheduler.scala:68:25]
wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21]
wire [12:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21]
wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21]
wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21]
wire [3:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21]
wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_source; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21]
wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21]
wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21]
wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21]
wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21]
wire [12:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21]
wire [12:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21]
wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21]
wire [12:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21]
wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21]
wire [127:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21]
wire [15:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21]
wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23]
wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23]
wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23]
wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23]
wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23]
wire [127:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23]
wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23]
wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23]
wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23]
wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23]
wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23]
wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23]
wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23]
wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23]
wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7]
wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7]
wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7]
wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7]
wire [3:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7]
wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7]
wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7]
wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7]
wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_196 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_197 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_198 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_199 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_200 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_201 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_202 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_203 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_204 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_205 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_206 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_207 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_208 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_209 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_210 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_211 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_212 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_213 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_214 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_215 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_216 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_217 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_218 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_574 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_575 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_598 = 1'h0; // @[Mux.scala:30:73]
wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21]
wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22]
wire blockB = 1'h0; // @[Scheduler.scala:175:70]
wire nestB = 1'h0; // @[Scheduler.scala:179:70]
wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_7_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_8_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_9_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_10_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_11_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13]
wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56]
wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7]
wire [5:0] io_in_b_bits_source = 6'h20; // @[Scheduler.scala:27:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Scheduler.scala:27:7]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Scheduler.scala:27:7]
wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7]
wire _mshr_request_T_253 = 1'h1; // @[Scheduler.scala:107:28]
wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22]
wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35]
wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55]
wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7]
wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_b_bits_source = 4'h0; // @[Scheduler.scala:27:7]
wire [3:0] _schedule_WIRE_19_bits_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_334 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_335 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_336 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_337 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_338 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_339 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_340 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_341 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_342 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_343 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_344 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_345 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_346 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_347 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_348 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_349 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_350 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_351 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_352 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_353 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_354 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_355 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_356 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_23 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_748 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_749 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_750 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_751 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_752 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_753 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_754 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_755 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_756 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_757 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_758 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_759 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_760 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_761 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_762 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_763 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_764 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_765 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_766 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_767 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_768 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_769 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_770 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_44 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_55_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_56_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_978 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_979 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_980 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_981 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_982 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_983 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_984 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_985 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_986 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_987 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_988 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_989 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_990 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_991 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_992 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_993 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_994 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_995 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_996 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_997 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_998 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_999 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_1000 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_58 = 4'h0; // @[Mux.scala:30:73]
wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_0 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_1 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_2 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_3 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_4 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_5 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_6 = 8'h0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7]
wire [11:0] _lowerMatches1_T_1 = 12'h800; // @[Scheduler.scala:200:43]
wire [11:0] _dirTarget_T = 12'h800; // @[Scheduler.scala:306:48]
wire [4:0] _requests_io_push_bits_index_T_43 = 5'h0; // @[Mux.scala:30:73]
wire [9:0] _prioFilter_T_1 = 10'h3FF; // @[Scheduler.scala:182:69]
wire [10:0] _lowerMatches1_T_3 = 11'h400; // @[Scheduler.scala:201:43]
wire io_in_a_ready_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7]
wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7]
wire io_in_b_valid_0; // @[Scheduler.scala:27:7]
wire io_in_c_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7]
wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7]
wire [3:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7]
wire [127:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_in_d_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_a_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_c_valid_0; // @[Scheduler.scala:27:7]
wire io_out_d_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_out_e_valid_0; // @[Scheduler.scala:27:7]
wire io_req_ready_0; // @[Scheduler.scala:27:7]
wire io_resp_valid_0; // @[Scheduler.scala:27:7]
wire [9:0] _nestedwb_set_T; // @[Scheduler.scala:155:24]
wire [12:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24]
wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75]
wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75]
wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37]
wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75]
wire [9:0] nestedwb_set; // @[Scheduler.scala:75:22]
wire [12:0] nestedwb_tag; // @[Scheduler.scala:75:22]
wire nestedwb_b_toN; // @[Scheduler.scala:75:22]
wire nestedwb_b_toB; // @[Scheduler.scala:75:22]
wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22]
wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22]
wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h0; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h0; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h1; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h1; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h2; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h2; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h3; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h3; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h4; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h4; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h5; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h5; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h6; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h6; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_7_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_7_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_7_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_7_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_7_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h7; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_7_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_7_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_7_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h7; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_7_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_7_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_8_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_8_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_8_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_8_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_8_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h8; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_8_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_8_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_8_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h8; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_8_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_8_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_9_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_9_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_9_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_9_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_9_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h9; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_9_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_9_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_9_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h9; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_9_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_9_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_10_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_10_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_10_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_10_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hA; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_10_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_10_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_10_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hA; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_10_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_10_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_11_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_11_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_11_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_11_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hB; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_11_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_11_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_11_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hB; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_11_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_11_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_1 = _mshrs_10_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_3 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_5 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_7 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_9 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_11 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_13 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_15 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_17 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_19 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_20 = _mshrs_5_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_21 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_20; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_22 = _mshrs_5_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_23 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_22; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_5 = _mshr_stall_abc_T_21 | _mshr_stall_abc_T_23; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_24 = _mshrs_6_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_25 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_24; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_26 = _mshrs_6_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_27 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_26; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_6 = _mshr_stall_abc_T_25 | _mshr_stall_abc_T_27; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_28 = _mshrs_7_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_29 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_28; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_30 = _mshrs_7_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_31 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_30; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_7 = _mshr_stall_abc_T_29 | _mshr_stall_abc_T_31; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_32 = _mshrs_8_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_33 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_32; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_34 = _mshrs_8_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_35 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_34; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_8 = _mshr_stall_abc_T_33 | _mshr_stall_abc_T_35; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_36 = _mshrs_9_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_37 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_36; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_38 = _mshrs_9_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_39 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_38; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_9 = _mshr_stall_abc_T_37 | _mshr_stall_abc_T_39; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_bc_T = _mshrs_10_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58]
wire mshr_stall_bc = _mshrs_11_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}]
wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_5 = mshr_stall_abc_5 & _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_6 = mshr_stall_abc_6 & _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_7 = mshr_stall_abc_7 & _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_8 = mshr_stall_abc_8 & _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_9 = mshr_stall_abc_9 & _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_115 = ~mshr_stall_abc_5; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_138 = ~mshr_stall_abc_6; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_139 = _mshrs_6_io_schedule_valid & _mshr_request_T_138; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_161 = ~mshr_stall_abc_7; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_162 = _mshrs_7_io_schedule_valid & _mshr_request_T_161; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_163 = ~_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_164 = _sourceA_io_req_ready | _mshr_request_T_163; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_165 = _mshr_request_T_162 & _mshr_request_T_164; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_166 = ~_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_167 = _sourceB_io_req_ready | _mshr_request_T_166; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_169 = ~_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_170 = _sourceC_io_req_ready | _mshr_request_T_169; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_172 = ~_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_173 = _sourceD_io_req_ready | _mshr_request_T_172; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_175 = ~_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_176 = _sourceE_io_req_ready | _mshr_request_T_175; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_178 = ~_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_179 = _sourceX_io_req_ready | _mshr_request_T_178; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_180 = _mshr_request_T_177 & _mshr_request_T_179; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_181 = ~_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_182 = _directory_io_write_ready | _mshr_request_T_181; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_183 = _mshr_request_T_180 & _mshr_request_T_182; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_184 = ~mshr_stall_abc_8; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_185 = _mshrs_8_io_schedule_valid & _mshr_request_T_184; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_186 = ~_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_187 = _sourceA_io_req_ready | _mshr_request_T_186; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_188 = _mshr_request_T_185 & _mshr_request_T_187; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_189 = ~_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_190 = _sourceB_io_req_ready | _mshr_request_T_189; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_192 = ~_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_193 = _sourceC_io_req_ready | _mshr_request_T_192; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_195 = ~_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_196 = _sourceD_io_req_ready | _mshr_request_T_195; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_198 = ~_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_199 = _sourceE_io_req_ready | _mshr_request_T_198; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_201 = ~_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_202 = _sourceX_io_req_ready | _mshr_request_T_201; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_203 = _mshr_request_T_200 & _mshr_request_T_202; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_204 = ~_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_205 = _directory_io_write_ready | _mshr_request_T_204; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_206 = _mshr_request_T_203 & _mshr_request_T_205; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_207 = ~mshr_stall_abc_9; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_208 = _mshrs_9_io_schedule_valid & _mshr_request_T_207; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_209 = ~_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_210 = _sourceA_io_req_ready | _mshr_request_T_209; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_211 = _mshr_request_T_208 & _mshr_request_T_210; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_212 = ~_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_213 = _sourceB_io_req_ready | _mshr_request_T_212; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_215 = ~_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_216 = _sourceC_io_req_ready | _mshr_request_T_215; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_218 = ~_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_219 = _sourceD_io_req_ready | _mshr_request_T_218; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_221 = ~_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_222 = _sourceE_io_req_ready | _mshr_request_T_221; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_224 = ~_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_225 = _sourceX_io_req_ready | _mshr_request_T_224; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_226 = _mshr_request_T_223 & _mshr_request_T_225; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_227 = ~_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_228 = _directory_io_write_ready | _mshr_request_T_227; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_229 = _mshr_request_T_226 & _mshr_request_T_228; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_230 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28]
wire _mshr_request_T_231 = _mshrs_10_io_schedule_valid & _mshr_request_T_230; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_232 = ~_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_233 = _sourceA_io_req_ready | _mshr_request_T_232; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_234 = _mshr_request_T_231 & _mshr_request_T_233; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_235 = ~_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_236 = _sourceB_io_req_ready | _mshr_request_T_235; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_238 = ~_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_239 = _sourceC_io_req_ready | _mshr_request_T_238; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_241 = ~_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_242 = _sourceD_io_req_ready | _mshr_request_T_241; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_244 = ~_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_245 = _sourceE_io_req_ready | _mshr_request_T_244; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_247 = ~_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_248 = _sourceX_io_req_ready | _mshr_request_T_247; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_249 = _mshr_request_T_246 & _mshr_request_T_248; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_250 = ~_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_251 = _directory_io_write_ready | _mshr_request_T_250; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_252 = _mshr_request_T_249 & _mshr_request_T_251; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_255 = ~_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_256 = _sourceA_io_req_ready | _mshr_request_T_255; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_254; // @[Scheduler.scala:107:25]
wire _mshr_request_T_257 = _mshr_request_T_254 & _mshr_request_T_256; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_258 = ~_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_259 = _sourceB_io_req_ready | _mshr_request_T_258; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_261 = ~_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_262 = _sourceC_io_req_ready | _mshr_request_T_261; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_264 = ~_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_265 = _sourceD_io_req_ready | _mshr_request_T_264; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_267 = ~_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_268 = _sourceE_io_req_ready | _mshr_request_T_267; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_270 = ~_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_271 = _sourceX_io_req_ready | _mshr_request_T_270; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_272 = _mshr_request_T_269 & _mshr_request_T_271; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_273 = ~_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_274 = _directory_io_write_ready | _mshr_request_T_273; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_275 = _mshr_request_T_272 & _mshr_request_T_274; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire [1:0] mshr_request_lo_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_lo = {mshr_request_lo_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_lo_hi_hi = {_mshr_request_T_137, _mshr_request_T_114}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_hi = {mshr_request_lo_hi_hi, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_lo = {mshr_request_lo_hi, mshr_request_lo_lo}; // @[Scheduler.scala:106:25]
wire [1:0] mshr_request_hi_lo_hi = {_mshr_request_T_206, _mshr_request_T_183}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_lo = {mshr_request_hi_lo_hi, _mshr_request_T_160}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_hi_hi_hi = {_mshr_request_T_275, _mshr_request_T_252}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_hi = {mshr_request_hi_hi_hi, _mshr_request_T_229}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25]
wire [11:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25]
reg [11:0] robin_filter; // @[Scheduler.scala:118:29]
wire [11:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54]
wire [23:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}]
wire [24:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48]
wire [23:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}]
wire [25:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}]
wire [27:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}]
wire [31:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}]
wire [39:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_13 = _mshr_selectOH2_T_12[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 | _mshr_selectOH2_T_13; // @[package.scala:253:{43,53}]
wire [23:0] _mshr_selectOH2_T_15 = _mshr_selectOH2_T_14; // @[package.scala:253:43, :254:17]
wire [24:0] _mshr_selectOH2_T_16 = {_mshr_selectOH2_T_15, 1'h0}; // @[package.scala:254:17]
wire [24:0] _mshr_selectOH2_T_17 = ~_mshr_selectOH2_T_16; // @[Scheduler.scala:120:{24,48}]
wire [24:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_17[23:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}]
wire [11:0] _mshr_selectOH_T = mshr_selectOH2[23:12]; // @[Scheduler.scala:120:54, :121:37]
wire [11:0] _mshr_selectOH_T_1 = mshr_selectOH2[11:0]; // @[Scheduler.scala:120:54, :121:86]
wire [11:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}]
wire [3:0] mshr_select_hi = mshr_selectOH[11:8]; // @[OneHot.scala:30:18]
wire [7:0] mshr_select_lo = mshr_selectOH[7:0]; // @[OneHot.scala:31:18]
wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _mshr_select_T_1 = {4'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] mshr_select_hi_1 = _mshr_select_T_1[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] mshr_select_lo_1 = _mshr_select_T_1[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] mshr_select_hi_2 = _mshr_select_T_3[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] mshr_select_lo_2 = _mshr_select_T_3[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_4 = |mshr_select_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _mshr_select_T_5 = mshr_select_hi_2 | mshr_select_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _mshr_select_T_6 = _mshr_select_T_5[1]; // @[OneHot.scala:32:28]
wire [1:0] _mshr_select_T_7 = {_mshr_select_T_4, _mshr_select_T_6}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _mshr_select_T_8 = {_mshr_select_T_2, _mshr_select_T_7}; // @[OneHot.scala:32:{10,14}]
wire [3:0] mshr_select = {_mshr_select_T, _mshr_select_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10]
wire [3:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10]
wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _schedule_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleTag_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleSet_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire sel_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _schedule_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleTag_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleSet_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire sel_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _schedule_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleTag_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleSet_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire sel_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _schedule_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleTag_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleSet_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire select_bc = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire sel_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _schedule_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleTag_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleSet_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire select_c = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire sel_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [3:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32]
wire [12:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE; // @[Mux.scala:30:73]
wire [12:0] schedule_a_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_a_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73]
wire schedule_a_bits_block; // @[Mux.scala:30:73]
wire schedule_a_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73]
wire [12:0] schedule_b_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_b_bits_set; // @[Mux.scala:30:73]
wire schedule_b_bits_clients; // @[Mux.scala:30:73]
wire schedule_b_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_source; // @[Mux.scala:30:73]
wire [12:0] schedule_c_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_c_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_way; // @[Mux.scala:30:73]
wire schedule_c_bits_dirty; // @[Mux.scala:30:73]
wire schedule_c_valid; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_0; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_1; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_2; // @[Mux.scala:30:73]
wire schedule_d_bits_control; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73]
wire [12:0] schedule_d_bits_tag; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73]
wire [9:0] schedule_d_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_way; // @[Mux.scala:30:73]
wire schedule_d_bits_bad; // @[Mux.scala:30:73]
wire schedule_d_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73]
wire schedule_e_valid; // @[Mux.scala:30:73]
wire schedule_x_valid; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_dir_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_dir_bits_way; // @[Mux.scala:30:73]
wire schedule_dir_valid; // @[Mux.scala:30:73]
wire schedule_reload; // @[Mux.scala:30:73]
wire _schedule_T_12 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_13 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_14 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_15 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_16 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_17 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_18 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_19 = _schedule_T_7 & _mshrs_7_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_20 = _schedule_T_8 & _mshrs_8_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_21 = _schedule_T_9 & _mshrs_9_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_22 = _schedule_T_10 & _mshrs_10_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_23 = _schedule_T_11 & _mshrs_11_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_24 = _schedule_T_12 | _schedule_T_13; // @[Mux.scala:30:73]
wire _schedule_T_25 = _schedule_T_24 | _schedule_T_14; // @[Mux.scala:30:73]
wire _schedule_T_26 = _schedule_T_25 | _schedule_T_15; // @[Mux.scala:30:73]
wire _schedule_T_27 = _schedule_T_26 | _schedule_T_16; // @[Mux.scala:30:73]
wire _schedule_T_28 = _schedule_T_27 | _schedule_T_17; // @[Mux.scala:30:73]
wire _schedule_T_29 = _schedule_T_28 | _schedule_T_18; // @[Mux.scala:30:73]
wire _schedule_T_30 = _schedule_T_29 | _schedule_T_19; // @[Mux.scala:30:73]
wire _schedule_T_31 = _schedule_T_30 | _schedule_T_20; // @[Mux.scala:30:73]
wire _schedule_T_32 = _schedule_T_31 | _schedule_T_21; // @[Mux.scala:30:73]
wire _schedule_T_33 = _schedule_T_32 | _schedule_T_22; // @[Mux.scala:30:73]
wire _schedule_T_34 = _schedule_T_33 | _schedule_T_23; // @[Mux.scala:30:73]
assign _schedule_WIRE = _schedule_T_34; // @[Mux.scala:30:73]
assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73]
wire _schedule_WIRE_10; // @[Mux.scala:30:73]
assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73]
assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73]
assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_9; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_8; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE_7; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_5; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_4; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_35 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_36 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_37 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_38 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_39 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_40 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_41 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_42 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_43 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_44 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_45 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_46 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_47 = _schedule_T_35 | _schedule_T_36; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_48 = _schedule_T_47 | _schedule_T_37; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_49 = _schedule_T_48 | _schedule_T_38; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_50 = _schedule_T_49 | _schedule_T_39; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_51 = _schedule_T_50 | _schedule_T_40; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_52 = _schedule_T_51 | _schedule_T_41; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_53 = _schedule_T_52 | _schedule_T_42; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_43; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_44; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_45; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_4 = _schedule_T_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73]
wire _schedule_T_58 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_59 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_60 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_61 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_62 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_63 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_64 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_65 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_66 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_67 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_68 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_69 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_70 = _schedule_T_58 | _schedule_T_59; // @[Mux.scala:30:73]
wire _schedule_T_71 = _schedule_T_70 | _schedule_T_60; // @[Mux.scala:30:73]
wire _schedule_T_72 = _schedule_T_71 | _schedule_T_61; // @[Mux.scala:30:73]
wire _schedule_T_73 = _schedule_T_72 | _schedule_T_62; // @[Mux.scala:30:73]
wire _schedule_T_74 = _schedule_T_73 | _schedule_T_63; // @[Mux.scala:30:73]
wire _schedule_T_75 = _schedule_T_74 | _schedule_T_64; // @[Mux.scala:30:73]
wire _schedule_T_76 = _schedule_T_75 | _schedule_T_65; // @[Mux.scala:30:73]
wire _schedule_T_77 = _schedule_T_76 | _schedule_T_66; // @[Mux.scala:30:73]
wire _schedule_T_78 = _schedule_T_77 | _schedule_T_67; // @[Mux.scala:30:73]
wire _schedule_T_79 = _schedule_T_78 | _schedule_T_68; // @[Mux.scala:30:73]
wire _schedule_T_80 = _schedule_T_79 | _schedule_T_69; // @[Mux.scala:30:73]
assign _schedule_WIRE_5 = _schedule_T_80; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_81 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_82 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_83 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_84 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_85 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_86 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_87 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_88 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_89 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_90 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_91 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_92 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_93 = _schedule_T_81 | _schedule_T_82; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_83; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_84; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_85; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_86; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_98 = _schedule_T_97 | _schedule_T_87; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_99 = _schedule_T_98 | _schedule_T_88; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_100 = _schedule_T_99 | _schedule_T_89; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_101 = _schedule_T_100 | _schedule_T_90; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_102 = _schedule_T_101 | _schedule_T_91; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_103 = _schedule_T_102 | _schedule_T_92; // @[Mux.scala:30:73]
assign _schedule_WIRE_6 = _schedule_T_103; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73]
wire _schedule_T_104 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_105 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_106 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_107 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_108 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_109 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_110 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_111 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_112 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_113 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_114 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_115 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_116 = _schedule_T_104 | _schedule_T_105; // @[Mux.scala:30:73]
wire _schedule_T_117 = _schedule_T_116 | _schedule_T_106; // @[Mux.scala:30:73]
wire _schedule_T_118 = _schedule_T_117 | _schedule_T_107; // @[Mux.scala:30:73]
wire _schedule_T_119 = _schedule_T_118 | _schedule_T_108; // @[Mux.scala:30:73]
wire _schedule_T_120 = _schedule_T_119 | _schedule_T_109; // @[Mux.scala:30:73]
wire _schedule_T_121 = _schedule_T_120 | _schedule_T_110; // @[Mux.scala:30:73]
wire _schedule_T_122 = _schedule_T_121 | _schedule_T_111; // @[Mux.scala:30:73]
wire _schedule_T_123 = _schedule_T_122 | _schedule_T_112; // @[Mux.scala:30:73]
wire _schedule_T_124 = _schedule_T_123 | _schedule_T_113; // @[Mux.scala:30:73]
wire _schedule_T_125 = _schedule_T_124 | _schedule_T_114; // @[Mux.scala:30:73]
wire _schedule_T_126 = _schedule_T_125 | _schedule_T_115; // @[Mux.scala:30:73]
assign _schedule_WIRE_7 = _schedule_T_126; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_127 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_128 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_129 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_130 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_131 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_132 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_133 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_134 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_135 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_136 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_137 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_138 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_139 = _schedule_T_127 | _schedule_T_128; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_140 = _schedule_T_139 | _schedule_T_129; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_141 = _schedule_T_140 | _schedule_T_130; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_142 = _schedule_T_141 | _schedule_T_131; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_143 = _schedule_T_142 | _schedule_T_132; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_144 = _schedule_T_143 | _schedule_T_133; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_134; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_135; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_136; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_137; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_138; // @[Mux.scala:30:73]
assign _schedule_WIRE_8 = _schedule_T_149; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_150 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_151 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_152 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_153 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_154 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_155 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_156 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_157 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_158 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_159 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_160 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_161 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_162 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_163 = _schedule_T_162 | _schedule_T_152; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_164 = _schedule_T_163 | _schedule_T_153; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_165 = _schedule_T_164 | _schedule_T_154; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_166 = _schedule_T_165 | _schedule_T_155; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_167 = _schedule_T_166 | _schedule_T_156; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_168 = _schedule_T_167 | _schedule_T_157; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_169 = _schedule_T_168 | _schedule_T_158; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_170 = _schedule_T_169 | _schedule_T_159; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_171 = _schedule_T_170 | _schedule_T_160; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_172 = _schedule_T_171 | _schedule_T_161; // @[Mux.scala:30:73]
assign _schedule_WIRE_9 = _schedule_T_172; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73]
wire _schedule_T_173 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_174 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_175 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_176 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_177 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_178 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_179 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_180 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_181 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_182 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_183 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_184 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_185 = _schedule_T_173 | _schedule_T_174; // @[Mux.scala:30:73]
wire _schedule_T_186 = _schedule_T_185 | _schedule_T_175; // @[Mux.scala:30:73]
wire _schedule_T_187 = _schedule_T_186 | _schedule_T_176; // @[Mux.scala:30:73]
wire _schedule_T_188 = _schedule_T_187 | _schedule_T_177; // @[Mux.scala:30:73]
wire _schedule_T_189 = _schedule_T_188 | _schedule_T_178; // @[Mux.scala:30:73]
wire _schedule_T_190 = _schedule_T_189 | _schedule_T_179; // @[Mux.scala:30:73]
wire _schedule_T_191 = _schedule_T_190 | _schedule_T_180; // @[Mux.scala:30:73]
wire _schedule_T_192 = _schedule_T_191 | _schedule_T_181; // @[Mux.scala:30:73]
wire _schedule_T_193 = _schedule_T_192 | _schedule_T_182; // @[Mux.scala:30:73]
wire _schedule_T_194 = _schedule_T_193 | _schedule_T_183; // @[Mux.scala:30:73]
wire _schedule_T_195 = _schedule_T_194 | _schedule_T_184; // @[Mux.scala:30:73]
assign _schedule_WIRE_10 = _schedule_T_195; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73]
wire _schedule_WIRE_14; // @[Mux.scala:30:73]
assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_T_219 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_220 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_221 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_222 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_223 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_224 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_225 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_226 = _schedule_T_7 & _mshrs_7_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_227 = _schedule_T_8 & _mshrs_8_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_228 = _schedule_T_9 & _mshrs_9_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_229 = _schedule_T_10 & _mshrs_10_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_230 = _schedule_T_11 & _mshrs_11_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_231 = _schedule_T_219 | _schedule_T_220; // @[Mux.scala:30:73]
wire _schedule_T_232 = _schedule_T_231 | _schedule_T_221; // @[Mux.scala:30:73]
wire _schedule_T_233 = _schedule_T_232 | _schedule_T_222; // @[Mux.scala:30:73]
wire _schedule_T_234 = _schedule_T_233 | _schedule_T_223; // @[Mux.scala:30:73]
wire _schedule_T_235 = _schedule_T_234 | _schedule_T_224; // @[Mux.scala:30:73]
wire _schedule_T_236 = _schedule_T_235 | _schedule_T_225; // @[Mux.scala:30:73]
wire _schedule_T_237 = _schedule_T_236 | _schedule_T_226; // @[Mux.scala:30:73]
wire _schedule_T_238 = _schedule_T_237 | _schedule_T_227; // @[Mux.scala:30:73]
wire _schedule_T_239 = _schedule_T_238 | _schedule_T_228; // @[Mux.scala:30:73]
wire _schedule_T_240 = _schedule_T_239 | _schedule_T_229; // @[Mux.scala:30:73]
wire _schedule_T_241 = _schedule_T_240 | _schedule_T_230; // @[Mux.scala:30:73]
assign _schedule_WIRE_14 = _schedule_T_241; // @[Mux.scala:30:73]
assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73]
wire _schedule_WIRE_18; // @[Mux.scala:30:73]
assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_242 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_243 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_244 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_245 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_246 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_247 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_248 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_249 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_250 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_251 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_252 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_253 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_254 = _schedule_T_242 | _schedule_T_243; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_255 = _schedule_T_254 | _schedule_T_244; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_256 = _schedule_T_255 | _schedule_T_245; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_257 = _schedule_T_256 | _schedule_T_246; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_258 = _schedule_T_257 | _schedule_T_247; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_259 = _schedule_T_258 | _schedule_T_248; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_260 = _schedule_T_259 | _schedule_T_249; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_261 = _schedule_T_260 | _schedule_T_250; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_251; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_252; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_253; // @[Mux.scala:30:73]
assign _schedule_WIRE_17 = _schedule_T_264; // @[Mux.scala:30:73]
assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73]
wire _schedule_T_265 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_266 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_267 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_268 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_269 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_270 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_271 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_272 = _schedule_T_7 & _mshrs_7_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_273 = _schedule_T_8 & _mshrs_8_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_274 = _schedule_T_9 & _mshrs_9_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_275 = _schedule_T_10 & _mshrs_10_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_276 = _schedule_T_11 & _mshrs_11_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_277 = _schedule_T_265 | _schedule_T_266; // @[Mux.scala:30:73]
wire _schedule_T_278 = _schedule_T_277 | _schedule_T_267; // @[Mux.scala:30:73]
wire _schedule_T_279 = _schedule_T_278 | _schedule_T_268; // @[Mux.scala:30:73]
wire _schedule_T_280 = _schedule_T_279 | _schedule_T_269; // @[Mux.scala:30:73]
wire _schedule_T_281 = _schedule_T_280 | _schedule_T_270; // @[Mux.scala:30:73]
wire _schedule_T_282 = _schedule_T_281 | _schedule_T_271; // @[Mux.scala:30:73]
wire _schedule_T_283 = _schedule_T_282 | _schedule_T_272; // @[Mux.scala:30:73]
wire _schedule_T_284 = _schedule_T_283 | _schedule_T_273; // @[Mux.scala:30:73]
wire _schedule_T_285 = _schedule_T_284 | _schedule_T_274; // @[Mux.scala:30:73]
wire _schedule_T_286 = _schedule_T_285 | _schedule_T_275; // @[Mux.scala:30:73]
wire _schedule_T_287 = _schedule_T_286 | _schedule_T_276; // @[Mux.scala:30:73]
assign _schedule_WIRE_18 = _schedule_T_287; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73]
wire _schedule_WIRE_37; // @[Mux.scala:30:73]
assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_control; // @[Mux.scala:30:73]
assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73]
assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73]
assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73]
assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73]
assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73]
assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73]
assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_0; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_1; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_2; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_32; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_27; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_24; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_22; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_21; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
wire _schedule_T_288 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_289 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_290 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_291 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_292 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_293 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_294 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_295 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_296 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_297 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_298 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_299 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_300 = _schedule_T_288 | _schedule_T_289; // @[Mux.scala:30:73]
wire _schedule_T_301 = _schedule_T_300 | _schedule_T_290; // @[Mux.scala:30:73]
wire _schedule_T_302 = _schedule_T_301 | _schedule_T_291; // @[Mux.scala:30:73]
wire _schedule_T_303 = _schedule_T_302 | _schedule_T_292; // @[Mux.scala:30:73]
wire _schedule_T_304 = _schedule_T_303 | _schedule_T_293; // @[Mux.scala:30:73]
wire _schedule_T_305 = _schedule_T_304 | _schedule_T_294; // @[Mux.scala:30:73]
wire _schedule_T_306 = _schedule_T_305 | _schedule_T_295; // @[Mux.scala:30:73]
wire _schedule_T_307 = _schedule_T_306 | _schedule_T_296; // @[Mux.scala:30:73]
wire _schedule_T_308 = _schedule_T_307 | _schedule_T_297; // @[Mux.scala:30:73]
wire _schedule_T_309 = _schedule_T_308 | _schedule_T_298; // @[Mux.scala:30:73]
wire _schedule_T_310 = _schedule_T_309 | _schedule_T_299; // @[Mux.scala:30:73]
assign _schedule_WIRE_21 = _schedule_T_310; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_311 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_312 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_313 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_314 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_315 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_316 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_317 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_318 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_319 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_320 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_321 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_322 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_323 = _schedule_T_311 | _schedule_T_312; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_324 = _schedule_T_323 | _schedule_T_313; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_325 = _schedule_T_324 | _schedule_T_314; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_326 = _schedule_T_325 | _schedule_T_315; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_327 = _schedule_T_326 | _schedule_T_316; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_328 = _schedule_T_327 | _schedule_T_317; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_329 = _schedule_T_328 | _schedule_T_318; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_330 = _schedule_T_329 | _schedule_T_319; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_331 = _schedule_T_330 | _schedule_T_320; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_332 = _schedule_T_331 | _schedule_T_321; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_333 = _schedule_T_332 | _schedule_T_322; // @[Mux.scala:30:73]
assign _schedule_WIRE_22 = _schedule_T_333; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_357 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_358 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_359 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_360 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_361 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_362 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_363 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_364 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_365 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_366 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_367 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_368 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_369 = _schedule_T_357 | _schedule_T_358; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_370 = _schedule_T_369 | _schedule_T_359; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_371 = _schedule_T_370 | _schedule_T_360; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_372 = _schedule_T_371 | _schedule_T_361; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_373 = _schedule_T_372 | _schedule_T_362; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_374 = _schedule_T_373 | _schedule_T_363; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_375 = _schedule_T_374 | _schedule_T_364; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_376 = _schedule_T_375 | _schedule_T_365; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_377 = _schedule_T_376 | _schedule_T_366; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_378 = _schedule_T_377 | _schedule_T_367; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_379 = _schedule_T_378 | _schedule_T_368; // @[Mux.scala:30:73]
assign _schedule_WIRE_24 = _schedule_T_379; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_380 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_381 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_382 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_383 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_384 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_385 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_386 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_387 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_388 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_389 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_390 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_391 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_392 = _schedule_T_380 | _schedule_T_381; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_382; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_383; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_384; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_385; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_397 = _schedule_T_396 | _schedule_T_386; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_398 = _schedule_T_397 | _schedule_T_387; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_399 = _schedule_T_398 | _schedule_T_388; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_400 = _schedule_T_399 | _schedule_T_389; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_401 = _schedule_T_400 | _schedule_T_390; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_402 = _schedule_T_401 | _schedule_T_391; // @[Mux.scala:30:73]
assign _schedule_WIRE_25 = _schedule_T_402; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_403 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_404 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_405 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_406 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_407 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_408 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_409 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_410 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_411 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_412 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_413 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_414 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_415 = _schedule_T_403 | _schedule_T_404; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_416 = _schedule_T_415 | _schedule_T_405; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_417 = _schedule_T_416 | _schedule_T_406; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_407; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_408; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_409; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_410; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_411; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_423 = _schedule_T_422 | _schedule_T_412; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_424 = _schedule_T_423 | _schedule_T_413; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_425 = _schedule_T_424 | _schedule_T_414; // @[Mux.scala:30:73]
assign _schedule_WIRE_26 = _schedule_T_425; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_426 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_427 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_428 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_429 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_430 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_431 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_432 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_433 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_434 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_435 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_436 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_437 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_438 = _schedule_T_426 | _schedule_T_427; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_439 = _schedule_T_438 | _schedule_T_428; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_440 = _schedule_T_439 | _schedule_T_429; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_441 = _schedule_T_440 | _schedule_T_430; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_442 = _schedule_T_441 | _schedule_T_431; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_443 = _schedule_T_442 | _schedule_T_432; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_433; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_434; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_435; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_436; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_437; // @[Mux.scala:30:73]
assign _schedule_WIRE_27 = _schedule_T_448; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_456 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_457 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_458 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_459 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_460 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_461 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_462 = _schedule_T_461 | _schedule_T_451; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_463 = _schedule_T_462 | _schedule_T_452; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_464 = _schedule_T_463 | _schedule_T_453; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_465 = _schedule_T_464 | _schedule_T_454; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_466 = _schedule_T_465 | _schedule_T_455; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_467 = _schedule_T_466 | _schedule_T_456; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_468 = _schedule_T_467 | _schedule_T_457; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_469 = _schedule_T_468 | _schedule_T_458; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_470 = _schedule_T_469 | _schedule_T_459; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_471 = _schedule_T_470 | _schedule_T_460; // @[Mux.scala:30:73]
assign _schedule_WIRE_28 = _schedule_T_471; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_472 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_473 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_474 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_475 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_476 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_477 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_478 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_479 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_480 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_481 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_482 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_483 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_484 = _schedule_T_472 | _schedule_T_473; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_474; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_475; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_476; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_488 = _schedule_T_487 | _schedule_T_477; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_489 = _schedule_T_488 | _schedule_T_478; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_490 = _schedule_T_489 | _schedule_T_479; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_491 = _schedule_T_490 | _schedule_T_480; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_492 = _schedule_T_491 | _schedule_T_481; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_493 = _schedule_T_492 | _schedule_T_482; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_494 = _schedule_T_493 | _schedule_T_483; // @[Mux.scala:30:73]
assign _schedule_WIRE_29 = _schedule_T_494; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_495 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_496 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_497 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_498 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_499 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_500 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_501 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_502 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_503 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_504 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_505 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_506 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_507 = _schedule_T_495 | _schedule_T_496; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_508 = _schedule_T_507 | _schedule_T_497; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_498; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_499; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_500; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_501; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_502; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_514 = _schedule_T_513 | _schedule_T_503; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_515 = _schedule_T_514 | _schedule_T_504; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_516 = _schedule_T_515 | _schedule_T_505; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_517 = _schedule_T_516 | _schedule_T_506; // @[Mux.scala:30:73]
assign _schedule_WIRE_30 = _schedule_T_517; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_518 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_519 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_520 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_521 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_522 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_523 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_524 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_525 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_526 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_527 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_528 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_529 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_530 = _schedule_T_518 | _schedule_T_519; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_531 = _schedule_T_530 | _schedule_T_520; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_532 = _schedule_T_531 | _schedule_T_521; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_533 = _schedule_T_532 | _schedule_T_522; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_534 = _schedule_T_533 | _schedule_T_523; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_535 = _schedule_T_534 | _schedule_T_524; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_536 = _schedule_T_535 | _schedule_T_525; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_537 = _schedule_T_536 | _schedule_T_526; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_538 = _schedule_T_537 | _schedule_T_527; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_539 = _schedule_T_538 | _schedule_T_528; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_540 = _schedule_T_539 | _schedule_T_529; // @[Mux.scala:30:73]
assign _schedule_WIRE_31 = _schedule_T_540; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73]
wire _schedule_T_541 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_542 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_543 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_544 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_545 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_546 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_547 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_548 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_549 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_550 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_551 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_552 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_553 = _schedule_T_541 | _schedule_T_542; // @[Mux.scala:30:73]
wire _schedule_T_554 = _schedule_T_553 | _schedule_T_543; // @[Mux.scala:30:73]
wire _schedule_T_555 = _schedule_T_554 | _schedule_T_544; // @[Mux.scala:30:73]
wire _schedule_T_556 = _schedule_T_555 | _schedule_T_545; // @[Mux.scala:30:73]
wire _schedule_T_557 = _schedule_T_556 | _schedule_T_546; // @[Mux.scala:30:73]
wire _schedule_T_558 = _schedule_T_557 | _schedule_T_547; // @[Mux.scala:30:73]
wire _schedule_T_559 = _schedule_T_558 | _schedule_T_548; // @[Mux.scala:30:73]
wire _schedule_T_560 = _schedule_T_559 | _schedule_T_549; // @[Mux.scala:30:73]
wire _schedule_T_561 = _schedule_T_560 | _schedule_T_550; // @[Mux.scala:30:73]
wire _schedule_T_562 = _schedule_T_561 | _schedule_T_551; // @[Mux.scala:30:73]
wire _schedule_T_563 = _schedule_T_562 | _schedule_T_552; // @[Mux.scala:30:73]
assign _schedule_WIRE_32 = _schedule_T_563; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73]
wire _schedule_WIRE_34; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_35; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_36; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73]
wire _schedule_T_564 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_565 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_566 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_567 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_568 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_569 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_570 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_571 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_572 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_573 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_576 = _schedule_T_564 | _schedule_T_565; // @[Mux.scala:30:73]
wire _schedule_T_577 = _schedule_T_576 | _schedule_T_566; // @[Mux.scala:30:73]
wire _schedule_T_578 = _schedule_T_577 | _schedule_T_567; // @[Mux.scala:30:73]
wire _schedule_T_579 = _schedule_T_578 | _schedule_T_568; // @[Mux.scala:30:73]
wire _schedule_T_580 = _schedule_T_579 | _schedule_T_569; // @[Mux.scala:30:73]
wire _schedule_T_581 = _schedule_T_580 | _schedule_T_570; // @[Mux.scala:30:73]
wire _schedule_T_582 = _schedule_T_581 | _schedule_T_571; // @[Mux.scala:30:73]
wire _schedule_T_583 = _schedule_T_582 | _schedule_T_572; // @[Mux.scala:30:73]
wire _schedule_T_584 = _schedule_T_583 | _schedule_T_573; // @[Mux.scala:30:73]
wire _schedule_T_585 = _schedule_T_584; // @[Mux.scala:30:73]
wire _schedule_T_586 = _schedule_T_585; // @[Mux.scala:30:73]
assign _schedule_WIRE_34 = _schedule_T_586; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73]
wire _schedule_T_587 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_588 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_589 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_590 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_591 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_592 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_593 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_594 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_595 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_596 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_597 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_599 = _schedule_T_587 | _schedule_T_588; // @[Mux.scala:30:73]
wire _schedule_T_600 = _schedule_T_599 | _schedule_T_589; // @[Mux.scala:30:73]
wire _schedule_T_601 = _schedule_T_600 | _schedule_T_590; // @[Mux.scala:30:73]
wire _schedule_T_602 = _schedule_T_601 | _schedule_T_591; // @[Mux.scala:30:73]
wire _schedule_T_603 = _schedule_T_602 | _schedule_T_592; // @[Mux.scala:30:73]
wire _schedule_T_604 = _schedule_T_603 | _schedule_T_593; // @[Mux.scala:30:73]
wire _schedule_T_605 = _schedule_T_604 | _schedule_T_594; // @[Mux.scala:30:73]
wire _schedule_T_606 = _schedule_T_605 | _schedule_T_595; // @[Mux.scala:30:73]
wire _schedule_T_607 = _schedule_T_606 | _schedule_T_596; // @[Mux.scala:30:73]
wire _schedule_T_608 = _schedule_T_607 | _schedule_T_597; // @[Mux.scala:30:73]
wire _schedule_T_609 = _schedule_T_608; // @[Mux.scala:30:73]
assign _schedule_WIRE_35 = _schedule_T_609; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73]
wire _schedule_T_610 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_611 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_612 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_613 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_614 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_615 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_616 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_617 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_618 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_619 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_620 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_621 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_622 = _schedule_T_610 | _schedule_T_611; // @[Mux.scala:30:73]
wire _schedule_T_623 = _schedule_T_622 | _schedule_T_612; // @[Mux.scala:30:73]
wire _schedule_T_624 = _schedule_T_623 | _schedule_T_613; // @[Mux.scala:30:73]
wire _schedule_T_625 = _schedule_T_624 | _schedule_T_614; // @[Mux.scala:30:73]
wire _schedule_T_626 = _schedule_T_625 | _schedule_T_615; // @[Mux.scala:30:73]
wire _schedule_T_627 = _schedule_T_626 | _schedule_T_616; // @[Mux.scala:30:73]
wire _schedule_T_628 = _schedule_T_627 | _schedule_T_617; // @[Mux.scala:30:73]
wire _schedule_T_629 = _schedule_T_628 | _schedule_T_618; // @[Mux.scala:30:73]
wire _schedule_T_630 = _schedule_T_629 | _schedule_T_619; // @[Mux.scala:30:73]
wire _schedule_T_631 = _schedule_T_630 | _schedule_T_620; // @[Mux.scala:30:73]
wire _schedule_T_632 = _schedule_T_631 | _schedule_T_621; // @[Mux.scala:30:73]
assign _schedule_WIRE_36 = _schedule_T_632; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73]
wire _schedule_T_633 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_634 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_635 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_636 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_637 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_638 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_639 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_640 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_641 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_642 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_643 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_644 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_645 = _schedule_T_633 | _schedule_T_634; // @[Mux.scala:30:73]
wire _schedule_T_646 = _schedule_T_645 | _schedule_T_635; // @[Mux.scala:30:73]
wire _schedule_T_647 = _schedule_T_646 | _schedule_T_636; // @[Mux.scala:30:73]
wire _schedule_T_648 = _schedule_T_647 | _schedule_T_637; // @[Mux.scala:30:73]
wire _schedule_T_649 = _schedule_T_648 | _schedule_T_638; // @[Mux.scala:30:73]
wire _schedule_T_650 = _schedule_T_649 | _schedule_T_639; // @[Mux.scala:30:73]
wire _schedule_T_651 = _schedule_T_650 | _schedule_T_640; // @[Mux.scala:30:73]
wire _schedule_T_652 = _schedule_T_651 | _schedule_T_641; // @[Mux.scala:30:73]
wire _schedule_T_653 = _schedule_T_652 | _schedule_T_642; // @[Mux.scala:30:73]
wire _schedule_T_654 = _schedule_T_653 | _schedule_T_643; // @[Mux.scala:30:73]
wire _schedule_T_655 = _schedule_T_654 | _schedule_T_644; // @[Mux.scala:30:73]
assign _schedule_WIRE_37 = _schedule_T_655; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73]
wire _schedule_WIRE_47; // @[Mux.scala:30:73]
assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73]
assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73]
assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73]
assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_43; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_42; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_41; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_40; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
wire _schedule_T_656 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_657 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_658 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_659 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_660 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_661 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_662 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_663 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_664 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_665 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_666 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_667 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_668 = _schedule_T_656 | _schedule_T_657; // @[Mux.scala:30:73]
wire _schedule_T_669 = _schedule_T_668 | _schedule_T_658; // @[Mux.scala:30:73]
wire _schedule_T_670 = _schedule_T_669 | _schedule_T_659; // @[Mux.scala:30:73]
wire _schedule_T_671 = _schedule_T_670 | _schedule_T_660; // @[Mux.scala:30:73]
wire _schedule_T_672 = _schedule_T_671 | _schedule_T_661; // @[Mux.scala:30:73]
wire _schedule_T_673 = _schedule_T_672 | _schedule_T_662; // @[Mux.scala:30:73]
wire _schedule_T_674 = _schedule_T_673 | _schedule_T_663; // @[Mux.scala:30:73]
wire _schedule_T_675 = _schedule_T_674 | _schedule_T_664; // @[Mux.scala:30:73]
wire _schedule_T_676 = _schedule_T_675 | _schedule_T_665; // @[Mux.scala:30:73]
wire _schedule_T_677 = _schedule_T_676 | _schedule_T_666; // @[Mux.scala:30:73]
wire _schedule_T_678 = _schedule_T_677 | _schedule_T_667; // @[Mux.scala:30:73]
assign _schedule_WIRE_40 = _schedule_T_678; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_679 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_680 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_681 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_682 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_683 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_684 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_685 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_686 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_687 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_688 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_689 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_690 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_691 = _schedule_T_679 | _schedule_T_680; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_692 = _schedule_T_691 | _schedule_T_681; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_693 = _schedule_T_692 | _schedule_T_682; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_694 = _schedule_T_693 | _schedule_T_683; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_695 = _schedule_T_694 | _schedule_T_684; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_696 = _schedule_T_695 | _schedule_T_685; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_697 = _schedule_T_696 | _schedule_T_686; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_698 = _schedule_T_697 | _schedule_T_687; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_699 = _schedule_T_698 | _schedule_T_688; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_700 = _schedule_T_699 | _schedule_T_689; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_701 = _schedule_T_700 | _schedule_T_690; // @[Mux.scala:30:73]
assign _schedule_WIRE_41 = _schedule_T_701; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_702 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_703 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_704 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_705 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_706 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_707 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_708 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_709 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_710 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_711 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_712 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_713 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_714 = _schedule_T_702 | _schedule_T_703; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_715 = _schedule_T_714 | _schedule_T_704; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_716 = _schedule_T_715 | _schedule_T_705; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_717 = _schedule_T_716 | _schedule_T_706; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_718 = _schedule_T_717 | _schedule_T_707; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_719 = _schedule_T_718 | _schedule_T_708; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_720 = _schedule_T_719 | _schedule_T_709; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_721 = _schedule_T_720 | _schedule_T_710; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_722 = _schedule_T_721 | _schedule_T_711; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_723 = _schedule_T_722 | _schedule_T_712; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_724 = _schedule_T_723 | _schedule_T_713; // @[Mux.scala:30:73]
assign _schedule_WIRE_42 = _schedule_T_724; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_725 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_726 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_727 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_728 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_729 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_730 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_731 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_732 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_733 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_734 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_735 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_736 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_737 = _schedule_T_725 | _schedule_T_726; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_738 = _schedule_T_737 | _schedule_T_727; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_739 = _schedule_T_738 | _schedule_T_728; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_740 = _schedule_T_739 | _schedule_T_729; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_741 = _schedule_T_740 | _schedule_T_730; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_742 = _schedule_T_741 | _schedule_T_731; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_743 = _schedule_T_742 | _schedule_T_732; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_744 = _schedule_T_743 | _schedule_T_733; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_745 = _schedule_T_744 | _schedule_T_734; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_746 = _schedule_T_745 | _schedule_T_735; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_747 = _schedule_T_746 | _schedule_T_736; // @[Mux.scala:30:73]
assign _schedule_WIRE_43 = _schedule_T_747; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_771 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_772 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_773 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_774 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_775 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_776 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_777 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_778 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_779 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_780 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_781 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_782 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_783 = _schedule_T_771 | _schedule_T_772; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_784 = _schedule_T_783 | _schedule_T_773; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_785 = _schedule_T_784 | _schedule_T_774; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_786 = _schedule_T_785 | _schedule_T_775; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_787 = _schedule_T_786 | _schedule_T_776; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_788 = _schedule_T_787 | _schedule_T_777; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_789 = _schedule_T_788 | _schedule_T_778; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_790 = _schedule_T_789 | _schedule_T_779; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_791 = _schedule_T_790 | _schedule_T_780; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_792 = _schedule_T_791 | _schedule_T_781; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_793 = _schedule_T_792 | _schedule_T_782; // @[Mux.scala:30:73]
assign _schedule_WIRE_45 = _schedule_T_793; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_794 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_795 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_796 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_797 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_798 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_799 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_800 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_801 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_802 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_803 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_804 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_805 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_806 = _schedule_T_794 | _schedule_T_795; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_807 = _schedule_T_806 | _schedule_T_796; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_808 = _schedule_T_807 | _schedule_T_797; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_809 = _schedule_T_808 | _schedule_T_798; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_810 = _schedule_T_809 | _schedule_T_799; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_811 = _schedule_T_810 | _schedule_T_800; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_812 = _schedule_T_811 | _schedule_T_801; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_813 = _schedule_T_812 | _schedule_T_802; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_814 = _schedule_T_813 | _schedule_T_803; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_815 = _schedule_T_814 | _schedule_T_804; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_816 = _schedule_T_815 | _schedule_T_805; // @[Mux.scala:30:73]
assign _schedule_WIRE_46 = _schedule_T_816; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73]
wire _schedule_T_817 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_818 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_819 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_820 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_821 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_822 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_823 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_824 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_825 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_826 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_827 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_828 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_829 = _schedule_T_817 | _schedule_T_818; // @[Mux.scala:30:73]
wire _schedule_T_830 = _schedule_T_829 | _schedule_T_819; // @[Mux.scala:30:73]
wire _schedule_T_831 = _schedule_T_830 | _schedule_T_820; // @[Mux.scala:30:73]
wire _schedule_T_832 = _schedule_T_831 | _schedule_T_821; // @[Mux.scala:30:73]
wire _schedule_T_833 = _schedule_T_832 | _schedule_T_822; // @[Mux.scala:30:73]
wire _schedule_T_834 = _schedule_T_833 | _schedule_T_823; // @[Mux.scala:30:73]
wire _schedule_T_835 = _schedule_T_834 | _schedule_T_824; // @[Mux.scala:30:73]
wire _schedule_T_836 = _schedule_T_835 | _schedule_T_825; // @[Mux.scala:30:73]
wire _schedule_T_837 = _schedule_T_836 | _schedule_T_826; // @[Mux.scala:30:73]
wire _schedule_T_838 = _schedule_T_837 | _schedule_T_827; // @[Mux.scala:30:73]
wire _schedule_T_839 = _schedule_T_838 | _schedule_T_828; // @[Mux.scala:30:73]
assign _schedule_WIRE_47 = _schedule_T_839; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73]
wire _schedule_WIRE_54; // @[Mux.scala:30:73]
assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73]
assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73]
assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_52; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_51; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_50; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
wire _schedule_T_840 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_841 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_842 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_843 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_844 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_845 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_846 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_847 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_848 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_849 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_850 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_851 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_852 = _schedule_T_840 | _schedule_T_841; // @[Mux.scala:30:73]
wire _schedule_T_853 = _schedule_T_852 | _schedule_T_842; // @[Mux.scala:30:73]
wire _schedule_T_854 = _schedule_T_853 | _schedule_T_843; // @[Mux.scala:30:73]
wire _schedule_T_855 = _schedule_T_854 | _schedule_T_844; // @[Mux.scala:30:73]
wire _schedule_T_856 = _schedule_T_855 | _schedule_T_845; // @[Mux.scala:30:73]
wire _schedule_T_857 = _schedule_T_856 | _schedule_T_846; // @[Mux.scala:30:73]
wire _schedule_T_858 = _schedule_T_857 | _schedule_T_847; // @[Mux.scala:30:73]
wire _schedule_T_859 = _schedule_T_858 | _schedule_T_848; // @[Mux.scala:30:73]
wire _schedule_T_860 = _schedule_T_859 | _schedule_T_849; // @[Mux.scala:30:73]
wire _schedule_T_861 = _schedule_T_860 | _schedule_T_850; // @[Mux.scala:30:73]
wire _schedule_T_862 = _schedule_T_861 | _schedule_T_851; // @[Mux.scala:30:73]
assign _schedule_WIRE_50 = _schedule_T_862; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_863 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_864 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_865 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_866 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_867 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_868 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_869 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_870 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_871 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_872 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_873 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_874 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_875 = _schedule_T_863 | _schedule_T_864; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_876 = _schedule_T_875 | _schedule_T_865; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_877 = _schedule_T_876 | _schedule_T_866; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_878 = _schedule_T_877 | _schedule_T_867; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_879 = _schedule_T_878 | _schedule_T_868; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_880 = _schedule_T_879 | _schedule_T_869; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_881 = _schedule_T_880 | _schedule_T_870; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_882 = _schedule_T_881 | _schedule_T_871; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_883 = _schedule_T_882 | _schedule_T_872; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_884 = _schedule_T_883 | _schedule_T_873; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_885 = _schedule_T_884 | _schedule_T_874; // @[Mux.scala:30:73]
assign _schedule_WIRE_51 = _schedule_T_885; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_886 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_887 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_888 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_889 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_890 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_891 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_892 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_893 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_894 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_895 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_896 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_897 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_898 = _schedule_T_886 | _schedule_T_887; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_899 = _schedule_T_898 | _schedule_T_888; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_900 = _schedule_T_899 | _schedule_T_889; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_901 = _schedule_T_900 | _schedule_T_890; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_902 = _schedule_T_901 | _schedule_T_891; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_903 = _schedule_T_902 | _schedule_T_892; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_904 = _schedule_T_903 | _schedule_T_893; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_905 = _schedule_T_904 | _schedule_T_894; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_906 = _schedule_T_905 | _schedule_T_895; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_907 = _schedule_T_906 | _schedule_T_896; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_908 = _schedule_T_907 | _schedule_T_897; // @[Mux.scala:30:73]
assign _schedule_WIRE_52 = _schedule_T_908; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_909 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_910 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_911 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_912 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_913 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_914 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_915 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_916 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_917 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_918 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_919 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_920 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_921 = _schedule_T_909 | _schedule_T_910; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_922 = _schedule_T_921 | _schedule_T_911; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_923 = _schedule_T_922 | _schedule_T_912; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_924 = _schedule_T_923 | _schedule_T_913; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_925 = _schedule_T_924 | _schedule_T_914; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_926 = _schedule_T_925 | _schedule_T_915; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_927 = _schedule_T_926 | _schedule_T_916; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_928 = _schedule_T_927 | _schedule_T_917; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_929 = _schedule_T_928 | _schedule_T_918; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_930 = _schedule_T_929 | _schedule_T_919; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_931 = _schedule_T_930 | _schedule_T_920; // @[Mux.scala:30:73]
assign _schedule_WIRE_53 = _schedule_T_931; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73]
wire _schedule_T_932 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_933 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_934 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_935 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_936 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_937 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_938 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_939 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_940 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_941 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_942 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_943 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_944 = _schedule_T_932 | _schedule_T_933; // @[Mux.scala:30:73]
wire _schedule_T_945 = _schedule_T_944 | _schedule_T_934; // @[Mux.scala:30:73]
wire _schedule_T_946 = _schedule_T_945 | _schedule_T_935; // @[Mux.scala:30:73]
wire _schedule_T_947 = _schedule_T_946 | _schedule_T_936; // @[Mux.scala:30:73]
wire _schedule_T_948 = _schedule_T_947 | _schedule_T_937; // @[Mux.scala:30:73]
wire _schedule_T_949 = _schedule_T_948 | _schedule_T_938; // @[Mux.scala:30:73]
wire _schedule_T_950 = _schedule_T_949 | _schedule_T_939; // @[Mux.scala:30:73]
wire _schedule_T_951 = _schedule_T_950 | _schedule_T_940; // @[Mux.scala:30:73]
wire _schedule_T_952 = _schedule_T_951 | _schedule_T_941; // @[Mux.scala:30:73]
wire _schedule_T_953 = _schedule_T_952 | _schedule_T_942; // @[Mux.scala:30:73]
wire _schedule_T_954 = _schedule_T_953 | _schedule_T_943; // @[Mux.scala:30:73]
assign _schedule_WIRE_54 = _schedule_T_954; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73]
wire _schedule_WIRE_62; // @[Mux.scala:30:73]
assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73]
assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73]
assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_56_block; // @[Mux.scala:30:73]
assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_61; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_60; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73]
wire _schedule_T_955 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_956 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_957 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_958 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_959 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_960 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_961 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_962 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_963 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_964 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_965 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_966 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_967 = _schedule_T_955 | _schedule_T_956; // @[Mux.scala:30:73]
wire _schedule_T_968 = _schedule_T_967 | _schedule_T_957; // @[Mux.scala:30:73]
wire _schedule_T_969 = _schedule_T_968 | _schedule_T_958; // @[Mux.scala:30:73]
wire _schedule_T_970 = _schedule_T_969 | _schedule_T_959; // @[Mux.scala:30:73]
wire _schedule_T_971 = _schedule_T_970 | _schedule_T_960; // @[Mux.scala:30:73]
wire _schedule_T_972 = _schedule_T_971 | _schedule_T_961; // @[Mux.scala:30:73]
wire _schedule_T_973 = _schedule_T_972 | _schedule_T_962; // @[Mux.scala:30:73]
wire _schedule_T_974 = _schedule_T_973 | _schedule_T_963; // @[Mux.scala:30:73]
wire _schedule_T_975 = _schedule_T_974 | _schedule_T_964; // @[Mux.scala:30:73]
wire _schedule_T_976 = _schedule_T_975 | _schedule_T_965; // @[Mux.scala:30:73]
wire _schedule_T_977 = _schedule_T_976 | _schedule_T_966; // @[Mux.scala:30:73]
assign _schedule_WIRE_57 = _schedule_T_977; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1001 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1002 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1003 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1004 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1005 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1006 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1007 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1008 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1009 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1010 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1011 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1012 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1013 = _schedule_T_1001 | _schedule_T_1002; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1014 = _schedule_T_1013 | _schedule_T_1003; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1015 = _schedule_T_1014 | _schedule_T_1004; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1016 = _schedule_T_1015 | _schedule_T_1005; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1017 = _schedule_T_1016 | _schedule_T_1006; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1018 = _schedule_T_1017 | _schedule_T_1007; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1019 = _schedule_T_1018 | _schedule_T_1008; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1020 = _schedule_T_1019 | _schedule_T_1009; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1021 = _schedule_T_1020 | _schedule_T_1010; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1022 = _schedule_T_1021 | _schedule_T_1011; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1023 = _schedule_T_1022 | _schedule_T_1012; // @[Mux.scala:30:73]
assign _schedule_WIRE_59 = _schedule_T_1023; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1024 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1025 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1026 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1027 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1028 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1029 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1030 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1031 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1032 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1033 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1034 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1035 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1036 = _schedule_T_1024 | _schedule_T_1025; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1037 = _schedule_T_1036 | _schedule_T_1026; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1038 = _schedule_T_1037 | _schedule_T_1027; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1039 = _schedule_T_1038 | _schedule_T_1028; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1040 = _schedule_T_1039 | _schedule_T_1029; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1041 = _schedule_T_1040 | _schedule_T_1030; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1042 = _schedule_T_1041 | _schedule_T_1031; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1043 = _schedule_T_1042 | _schedule_T_1032; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1044 = _schedule_T_1043 | _schedule_T_1033; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1045 = _schedule_T_1044 | _schedule_T_1034; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1046 = _schedule_T_1045 | _schedule_T_1035; // @[Mux.scala:30:73]
assign _schedule_WIRE_60 = _schedule_T_1046; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1047 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1048 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1049 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1050 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1051 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1052 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1053 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1054 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1055 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1056 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1057 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1058 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1059 = _schedule_T_1047 | _schedule_T_1048; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1060 = _schedule_T_1059 | _schedule_T_1049; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1061 = _schedule_T_1060 | _schedule_T_1050; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1062 = _schedule_T_1061 | _schedule_T_1051; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1063 = _schedule_T_1062 | _schedule_T_1052; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1064 = _schedule_T_1063 | _schedule_T_1053; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1065 = _schedule_T_1064 | _schedule_T_1054; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1066 = _schedule_T_1065 | _schedule_T_1055; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1067 = _schedule_T_1066 | _schedule_T_1056; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1068 = _schedule_T_1067 | _schedule_T_1057; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1069 = _schedule_T_1068 | _schedule_T_1058; // @[Mux.scala:30:73]
assign _schedule_WIRE_61 = _schedule_T_1069; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73]
wire _schedule_T_1070 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1071 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1072 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1073 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1074 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1075 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1076 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1077 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1078 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1079 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1080 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1081 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1082 = _schedule_T_1070 | _schedule_T_1071; // @[Mux.scala:30:73]
wire _schedule_T_1083 = _schedule_T_1082 | _schedule_T_1072; // @[Mux.scala:30:73]
wire _schedule_T_1084 = _schedule_T_1083 | _schedule_T_1073; // @[Mux.scala:30:73]
wire _schedule_T_1085 = _schedule_T_1084 | _schedule_T_1074; // @[Mux.scala:30:73]
wire _schedule_T_1086 = _schedule_T_1085 | _schedule_T_1075; // @[Mux.scala:30:73]
wire _schedule_T_1087 = _schedule_T_1086 | _schedule_T_1076; // @[Mux.scala:30:73]
wire _schedule_T_1088 = _schedule_T_1087 | _schedule_T_1077; // @[Mux.scala:30:73]
wire _schedule_T_1089 = _schedule_T_1088 | _schedule_T_1078; // @[Mux.scala:30:73]
wire _schedule_T_1090 = _schedule_T_1089 | _schedule_T_1079; // @[Mux.scala:30:73]
wire _schedule_T_1091 = _schedule_T_1090 | _schedule_T_1080; // @[Mux.scala:30:73]
wire _schedule_T_1092 = _schedule_T_1091 | _schedule_T_1081; // @[Mux.scala:30:73]
assign _schedule_WIRE_62 = _schedule_T_1092; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_12 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_13 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_14 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_15 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_16 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_17 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_18 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_19 = _scheduleTag_T_7 ? _mshrs_7_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_20 = _scheduleTag_T_8 ? _mshrs_8_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_21 = _scheduleTag_T_9 ? _mshrs_9_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_22 = _scheduleTag_T_10 ? _mshrs_10_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_23 = _scheduleTag_T_11 ? _mshrs_11_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_24 = _scheduleTag_T_12 | _scheduleTag_T_13; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_25 = _scheduleTag_T_24 | _scheduleTag_T_14; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_26 = _scheduleTag_T_25 | _scheduleTag_T_15; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_27 = _scheduleTag_T_26 | _scheduleTag_T_16; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_28 = _scheduleTag_T_27 | _scheduleTag_T_17; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_29 = _scheduleTag_T_28 | _scheduleTag_T_18; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_30 = _scheduleTag_T_29 | _scheduleTag_T_19; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_31 = _scheduleTag_T_30 | _scheduleTag_T_20; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_32 = _scheduleTag_T_31 | _scheduleTag_T_21; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_33 = _scheduleTag_T_32 | _scheduleTag_T_22; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_34 = _scheduleTag_T_33 | _scheduleTag_T_23; // @[Mux.scala:30:73]
wire [12:0] scheduleTag = _scheduleTag_T_34; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_12 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_13 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_14 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_15 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_16 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_17 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_18 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_19 = _scheduleSet_T_7 ? _mshrs_7_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_20 = _scheduleSet_T_8 ? _mshrs_8_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_21 = _scheduleSet_T_9 ? _mshrs_9_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_22 = _scheduleSet_T_10 ? _mshrs_10_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_23 = _scheduleSet_T_11 ? _mshrs_11_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_24 = _scheduleSet_T_12 | _scheduleSet_T_13; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_25 = _scheduleSet_T_24 | _scheduleSet_T_14; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_26 = _scheduleSet_T_25 | _scheduleSet_T_15; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_27 = _scheduleSet_T_26 | _scheduleSet_T_16; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_28 = _scheduleSet_T_27 | _scheduleSet_T_17; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_29 = _scheduleSet_T_28 | _scheduleSet_T_18; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_30 = _scheduleSet_T_29 | _scheduleSet_T_19; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_31 = _scheduleSet_T_30 | _scheduleSet_T_20; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_32 = _scheduleSet_T_31 | _scheduleSet_T_21; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_33 = _scheduleSet_T_32 | _scheduleSet_T_22; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_34 = _scheduleSet_T_33 | _scheduleSet_T_23; // @[Mux.scala:30:73]
wire [9:0] scheduleSet = _scheduleSet_T_34; // @[Mux.scala:30:73]
wire [10:0] _robin_filter_T = mshr_selectOH[11:1]; // @[package.scala:262:48]
wire [11:0] _robin_filter_T_1 = {mshr_selectOH[11], mshr_selectOH[10:0] | _robin_filter_T}; // @[Mux.scala:32:36]
wire [9:0] _robin_filter_T_2 = _robin_filter_T_1[11:2]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_3 = {_robin_filter_T_1[11:10], _robin_filter_T_1[9:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}]
wire [7:0] _robin_filter_T_4 = _robin_filter_T_3[11:4]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_5 = {_robin_filter_T_3[11:8], _robin_filter_T_3[7:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}]
wire [3:0] _robin_filter_T_6 = _robin_filter_T_5[11:8]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_7 = {_robin_filter_T_5[11:4], _robin_filter_T_5[3:0] | _robin_filter_T_6}; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_8 = _robin_filter_T_7; // @[package.scala:262:43, :263:17]
wire [11:0] _robin_filter_T_9 = ~_robin_filter_T_8; // @[package.scala:263:17]
wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73]
assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 4'h0; // @[OneHot.scala:32:10]
assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73]
assign _nestedwb_set_T = select_c ? _mshrs_11_io_status_bits_set : _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24]
assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24]
assign _nestedwb_tag_T = select_c ? _mshrs_11_io_status_bits_tag : _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24]
assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24]
wire _GEN = select_bc & _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37]
wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37]
assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37]
wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37]
assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37]
assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37]
wire _nestedwb_b_toN_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123]
assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}]
assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75]
wire _nestedwb_b_toB_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123]
assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}]
assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75]
assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37]
wire _nestedwb_c_set_dirty_T = select_c & _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37]
assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}]
assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75]
wire _request_ready_T_2; // @[Scheduler.scala:261:40]
wire _request_valid_T_2; // @[Scheduler.scala:164:39]
wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22]
wire _request_bits_T_1_control; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22]
wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22]
wire [12:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_7_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_8_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_9_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_10_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_11_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [9:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [9:0] request_bits_set; // @[Scheduler.scala:163:21]
wire request_ready; // @[Scheduler.scala:163:21]
wire request_valid; // @[Scheduler.scala:163:21]
wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62]
wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}]
assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}]
assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39]
wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [12:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [9:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire _request_bits_T_control; // @[Scheduler.scala:166:22]
assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22]
assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22]
wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44]
wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44]
assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44]
wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44]
assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44]
wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44]
assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44]
wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64]
wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}]
wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64]
wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}]
wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87]
wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}]
wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_14 = _mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_15 = _mshrs_7_io_status_valid & _setMatches_T_14; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_16 = _mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_17 = _mshrs_8_io_status_valid & _setMatches_T_16; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_18 = _mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_19 = _mshrs_9_io_status_valid & _setMatches_T_18; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_20 = _mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_21 = _mshrs_10_io_status_valid & _setMatches_T_20; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_22 = _mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_23 = _mshrs_11_io_status_valid & _setMatches_T_22; // @[Scheduler.scala:71:46, :172:{59,83}]
wire [1:0] setMatches_lo_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_lo = {setMatches_lo_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_lo_hi_hi = {_setMatches_T_11, _setMatches_T_9}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_hi = {setMatches_lo_hi_hi, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_lo = {setMatches_lo_hi, setMatches_lo_lo}; // @[Scheduler.scala:172:23]
wire [1:0] setMatches_hi_lo_hi = {_setMatches_T_17, _setMatches_T_15}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_lo = {setMatches_hi_lo_hi, _setMatches_T_13}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_hi_hi_hi = {_setMatches_T_23, _setMatches_T_21}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_hi = {setMatches_hi_hi_hi, _setMatches_T_19}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23]
wire [11:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23]
wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27]
wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}]
wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockB_T_12 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_13 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_14 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_15 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_16 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_17 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_18 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_19 = _blockB_T_7 & _mshrs_7_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_20 = _blockB_T_8 & _mshrs_8_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_21 = _blockB_T_9 & _mshrs_9_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_22 = _blockB_T_10 & _mshrs_10_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_23 = _blockB_T_11 & _mshrs_11_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_24 = _blockB_T_12 | _blockB_T_13; // @[Mux.scala:30:73]
wire _blockB_T_25 = _blockB_T_24 | _blockB_T_14; // @[Mux.scala:30:73]
wire _blockB_T_26 = _blockB_T_25 | _blockB_T_15; // @[Mux.scala:30:73]
wire _blockB_T_27 = _blockB_T_26 | _blockB_T_16; // @[Mux.scala:30:73]
wire _blockB_T_28 = _blockB_T_27 | _blockB_T_17; // @[Mux.scala:30:73]
wire _blockB_T_29 = _blockB_T_28 | _blockB_T_18; // @[Mux.scala:30:73]
wire _blockB_T_30 = _blockB_T_29 | _blockB_T_19; // @[Mux.scala:30:73]
wire _blockB_T_31 = _blockB_T_30 | _blockB_T_20; // @[Mux.scala:30:73]
wire _blockB_T_32 = _blockB_T_31 | _blockB_T_21; // @[Mux.scala:30:73]
wire _blockB_T_33 = _blockB_T_32 | _blockB_T_22; // @[Mux.scala:30:73]
wire _blockB_T_34 = _blockB_T_33 | _blockB_T_23; // @[Mux.scala:30:73]
wire _blockB_WIRE = _blockB_T_34; // @[Mux.scala:30:73]
wire _blockC_T_12 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_13 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_14 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_15 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_16 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_17 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_18 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_19 = _blockC_T_7 & _mshrs_7_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_20 = _blockC_T_8 & _mshrs_8_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_21 = _blockC_T_9 & _mshrs_9_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_22 = _blockC_T_10 & _mshrs_10_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_23 = _blockC_T_11 & _mshrs_11_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_24 = _blockC_T_12 | _blockC_T_13; // @[Mux.scala:30:73]
wire _blockC_T_25 = _blockC_T_24 | _blockC_T_14; // @[Mux.scala:30:73]
wire _blockC_T_26 = _blockC_T_25 | _blockC_T_15; // @[Mux.scala:30:73]
wire _blockC_T_27 = _blockC_T_26 | _blockC_T_16; // @[Mux.scala:30:73]
wire _blockC_T_28 = _blockC_T_27 | _blockC_T_17; // @[Mux.scala:30:73]
wire _blockC_T_29 = _blockC_T_28 | _blockC_T_18; // @[Mux.scala:30:73]
wire _blockC_T_30 = _blockC_T_29 | _blockC_T_19; // @[Mux.scala:30:73]
wire _blockC_T_31 = _blockC_T_30 | _blockC_T_20; // @[Mux.scala:30:73]
wire _blockC_T_32 = _blockC_T_31 | _blockC_T_21; // @[Mux.scala:30:73]
wire _blockC_T_33 = _blockC_T_32 | _blockC_T_22; // @[Mux.scala:30:73]
wire _blockC_T_34 = _blockC_T_33 | _blockC_T_23; // @[Mux.scala:30:73]
wire _blockC_WIRE = _blockC_T_34; // @[Mux.scala:30:73]
wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _nestB_T_12 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_13 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_14 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_15 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_16 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_17 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_18 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_19 = _nestB_T_7 & _mshrs_7_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_20 = _nestB_T_8 & _mshrs_8_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_21 = _nestB_T_9 & _mshrs_9_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_22 = _nestB_T_10 & _mshrs_10_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_23 = _nestB_T_11 & _mshrs_11_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_24 = _nestB_T_12 | _nestB_T_13; // @[Mux.scala:30:73]
wire _nestB_T_25 = _nestB_T_24 | _nestB_T_14; // @[Mux.scala:30:73]
wire _nestB_T_26 = _nestB_T_25 | _nestB_T_15; // @[Mux.scala:30:73]
wire _nestB_T_27 = _nestB_T_26 | _nestB_T_16; // @[Mux.scala:30:73]
wire _nestB_T_28 = _nestB_T_27 | _nestB_T_17; // @[Mux.scala:30:73]
wire _nestB_T_29 = _nestB_T_28 | _nestB_T_18; // @[Mux.scala:30:73]
wire _nestB_T_30 = _nestB_T_29 | _nestB_T_19; // @[Mux.scala:30:73]
wire _nestB_T_31 = _nestB_T_30 | _nestB_T_20; // @[Mux.scala:30:73]
wire _nestB_T_32 = _nestB_T_31 | _nestB_T_21; // @[Mux.scala:30:73]
wire _nestB_T_33 = _nestB_T_32 | _nestB_T_22; // @[Mux.scala:30:73]
wire _nestB_T_34 = _nestB_T_33 | _nestB_T_23; // @[Mux.scala:30:73]
wire _nestB_WIRE = _nestB_T_34; // @[Mux.scala:30:73]
wire _nestC_T_12 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_13 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_14 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_15 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_16 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_17 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_18 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_19 = _nestC_T_7 & _mshrs_7_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_20 = _nestC_T_8 & _mshrs_8_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_21 = _nestC_T_9 & _mshrs_9_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_22 = _nestC_T_10 & _mshrs_10_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_23 = _nestC_T_11 & _mshrs_11_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_24 = _nestC_T_12 | _nestC_T_13; // @[Mux.scala:30:73]
wire _nestC_T_25 = _nestC_T_24 | _nestC_T_14; // @[Mux.scala:30:73]
wire _nestC_T_26 = _nestC_T_25 | _nestC_T_15; // @[Mux.scala:30:73]
wire _nestC_T_27 = _nestC_T_26 | _nestC_T_16; // @[Mux.scala:30:73]
wire _nestC_T_28 = _nestC_T_27 | _nestC_T_17; // @[Mux.scala:30:73]
wire _nestC_T_29 = _nestC_T_28 | _nestC_T_18; // @[Mux.scala:30:73]
wire _nestC_T_30 = _nestC_T_29 | _nestC_T_19; // @[Mux.scala:30:73]
wire _nestC_T_31 = _nestC_T_30 | _nestC_T_20; // @[Mux.scala:30:73]
wire _nestC_T_32 = _nestC_T_31 | _nestC_T_21; // @[Mux.scala:30:73]
wire _nestC_T_33 = _nestC_T_32 | _nestC_T_22; // @[Mux.scala:30:73]
wire _nestC_T_34 = _nestC_T_33 | _nestC_T_23; // @[Mux.scala:30:73]
wire _nestC_WIRE = _nestC_T_34; // @[Mux.scala:30:73]
wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46]
wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}]
wire [11:0] prioFilter = {prioFilter_hi, 10'h3FF}; // @[Scheduler.scala:182:23]
wire [11:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33]
wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28]
wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}]
wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45]
wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}]
wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}]
wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66]
wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}]
wire _T_12 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31]
wire _bypass_T; // @[Scheduler.scala:213:30]
assign _bypass_T = _T_12; // @[Scheduler.scala:195:31, :213:30]
wire _bypass_T_1; // @[Scheduler.scala:231:32]
assign _bypass_T_1 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_2; // @[Scheduler.scala:231:32]
assign _bypass_T_2 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_3; // @[Scheduler.scala:231:32]
assign _bypass_T_3 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_4; // @[Scheduler.scala:231:32]
assign _bypass_T_4 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_5; // @[Scheduler.scala:231:32]
assign _bypass_T_5 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_6; // @[Scheduler.scala:231:32]
assign _bypass_T_6 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_7; // @[Scheduler.scala:231:32]
assign _bypass_T_7 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_8; // @[Scheduler.scala:231:32]
assign _bypass_T_8 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_9; // @[Scheduler.scala:231:32]
assign _bypass_T_9 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_10; // @[Scheduler.scala:231:32]
assign _bypass_T_10 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_11; // @[Scheduler.scala:231:32]
assign _bypass_T_11 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_12; // @[Scheduler.scala:231:32]
assign _bypass_T_12 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43]
assign _requests_io_push_valid_T = _T_12; // @[Scheduler.scala:195:31, :270:43]
wire _lowerMatches1_T = lowerMatches[11]; // @[Scheduler.scala:183:33, :200:21]
wire _lowerMatches1_T_2 = lowerMatches[10]; // @[Scheduler.scala:183:33, :201:21]
wire [11:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 12'h400 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}]
wire [11:0] lowerMatches1 = _lowerMatches1_T ? 12'h800 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8]
wire [11:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30]
wire [23:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30]
wire [23:0] selected_requests_hi; // @[Scheduler.scala:206:30]
assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30]
wire [23:0] pop_index_hi; // @[Scheduler.scala:241:31]
assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31]
wire [35:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30]
wire [35:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}]
wire [11:0] _a_pop_T = selected_requests[11:0]; // @[Scheduler.scala:206:76, :207:32]
wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}]
wire [11:0] _b_pop_T = selected_requests[23:12]; // @[Scheduler.scala:206:76, :208:32]
wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}]
wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76]
wire [11:0] _c_pop_T = selected_requests[35:24]; // @[Scheduler.scala:206:76, :209:32]
wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}]
wire [11:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38]
wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}]
wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33]
wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58]
wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101]
wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109]
wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}]
wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}]
wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26]
wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23]
wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}]
wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}]
wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49]
wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73]
wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73]
wire _will_pop_T; // @[Scheduler.scala:215:34]
assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34]
wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64]
assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64]
wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48]
wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}]
wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_1 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_1 = _requests_io_valid[24]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_2 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_2 = _requests_io_valid[25]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_3 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_3 = _requests_io_valid[26]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_4 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_4 = _requests_io_valid[27]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_5 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_5 = _requests_io_valid[28]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_6 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_6 = _requests_io_valid[29]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_7 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_7 = _requests_io_valid[30]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_8 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_8 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_68 = b_pop_8; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_8 = _requests_io_valid[31]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_65 = lowerMatches1[7]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_66 = c_pop_8 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_67 = ~c_pop_8; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_69 = ~b_pop_8; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_70 = ~a_pop_8; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_71 = _bypassMatches_T_68 ? _bypassMatches_T_69 : _bypassMatches_T_70; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_72 = _bypassMatches_T_66 ? _bypassMatches_T_67 : _bypassMatches_T_71; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_8 = _bypassMatches_T_65 & _bypassMatches_T_72; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_8 = a_pop_8 | b_pop_8; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_8 = _may_pop_T_8 | c_pop_8; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_8 = _bypass_T_8 & bypassMatches_8; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_8 = may_pop_8 | bypass_8; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_8 = _mshrs_7_io_schedule_bits_reload & _will_reload_T_8; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_7_prio_0 = bypass_8 ? _view__WIRE_7_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_prio_1 = ~bypass_8 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_7_prio_2 = bypass_8 ? _view__WIRE_7_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_control = bypass_8 ? _view__WIRE_7_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_opcode = bypass_8 ? _view__WIRE_7_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_param = bypass_8 ? _view__WIRE_7_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_size = bypass_8 ? _view__WIRE_7_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_source = bypass_8 ? _view__WIRE_7_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_7_tag = bypass_8 ? _view__WIRE_7_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_offset = bypass_8 ? _view__WIRE_7_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_put = bypass_8 ? _view__WIRE_7_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_7_io_allocate_bits_repeat_T = mshrs_7_io_allocate_bits_tag == _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_7_io_allocate_valid_T = sel_7 & will_reload_8; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_9 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_9 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_76 = b_pop_9; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_9 = _requests_io_valid[32]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_73 = lowerMatches1[8]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_74 = c_pop_9 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_75 = ~c_pop_9; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_77 = ~b_pop_9; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_78 = ~a_pop_9; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_79 = _bypassMatches_T_76 ? _bypassMatches_T_77 : _bypassMatches_T_78; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_80 = _bypassMatches_T_74 ? _bypassMatches_T_75 : _bypassMatches_T_79; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_9 = _bypassMatches_T_73 & _bypassMatches_T_80; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_9 = a_pop_9 | b_pop_9; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_9 = _may_pop_T_9 | c_pop_9; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_9 = _bypass_T_9 & bypassMatches_9; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_9 = may_pop_9 | bypass_9; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_9 = _mshrs_8_io_schedule_bits_reload & _will_reload_T_9; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_8_prio_0 = bypass_9 ? _view__WIRE_8_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_prio_1 = ~bypass_9 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_8_prio_2 = bypass_9 ? _view__WIRE_8_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_control = bypass_9 ? _view__WIRE_8_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_opcode = bypass_9 ? _view__WIRE_8_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_param = bypass_9 ? _view__WIRE_8_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_size = bypass_9 ? _view__WIRE_8_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_source = bypass_9 ? _view__WIRE_8_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_8_tag = bypass_9 ? _view__WIRE_8_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_offset = bypass_9 ? _view__WIRE_8_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_put = bypass_9 ? _view__WIRE_8_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_8_io_allocate_bits_repeat_T = mshrs_8_io_allocate_bits_tag == _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_8_io_allocate_valid_T = sel_8 & will_reload_9; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_10 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_10 = _requests_io_valid[21]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_84 = b_pop_10; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_10 = _requests_io_valid[33]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_81 = lowerMatches1[9]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_82 = c_pop_10 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_83 = ~c_pop_10; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_85 = ~b_pop_10; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_86 = ~a_pop_10; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_87 = _bypassMatches_T_84 ? _bypassMatches_T_85 : _bypassMatches_T_86; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_88 = _bypassMatches_T_82 ? _bypassMatches_T_83 : _bypassMatches_T_87; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_10 = _bypassMatches_T_81 & _bypassMatches_T_88; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_10 = a_pop_10 | b_pop_10; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_10 = _may_pop_T_10 | c_pop_10; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_10 = _bypass_T_10 & bypassMatches_10; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_10 = may_pop_10 | bypass_10; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_10 = _mshrs_9_io_schedule_bits_reload & _will_reload_T_10; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_9_prio_0 = bypass_10 ? _view__WIRE_9_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_prio_1 = ~bypass_10 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_9_prio_2 = bypass_10 ? _view__WIRE_9_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_control = bypass_10 ? _view__WIRE_9_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_opcode = bypass_10 ? _view__WIRE_9_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_param = bypass_10 ? _view__WIRE_9_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_size = bypass_10 ? _view__WIRE_9_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_source = bypass_10 ? _view__WIRE_9_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_9_tag = bypass_10 ? _view__WIRE_9_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_offset = bypass_10 ? _view__WIRE_9_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_put = bypass_10 ? _view__WIRE_9_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_9_io_allocate_bits_repeat_T = mshrs_9_io_allocate_bits_tag == _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_9_io_allocate_valid_T = sel_9 & will_reload_10; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_11 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_11 = _requests_io_valid[22]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_92 = b_pop_11; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_11 = _requests_io_valid[34]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_89 = lowerMatches1[10]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_90 = c_pop_11 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_91 = ~c_pop_11; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_93 = ~b_pop_11; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_94 = ~a_pop_11; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_95 = _bypassMatches_T_92 ? _bypassMatches_T_93 : _bypassMatches_T_94; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_96 = _bypassMatches_T_90 ? _bypassMatches_T_91 : _bypassMatches_T_95; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_11 = _bypassMatches_T_89 & _bypassMatches_T_96; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_11 = a_pop_11 | b_pop_11; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_11 = _may_pop_T_11 | c_pop_11; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_11 = _bypass_T_11 & bypassMatches_11; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_11 = may_pop_11 | bypass_11; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_11 = _mshrs_10_io_schedule_bits_reload & _will_reload_T_11; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_10_prio_0 = bypass_11 ? _view__WIRE_10_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_prio_1 = ~bypass_11 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_10_prio_2 = bypass_11 ? _view__WIRE_10_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_control = bypass_11 ? _view__WIRE_10_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_opcode = bypass_11 ? _view__WIRE_10_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_param = bypass_11 ? _view__WIRE_10_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_size = bypass_11 ? _view__WIRE_10_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_source = bypass_11 ? _view__WIRE_10_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_10_tag = bypass_11 ? _view__WIRE_10_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_offset = bypass_11 ? _view__WIRE_10_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_put = bypass_11 ? _view__WIRE_10_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_10_io_allocate_bits_repeat_T = mshrs_10_io_allocate_bits_tag == _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74]
wire _mshrs_10_io_allocate_valid_T = sel_10 & will_reload_11; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_12 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_12 = _requests_io_valid[23]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_100 = b_pop_12; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_12 = _requests_io_valid[35]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_97 = lowerMatches1[11]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_98 = c_pop_12 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_99 = ~c_pop_12; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_101 = ~b_pop_12; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_102 = ~a_pop_12; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_103 = _bypassMatches_T_100 ? _bypassMatches_T_101 : _bypassMatches_T_102; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_104 = _bypassMatches_T_98 ? _bypassMatches_T_99 : _bypassMatches_T_103; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_12 = _bypassMatches_T_97 & _bypassMatches_T_104; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_12 = a_pop_12 | b_pop_12; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_12 = _may_pop_T_12 | c_pop_12; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_12 = _bypass_T_12 & bypassMatches_12; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_12 = may_pop_12 | bypass_12; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_12 = _mshrs_11_io_schedule_bits_reload & _will_reload_T_12; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_11_prio_0 = bypass_12 ? _view__WIRE_11_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_prio_1 = ~bypass_12 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_11_prio_2 = bypass_12 ? _view__WIRE_11_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_control = bypass_12 ? _view__WIRE_11_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_opcode = bypass_12 ? _view__WIRE_11_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_param = bypass_12 ? _view__WIRE_11_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_size = bypass_12 ? _view__WIRE_11_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_source = bypass_12 ? _view__WIRE_11_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_11_tag = bypass_12 ? _view__WIRE_11_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_offset = bypass_12 ? _view__WIRE_11_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_put = bypass_12 ? _view__WIRE_11_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_11_io_allocate_bits_repeat_T = mshrs_11_io_allocate_bits_tag == _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73]
wire _mshrs_11_io_allocate_valid_T = sel_11 & will_reload_12; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire [35:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25]
wire [23:0] _prio_requests_T_1 = _requests_io_valid[35:12]; // @[Scheduler.scala:70:24, :240:65]
wire [35:0] _prio_requests_T_2 = {_prio_requests_T[35:24], _prio_requests_T[23:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}]
wire [11:0] _prio_requests_T_3 = _requests_io_valid[35:24]; // @[Scheduler.scala:70:24, :240:103]
wire [35:0] _prio_requests_T_4 = {_prio_requests_T_2[35:12], _prio_requests_T_2[11:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}]
wire [35:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}]
wire [35:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31]
wire [35:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}]
wire [3:0] pop_index_hi_1 = _pop_index_T_1[35:32]; // @[OneHot.scala:30:18]
wire [31:0] pop_index_lo = _pop_index_T_1[31:0]; // @[OneHot.scala:31:18]
wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _pop_index_T_3 = {28'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] pop_index_hi_2 = _pop_index_T_3[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] pop_index_lo_1 = _pop_index_T_3[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] pop_index_hi_3 = _pop_index_T_5[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] pop_index_lo_2 = _pop_index_T_5[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] pop_index_hi_4 = _pop_index_T_7[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] pop_index_lo_3 = _pop_index_T_7[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] pop_index_hi_5 = _pop_index_T_9[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] pop_index_lo_4 = _pop_index_T_9[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_10 = |pop_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _pop_index_T_11 = pop_index_hi_5 | pop_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _pop_index_T_12 = _pop_index_T_11[1]; // @[OneHot.scala:32:28]
wire [1:0] _pop_index_T_13 = {_pop_index_T_10, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _pop_index_T_14 = {_pop_index_T_8, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _pop_index_T_15 = {_pop_index_T_6, _pop_index_T_14}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _pop_index_T_16 = {_pop_index_T_4, _pop_index_T_15}; // @[OneHot.scala:32:{10,14}]
wire [5:0] pop_index = {_pop_index_T_2, _pop_index_T_16}; // @[OneHot.scala:32:{10,14}]
wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73]
wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}]
wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45]
wire [12:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63]
wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73]
wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}]
wire [1:0] mshr_validOH_lo_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_lo = {mshr_validOH_lo_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_lo_hi_hi = {_mshrs_5_io_status_valid, _mshrs_4_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_hi = {mshr_validOH_lo_hi_hi, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_lo = {mshr_validOH_lo_hi, mshr_validOH_lo_lo}; // @[Scheduler.scala:252:25]
wire [1:0] mshr_validOH_hi_lo_hi = {_mshrs_8_io_status_valid, _mshrs_7_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_lo = {mshr_validOH_hi_lo_hi, _mshrs_6_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_hi_hi_hi = {_mshrs_11_io_status_valid, _mshrs_10_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_hi = {mshr_validOH_hi_hi_hi, _mshrs_9_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25]
wire [11:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25]
wire [11:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20]
wire [11:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}]
wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}]
wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73]
wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16]
wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}]
wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}]
wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}]
wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16]
wire _request_alloc_cases_T_5 = ~_mshrs_10_io_status_valid; // @[Scheduler.scala:71:46, :259:59]
wire _request_alloc_cases_T_7 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87]
wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16]
wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}]
wire _request_alloc_cases_T_12 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59]
wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}]
wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56]
wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66]
wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}]
assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}]
assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40]
wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44]
wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50]
wire [9:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73]
wire [12:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36]
wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55]
wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}]
wire [3:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[11:8]; // @[OneHot.scala:30:18]
wire [7:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[7:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_2 = {4'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_5 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_7 = _requests_io_push_bits_index_T_6[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_8 = {_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_9 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_10 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9}; // @[OneHot.scala:32:{10,14}]
wire [23:0] _requests_io_push_bits_index_T_11 = {lowerMatches1, 12'h0}; // @[Scheduler.scala:200:8, :275:30]
wire [7:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_11[23:16]; // @[OneHot.scala:30:18]
wire [15:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_11[15:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_12 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_13 = {8'h0, requests_io_push_bits_index_hi_3} | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_13[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_13[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_14 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_15 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_15[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_15[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_16 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_17 = requests_io_push_bits_index_hi_5 | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_17[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_17[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_18 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_19 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_20 = _requests_io_push_bits_index_T_19[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_21 = {_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_22 = {_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_23 = {_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_24 = {_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23}; // @[OneHot.scala:32:{10,14}]
wire [35:0] _requests_io_push_bits_index_T_25 = {lowerMatches1, 24'h0}; // @[Scheduler.scala:200:8, :276:30]
wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_25[35:32]; // @[OneHot.scala:30:18]
wire [31:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_25[31:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _requests_io_push_bits_index_T_27 = {28'h0, requests_io_push_bits_index_hi_7} | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_27[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_27[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_28 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_29 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_29[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_29[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_30 = |requests_io_push_bits_index_hi_9; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_31 = requests_io_push_bits_index_hi_9 | requests_io_push_bits_index_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_31[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_31[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_32 = |requests_io_push_bits_index_hi_10; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_33 = requests_io_push_bits_index_hi_10 | requests_io_push_bits_index_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_34 = |requests_io_push_bits_index_hi_11; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_11 | requests_io_push_bits_index_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_36 = _requests_io_push_bits_index_T_35[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_37 = {_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_38 = {_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_39 = {_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_40 = {_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39}; // @[OneHot.scala:32:{10,14}]
wire [5:0] _requests_io_push_bits_index_T_41 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_42 = request_bits_prio_0 ? _requests_io_push_bits_index_T_10 : 4'h0; // @[OneHot.scala:32:10]
wire [5:0] _requests_io_push_bits_index_T_44 = request_bits_prio_2 ? _requests_io_push_bits_index_T_41 : 6'h0; // @[OneHot.scala:32:10]
wire [4:0] _requests_io_push_bits_index_T_45 = {1'h0, _requests_io_push_bits_index_T_42}; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_T_46 = {1'h0, _requests_io_push_bits_index_T_45} | _requests_io_push_bits_index_T_44; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_46; // @[Mux.scala:30:73]
wire [11:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32]
wire [12:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48]
wire [11:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}]
wire [13:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}]
wire [15:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}]
wire [19:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_11 = _mshr_insertOH_T_10[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 | _mshr_insertOH_T_11; // @[package.scala:253:{43,53}]
wire [11:0] _mshr_insertOH_T_13 = _mshr_insertOH_T_12; // @[package.scala:253:43, :254:17]
wire [12:0] _mshr_insertOH_T_14 = {_mshr_insertOH_T_13, 1'h0}; // @[package.scala:254:17]
wire [12:0] _mshr_insertOH_T_15 = ~_mshr_insertOH_T_14; // @[Scheduler.scala:278:{23,47}]
wire [11:0] _mshr_insertOH_T_16 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55]
wire [12:0] _mshr_insertOH_T_17 = {1'h0, _mshr_insertOH_T_15[11:0] & _mshr_insertOH_T_16}; // @[Scheduler.scala:278:{23,53,55}]
wire [12:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_17[11:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}]
wire _T_76 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25]
wire _T_35 = _T_76 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_0_io_allocate_bits_tag = _T_35 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_39 = _T_76 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_1_io_allocate_bits_tag = _T_39 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_43 = _T_76 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_2_io_allocate_bits_tag = _T_43 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_47 = _T_76 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_3_io_allocate_bits_tag = _T_47 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_51 = _T_76 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_4_io_allocate_bits_tag = _T_51 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_55 = _T_76 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_5_io_allocate_bits_tag = _T_55 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_59 = _T_76 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_6_io_allocate_bits_tag = _T_59 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_63 = _T_76 & mshr_insertOH[7] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_7_io_allocate_bits_tag = _T_63 ? request_bits_tag : _view__T_7_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_67 = _T_76 & mshr_insertOH[8] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_8_io_allocate_bits_tag = _T_67 ? request_bits_tag : _view__T_8_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_71 = _T_76 & mshr_insertOH[9] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_9_io_allocate_bits_tag = _T_71 ? request_bits_tag : _view__T_9_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_75 = _T_76 & mshr_insertOH[10] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_10_io_allocate_bits_tag = _T_75 ? request_bits_tag : _view__T_10_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74]
wire _T_95 = request_valid & nestC & ~_mshrs_11_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}]
wire _GEN_3 = _T_95 | _T_76 & mshr_insertOH[11] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30]
assign mshrs_11_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_11_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73] |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_3 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
inst main of BranchKillableQueue_2
connect main.clock, clock
connect main.reset, reset
reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}, clock
regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
connect main.io.enq, io.enq
connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect main.io.brupdate.b2.taken, io.brupdate.b2.taken
connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ
connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm
connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op
connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw
connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd
connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec
connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags
connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt
connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div
connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma
connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe
connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint
connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut
connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn
connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23
connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12
connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3
connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2
connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1
connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen
connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst
connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel
connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel
connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm
connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel
connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename
connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov
connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc
connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret
connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence
connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type
connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel
connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint
connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint
connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child
connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child
connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen
connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen
connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued
connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0]
connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1]
connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2]
connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3]
connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4]
connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5]
connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6]
connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7]
connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8]
connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9]
connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0]
connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1]
connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2]
connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3]
connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect main.io.flush, io.flush
node _io_empty_T = eq(out_valid, UInt<1>(0h0))
node _io_empty_T_1 = and(main.io.empty, _io_empty_T)
connect io.empty, _io_empty_T_1
node _io_count_T = add(main.io.count, out_valid)
node _io_count_T_1 = tail(_io_count_T, 1)
connect io.count, _io_count_T_1
connect io.deq.valid, out_valid
connect io.deq.bits, out_reg
connect io.deq.bits.uop, out_uop
wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out, out_uop
node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T)
connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1
connect out_uop, out_uop_out
node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask)
node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0))
node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0))
node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0))
node _out_valid_T_4 = and(out_valid, _out_valid_T_3)
node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq)
node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0))
node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6)
connect out_valid, _out_valid_T_7
connect main.io.deq.ready, UInt<1>(0h0)
node _T = and(io.deq.ready, io.deq.valid)
node _T_1 = eq(out_valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
when _T_2 :
node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask)
node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0))
node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0))
node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0))
node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11)
node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq)
node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0))
node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14)
connect out_valid, _out_valid_T_15
connect out_reg, main.io.deq.bits
wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect out_uop_out_1, main.io.deq.bits.uop
node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2)
connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3
connect out_uop, out_uop_out_1
connect main.io.deq.ready, UInt<1>(0h1) | module BranchKillableQueue_3( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [39:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [11:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [39:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush, // @[util.scala:463:14]
output io_empty // @[util.scala:463:14]
);
wire _main_io_deq_valid; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22]
wire [39:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22]
wire [11:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22]
wire [6:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22]
wire [39:0] _main_io_deq_bits_addr; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22]
wire _main_io_deq_bits_is_hella; // @[util.scala:476:22]
wire _main_io_deq_bits_tag_match; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_way_en; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22]
wire _main_io_empty; // @[util.scala:476:22]
wire [3:0] _main_io_count; // @[util.scala:476:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire _io_empty_T_1; // @[util.scala:484:31]
wire [3:0] _io_count_T_1; // @[util.scala:485:31]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [11:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count; // @[util.scala:458:7]
reg [31:0] out_reg_uop_inst; // @[util.scala:477:22]
reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22]
reg out_reg_uop_is_rvc; // @[util.scala:477:22]
reg [39:0] out_reg_uop_debug_pc; // @[util.scala:477:22]
reg out_reg_uop_iq_type_0; // @[util.scala:477:22]
reg out_reg_uop_iq_type_1; // @[util.scala:477:22]
reg out_reg_uop_iq_type_2; // @[util.scala:477:22]
reg out_reg_uop_iq_type_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_0; // @[util.scala:477:22]
reg out_reg_uop_fu_code_1; // @[util.scala:477:22]
reg out_reg_uop_fu_code_2; // @[util.scala:477:22]
reg out_reg_uop_fu_code_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_4; // @[util.scala:477:22]
reg out_reg_uop_fu_code_5; // @[util.scala:477:22]
reg out_reg_uop_fu_code_6; // @[util.scala:477:22]
reg out_reg_uop_fu_code_7; // @[util.scala:477:22]
reg out_reg_uop_fu_code_8; // @[util.scala:477:22]
reg out_reg_uop_fu_code_9; // @[util.scala:477:22]
reg out_reg_uop_iw_issued; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22]
reg [1:0] out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22]
reg [1:0] out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dis_col_sel; // @[util.scala:477:22]
reg [11:0] out_reg_uop_br_mask; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_tag; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22]
reg out_reg_uop_is_sfb; // @[util.scala:477:22]
reg out_reg_uop_is_fence; // @[util.scala:477:22]
reg out_reg_uop_is_fencei; // @[util.scala:477:22]
reg out_reg_uop_is_sfence; // @[util.scala:477:22]
reg out_reg_uop_is_amo; // @[util.scala:477:22]
reg out_reg_uop_is_eret; // @[util.scala:477:22]
reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22]
reg out_reg_uop_is_rocc; // @[util.scala:477:22]
reg out_reg_uop_is_mov; // @[util.scala:477:22]
reg [4:0] out_reg_uop_ftq_idx; // @[util.scala:477:22]
reg out_reg_uop_edge_inst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22]
reg out_reg_uop_taken; // @[util.scala:477:22]
reg out_reg_uop_imm_rename; // @[util.scala:477:22]
reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22]
reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22]
reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22]
reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22]
reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22]
reg [5:0] out_reg_uop_rob_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22]
reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22]
reg [6:0] out_reg_uop_pdst; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs1; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs2; // @[util.scala:477:22]
reg [6:0] out_reg_uop_prs3; // @[util.scala:477:22]
reg [4:0] out_reg_uop_ppred; // @[util.scala:477:22]
reg out_reg_uop_prs1_busy; // @[util.scala:477:22]
reg out_reg_uop_prs2_busy; // @[util.scala:477:22]
reg out_reg_uop_prs3_busy; // @[util.scala:477:22]
reg out_reg_uop_ppred_busy; // @[util.scala:477:22]
reg [6:0] out_reg_uop_stale_pdst; // @[util.scala:477:22]
reg out_reg_uop_exception; // @[util.scala:477:22]
reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22]
reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22]
reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22]
reg out_reg_uop_mem_signed; // @[util.scala:477:22]
reg out_reg_uop_uses_ldq; // @[util.scala:477:22]
reg out_reg_uop_uses_stq; // @[util.scala:477:22]
reg out_reg_uop_is_unique; // @[util.scala:477:22]
reg out_reg_uop_flush_on_commit; // @[util.scala:477:22]
reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22]
reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22]
reg out_reg_uop_frs3_en; // @[util.scala:477:22]
reg out_reg_uop_fcn_dw; // @[util.scala:477:22]
reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22]
reg out_reg_uop_fp_val; // @[util.scala:477:22]
reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22]
reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22]
reg out_reg_uop_bp_debug_if; // @[util.scala:477:22]
reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22]
reg [39:0] out_reg_addr; // @[util.scala:477:22]
assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22]
reg [63:0] out_reg_data; // @[util.scala:477:22]
assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22]
reg out_reg_is_hella; // @[util.scala:477:22]
assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22]
reg out_reg_tag_match; // @[util.scala:477:22]
assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22]
assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22]
reg [19:0] out_reg_old_meta_tag; // @[util.scala:477:22]
assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22]
reg [3:0] out_reg_way_en; // @[util.scala:477:22]
assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22]
reg [4:0] out_reg_sdq_id; // @[util.scala:477:22]
assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22]
reg out_valid; // @[util.scala:478:28]
assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28]
reg [31:0] out_uop_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22]
reg [31:0] out_uop_debug_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22]
reg out_uop_is_rvc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22]
reg [39:0] out_uop_debug_pc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22]
wire [39:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_0; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_1; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_2; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_3; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_0; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_1; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_2; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_3; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_4; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_5; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_6; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_7; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_8; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_9; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_iw_p1_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_iw_p2_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dis_col_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22]
reg [11:0] out_uop_br_mask; // @[util.scala:479:22]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22]
reg [3:0] out_uop_br_tag; // @[util.scala:479:22]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_type; // @[util.scala:479:22]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfb; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22]
reg out_uop_is_fence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22]
reg out_uop_is_fencei; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22]
reg out_uop_is_amo; // @[util.scala:479:22]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22]
reg out_uop_is_eret; // @[util.scala:479:22]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22]
reg out_uop_is_sys_pc2epc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22]
reg out_uop_is_rocc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22]
reg out_uop_is_mov; // @[util.scala:479:22]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_ftq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22]
reg out_uop_edge_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22]
wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pc_lob; // @[util.scala:479:22]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22]
reg out_uop_taken; // @[util.scala:479:22]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22]
wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22]
reg out_uop_imm_rename; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22]
wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_imm_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_pimm; // @[util.scala:479:22]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22]
reg [19:0] out_uop_imm_packed; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22]
wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_op1_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_op2_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wen; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_toint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fma; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_div; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_vec; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_rob_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_stq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs1; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs2; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_prs3; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_ppred; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22]
reg out_uop_prs1_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs2_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs3_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22]
reg out_uop_ppred_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22]
reg [6:0] out_uop_stale_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22]
wire [6:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22]
reg out_uop_exception; // @[util.scala:479:22]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22]
wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22]
reg [63:0] out_uop_exc_cause; // @[util.scala:479:22]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22]
wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_mem_size; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22]
reg out_uop_mem_signed; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22]
wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22]
reg out_uop_uses_ldq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22]
reg out_uop_uses_stq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22]
reg out_uop_is_unique; // @[util.scala:479:22]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22]
reg out_uop_flush_on_commit; // @[util.scala:479:22]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22]
wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22]
reg out_uop_ldst_is_rs1; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22]
wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs1; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs2; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs3; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22]
reg out_uop_frs3_en; // @[util.scala:479:22]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22]
wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22]
reg out_uop_fcn_dw; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22]
wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_fcn_op; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22]
reg out_uop_fp_val; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_fp_rm; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_typ; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_pf_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ae_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ma_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_debug_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_xcpt_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22]
wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34]
assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31]
wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:476:22, :478:28, :485:31]
assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31]
assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31]
wire [11:0] _out_uop_out_br_mask_T_1; // @[util.scala:93:25]
wire [11:0] out_uop_out_br_mask; // @[util.scala:104:23]
wire [11:0] _out_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7]
assign _out_uop_out_br_mask_T_1 = out_uop_br_mask & _out_uop_out_br_mask_T; // @[util.scala:93:{25,27}, :479:22]
assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire [11:0] _out_valid_T = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:126:51, :458:7, :479:22]
wire _out_valid_T_1 = |_out_valid_T; // @[util.scala:126:{51,59}]
wire _out_valid_T_2 = _out_valid_T_1; // @[util.scala:61:61, :126:59]
wire _out_valid_T_3 = ~_out_valid_T_2; // @[util.scala:61:61, :492:31]
wire _out_valid_T_4 = out_valid & _out_valid_T_3; // @[util.scala:478:28, :492:{28,31}]
wire _out_valid_T_5 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:458:7, :479:22, :492:94]
wire _out_valid_T_6 = ~_out_valid_T_5; // @[util.scala:492:{83,94}]
wire _out_valid_T_7 = _out_valid_T_4 & _out_valid_T_6; // @[util.scala:492:{28,80,83}]
wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35]
wire [11:0] _out_valid_T_8 = io_brupdate_b1_mispredict_mask_0 & _main_io_deq_bits_uop_br_mask; // @[util.scala:126:51, :458:7, :476:22]
wire _out_valid_T_9 = |_out_valid_T_8; // @[util.scala:126:{51,59}]
wire _out_valid_T_10 = _out_valid_T_9; // @[util.scala:61:61, :126:59]
wire _out_valid_T_11 = ~_out_valid_T_10; // @[util.scala:61:61, :496:41]
wire _out_valid_T_12 = _main_io_deq_valid & _out_valid_T_11; // @[util.scala:476:22, :496:{38,41}]
wire _out_valid_T_13 = io_flush_0 & _main_io_deq_bits_uop_uses_ldq; // @[util.scala:458:7, :476:22, :496:117]
wire _out_valid_T_14 = ~_out_valid_T_13; // @[util.scala:496:{106,117}]
wire _out_valid_T_15 = _out_valid_T_12 & _out_valid_T_14; // @[util.scala:496:{38,103,106}]
wire [11:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25]
wire out_uop_out_1_iq_type_0; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_1; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_2; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_0; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_1; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_2; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_4; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_5; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_6; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_7; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_8; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_9; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23]
wire out_uop_out_1_is_rvc; // @[util.scala:104:23]
wire [39:0] out_uop_out_1_debug_pc; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dis_col_sel; // @[util.scala:104:23]
wire [11:0] out_uop_out_1_br_mask; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_tag; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23]
wire out_uop_out_1_is_sfb; // @[util.scala:104:23]
wire out_uop_out_1_is_fence; // @[util.scala:104:23]
wire out_uop_out_1_is_fencei; // @[util.scala:104:23]
wire out_uop_out_1_is_sfence; // @[util.scala:104:23]
wire out_uop_out_1_is_amo; // @[util.scala:104:23]
wire out_uop_out_1_is_eret; // @[util.scala:104:23]
wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23]
wire out_uop_out_1_is_rocc; // @[util.scala:104:23]
wire out_uop_out_1_is_mov; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23]
wire out_uop_out_1_edge_inst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23]
wire out_uop_out_1_taken; // @[util.scala:104:23]
wire out_uop_out_1_imm_rename; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23]
wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_rob_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_pdst; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs1; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs2; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_prs3; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_ppred; // @[util.scala:104:23]
wire out_uop_out_1_prs1_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs2_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs3_busy; // @[util.scala:104:23]
wire out_uop_out_1_ppred_busy; // @[util.scala:104:23]
wire [6:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23]
wire out_uop_out_1_exception; // @[util.scala:104:23]
wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23]
wire out_uop_out_1_mem_signed; // @[util.scala:104:23]
wire out_uop_out_1_uses_ldq; // @[util.scala:104:23]
wire out_uop_out_1_uses_stq; // @[util.scala:104:23]
wire out_uop_out_1_is_unique; // @[util.scala:104:23]
wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23]
wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23]
wire out_uop_out_1_frs3_en; // @[util.scala:104:23]
wire out_uop_out_1_fcn_dw; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23]
wire out_uop_out_1_fp_val; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _out_uop_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :458:7]
assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask & _out_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}, :476:22]
assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
always @(posedge clock) begin // @[util.scala:458:7]
if (main_io_deq_ready) begin // @[util.scala:495:23]
out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22]
out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22]
out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22]
out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22]
out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22]
out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22]
out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22]
out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22]
out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22]
out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22]
out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22]
out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22]
out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22]
out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22]
out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22]
out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22]
out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22]
out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22]
out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22]
out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22]
out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22]
end
out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
if (reset) // @[util.scala:458:7]
out_valid <= 1'h0; // @[util.scala:478:28]
else // @[util.scala:458:7]
out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}]
always @(posedge)
BranchKillableQueue_2 main ( // @[util.scala:476:22]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[util.scala:458:7]
.io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7]
.io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7]
.io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7]
.io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7]
.io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7]
.io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7]
.io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7]
.io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7]
.io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7]
.io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7]
.io_deq_ready (main_io_deq_ready), // @[util.scala:495:23]
.io_deq_valid (_main_io_deq_valid),
.io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst),
.io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst),
.io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc),
.io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc),
.io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0),
.io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1),
.io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2),
.io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3),
.io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0),
.io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1),
.io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2),
.io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3),
.io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4),
.io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5),
.io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6),
.io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7),
.io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8),
.io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9),
.io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued),
.io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen),
.io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen),
.io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child),
.io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child),
.io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint),
.io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint),
.io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint),
.io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel),
.io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag),
.io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type),
.io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb),
.io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence),
.io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei),
.io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence),
.io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret),
.io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc),
.io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc),
.io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov),
.io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx),
.io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst),
.io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob),
.io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken),
.io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename),
.io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel),
.io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm),
.io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed),
.io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel),
.io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel),
.io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst),
.io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen),
.io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1),
.io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2),
.io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3),
.io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12),
.io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23),
.io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn),
.io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut),
.io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint),
.io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint),
.io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe),
.io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma),
.io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div),
.io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt),
.io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags),
.io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec),
.io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx),
.io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx),
.io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst),
.io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1),
.io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2),
.io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3),
.io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred),
.io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy),
.io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy),
.io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy),
.io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy),
.io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst),
.io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception),
.io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause),
.io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd),
.io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size),
.io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed),
.io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq),
.io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique),
.io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit),
.io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd),
.io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1),
.io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst),
.io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1),
.io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2),
.io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3),
.io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype),
.io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype),
.io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en),
.io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw),
.io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op),
.io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val),
.io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm),
.io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ),
.io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if),
.io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if),
.io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if),
.io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if),
.io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if),
.io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc),
.io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc),
.io_deq_bits_addr (_main_io_deq_bits_addr),
.io_deq_bits_data (_main_io_deq_bits_data),
.io_deq_bits_is_hella (_main_io_deq_bits_is_hella),
.io_deq_bits_tag_match (_main_io_deq_bits_tag_match),
.io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state),
.io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag),
.io_deq_bits_way_en (_main_io_deq_bits_way_en),
.io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0), // @[util.scala:458:7]
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_0 (io_brupdate_b2_uop_iq_type_0_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_1 (io_brupdate_b2_uop_iq_type_1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_2 (io_brupdate_b2_uop_iq_type_2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iq_type_3 (io_brupdate_b2_uop_iq_type_3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_0 (io_brupdate_b2_uop_fu_code_0_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_1 (io_brupdate_b2_uop_fu_code_1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_2 (io_brupdate_b2_uop_fu_code_2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_3 (io_brupdate_b2_uop_fu_code_3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_4 (io_brupdate_b2_uop_fu_code_4_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_5 (io_brupdate_b2_uop_fu_code_5_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_6 (io_brupdate_b2_uop_fu_code_6_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_7 (io_brupdate_b2_uop_fu_code_7_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_8 (io_brupdate_b2_uop_fu_code_8_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fu_code_9 (io_brupdate_b2_uop_fu_code_9_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued (io_brupdate_b2_uop_iw_issued_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued_partial_agen (io_brupdate_b2_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_issued_partial_dgen (io_brupdate_b2_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p1_speculative_child (io_brupdate_b2_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p2_speculative_child (io_brupdate_b2_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p1_bypass_hint (io_brupdate_b2_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p2_bypass_hint (io_brupdate_b2_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_iw_p3_bypass_hint (io_brupdate_b2_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_dis_col_sel (io_brupdate_b2_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_br_type (io_brupdate_b2_uop_br_type_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sfence (io_brupdate_b2_uop_is_sfence_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_eret (io_brupdate_b2_uop_is_eret_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_rocc (io_brupdate_b2_uop_is_rocc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_mov (io_brupdate_b2_uop_is_mov_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_rename (io_brupdate_b2_uop_imm_rename_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_sel (io_brupdate_b2_uop_imm_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pimm (io_brupdate_b2_uop_pimm_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_op1_sel (io_brupdate_b2_uop_op1_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_op2_sel (io_brupdate_b2_uop_op2_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ldst (io_brupdate_b2_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_wen (io_brupdate_b2_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren1 (io_brupdate_b2_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren2 (io_brupdate_b2_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_ren3 (io_brupdate_b2_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_swap12 (io_brupdate_b2_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_swap23 (io_brupdate_b2_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_typeTagIn (io_brupdate_b2_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_typeTagOut (io_brupdate_b2_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fromint (io_brupdate_b2_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_toint (io_brupdate_b2_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fastpipe (io_brupdate_b2_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_fma (io_brupdate_b2_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_div (io_brupdate_b2_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_sqrt (io_brupdate_b2_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_wflags (io_brupdate_b2_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_ctrl_vec (io_brupdate_b2_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_csr_cmd (io_brupdate_b2_uop_csr_cmd_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fcn_dw (io_brupdate_b2_uop_fcn_dw_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fcn_op (io_brupdate_b2_uop_fcn_op_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_rm (io_brupdate_b2_uop_fp_rm_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_fp_typ (io_brupdate_b2_uop_fp_typ_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0), // @[util.scala:458:7]
.io_brupdate_b2_taken (io_brupdate_b2_taken_0), // @[util.scala:458:7]
.io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0), // @[util.scala:458:7]
.io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0), // @[util.scala:458:7]
.io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0), // @[util.scala:458:7]
.io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0), // @[util.scala:458:7]
.io_flush (io_flush_0), // @[util.scala:458:7]
.io_empty (_main_io_empty),
.io_count (_main_io_count)
); // @[util.scala:476:22]
assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_501 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_501( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T = shr(io.in.a.bits.source, 3)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_4 = shr(io.in.a.bits.source, 3)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<3>(0h4))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_24 = shr(io.in.a.bits.source, 3)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<3>(0h4))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_34 = and(_T_32, _T_33)
node _T_35 = or(UInt<1>(0h0), _T_34)
node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_37 = cvt(_T_36)
node _T_38 = and(_T_37, asSInt(UInt<17>(0h100c0)))
node _T_39 = asSInt(_T_38)
node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0)))
node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_42 = cvt(_T_41)
node _T_43 = and(_T_42, asSInt(UInt<29>(0h100000c0)))
node _T_44 = asSInt(_T_43)
node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0)))
node _T_46 = or(_T_40, _T_45)
node _T_47 = and(_T_35, _T_46)
node _T_48 = or(UInt<1>(0h0), _T_47)
node _T_49 = and(_T_31, _T_48)
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_49, UInt<1>(0h1), "") : assert_2
node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_56 = and(_T_54, _T_55)
node _T_57 = or(UInt<1>(0h0), _T_56)
node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<17>(0h100c0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<29>(0h100000c0)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = or(_T_62, _T_67)
node _T_69 = and(_T_57, _T_68)
node _T_70 = or(UInt<1>(0h0), _T_69)
node _T_71 = and(_T_53, _T_70)
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(_T_71, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_71, UInt<1>(0h1), "") : assert_3
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_78, UInt<1>(0h1), "") : assert_5
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(is_aligned, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_85, UInt<1>(0h1), "") : assert_7
node _T_89 = not(io.in.a.bits.mask)
node _T_90 = eq(_T_89, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_90, UInt<1>(0h1), "") : assert_8
node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_98 :
node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_101 = and(_T_99, _T_100)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0)
node _T_102 = shr(io.in.a.bits.source, 3)
node _T_103 = eq(_T_102, UInt<1>(0h0))
node _T_104 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_105 = and(_T_103, _T_104)
node _T_106 = leq(uncommonBits_2, UInt<3>(0h4))
node _T_107 = and(_T_105, _T_106)
node _T_108 = and(_T_101, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_112 = and(_T_110, _T_111)
node _T_113 = or(UInt<1>(0h0), _T_112)
node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<17>(0h100c0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_120 = cvt(_T_119)
node _T_121 = and(_T_120, asSInt(UInt<29>(0h100000c0)))
node _T_122 = asSInt(_T_121)
node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = or(_T_118, _T_123)
node _T_125 = and(_T_113, _T_124)
node _T_126 = or(UInt<1>(0h0), _T_125)
node _T_127 = and(_T_109, _T_126)
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(_T_127, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_127, UInt<1>(0h1), "") : assert_10
node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_134 = and(_T_132, _T_133)
node _T_135 = or(UInt<1>(0h0), _T_134)
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h100c0)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<29>(0h100000c0)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = or(_T_140, _T_145)
node _T_147 = and(_T_135, _T_146)
node _T_148 = or(UInt<1>(0h0), _T_147)
node _T_149 = and(_T_131, _T_148)
node _T_150 = asUInt(reset)
node _T_151 = eq(_T_150, UInt<1>(0h0))
when _T_151 :
node _T_152 = eq(_T_149, UInt<1>(0h0))
when _T_152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_149, UInt<1>(0h1), "") : assert_11
node _T_153 = asUInt(reset)
node _T_154 = eq(_T_153, UInt<1>(0h0))
when _T_154 :
node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_156, UInt<1>(0h1), "") : assert_13
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(is_aligned, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_163, UInt<1>(0h1), "") : assert_15
node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_168 = asUInt(reset)
node _T_169 = eq(_T_168, UInt<1>(0h0))
when _T_169 :
node _T_170 = eq(_T_167, UInt<1>(0h0))
when _T_170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_167, UInt<1>(0h1), "") : assert_16
node _T_171 = not(io.in.a.bits.mask)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_172, UInt<1>(0h1), "") : assert_17
node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_176, UInt<1>(0h1), "") : assert_18
node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_180 :
node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_183 = and(_T_181, _T_182)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0)
node _T_184 = shr(io.in.a.bits.source, 3)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_187 = and(_T_185, _T_186)
node _T_188 = leq(uncommonBits_3, UInt<3>(0h4))
node _T_189 = and(_T_187, _T_188)
node _T_190 = and(_T_183, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_191, UInt<1>(0h1), "") : assert_19
node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_197 = and(_T_195, _T_196)
node _T_198 = or(UInt<1>(0h0), _T_197)
node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<17>(0h100c0)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<29>(0h100000c0)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_203, _T_208)
node _T_210 = and(_T_198, _T_209)
node _T_211 = or(UInt<1>(0h0), _T_210)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_211, UInt<1>(0h1), "") : assert_20
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(is_aligned, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_221, UInt<1>(0h1), "") : assert_23
node _T_225 = eq(io.in.a.bits.mask, mask)
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_225, UInt<1>(0h1), "") : assert_24
node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_229, UInt<1>(0h1), "") : assert_25
node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_233 :
node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_237 = shr(io.in.a.bits.source, 3)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_4, UInt<3>(0h4))
node _T_242 = and(_T_240, _T_241)
node _T_243 = and(_T_236, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_247 = and(_T_245, _T_246)
node _T_248 = or(UInt<1>(0h0), _T_247)
node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<17>(0h100c0)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<29>(0h100000c0)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = or(_T_253, _T_258)
node _T_260 = and(_T_248, _T_259)
node _T_261 = or(UInt<1>(0h0), _T_260)
node _T_262 = and(_T_244, _T_261)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_262, UInt<1>(0h1), "") : assert_26
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(is_aligned, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_272, UInt<1>(0h1), "") : assert_29
node _T_276 = eq(io.in.a.bits.mask, mask)
node _T_277 = asUInt(reset)
node _T_278 = eq(_T_277, UInt<1>(0h0))
when _T_278 :
node _T_279 = eq(_T_276, UInt<1>(0h0))
when _T_279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_276, UInt<1>(0h1), "") : assert_30
node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_280 :
node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_284 = shr(io.in.a.bits.source, 3)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_5, UInt<3>(0h4))
node _T_289 = and(_T_287, _T_288)
node _T_290 = and(_T_283, _T_289)
node _T_291 = or(UInt<1>(0h0), _T_290)
node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_294 = and(_T_292, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h100c0)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h100000c0)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = and(_T_291, _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_309, UInt<1>(0h1), "") : assert_31
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(is_aligned, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(_T_319, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_319, UInt<1>(0h1), "") : assert_34
node _T_323 = not(mask)
node _T_324 = and(io.in.a.bits.mask, _T_323)
node _T_325 = eq(_T_324, UInt<1>(0h0))
node _T_326 = asUInt(reset)
node _T_327 = eq(_T_326, UInt<1>(0h0))
when _T_327 :
node _T_328 = eq(_T_325, UInt<1>(0h0))
when _T_328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_325, UInt<1>(0h1), "") : assert_35
node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_329 :
node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_333 = shr(io.in.a.bits.source, 3)
node _T_334 = eq(_T_333, UInt<1>(0h0))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_6, UInt<3>(0h4))
node _T_338 = and(_T_336, _T_337)
node _T_339 = and(_T_332, _T_338)
node _T_340 = or(UInt<1>(0h0), _T_339)
node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<17>(0h100c0)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<29>(0h100000c0)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = or(_T_346, _T_351)
node _T_353 = and(_T_341, _T_352)
node _T_354 = or(UInt<1>(0h0), _T_353)
node _T_355 = and(_T_340, _T_354)
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_355, UInt<1>(0h1), "") : assert_36
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(is_aligned, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_365, UInt<1>(0h1), "") : assert_39
node _T_369 = eq(io.in.a.bits.mask, mask)
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_369, UInt<1>(0h1), "") : assert_40
node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_373 :
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_377 = shr(io.in.a.bits.source, 3)
node _T_378 = eq(_T_377, UInt<1>(0h0))
node _T_379 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_380 = and(_T_378, _T_379)
node _T_381 = leq(uncommonBits_7, UInt<3>(0h4))
node _T_382 = and(_T_380, _T_381)
node _T_383 = and(_T_376, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_387 = cvt(_T_386)
node _T_388 = and(_T_387, asSInt(UInt<17>(0h100c0)))
node _T_389 = asSInt(_T_388)
node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0)))
node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_392 = cvt(_T_391)
node _T_393 = and(_T_392, asSInt(UInt<29>(0h100000c0)))
node _T_394 = asSInt(_T_393)
node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0)))
node _T_396 = or(_T_390, _T_395)
node _T_397 = and(_T_385, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = and(_T_384, _T_398)
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_399, UInt<1>(0h1), "") : assert_41
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(is_aligned, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_409, UInt<1>(0h1), "") : assert_44
node _T_413 = eq(io.in.a.bits.mask, mask)
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_413, UInt<1>(0h1), "") : assert_45
node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_417 :
node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0)
node _T_421 = shr(io.in.a.bits.source, 3)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_8, UInt<3>(0h4))
node _T_426 = and(_T_424, _T_425)
node _T_427 = and(_T_420, _T_426)
node _T_428 = or(UInt<1>(0h0), _T_427)
node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000080))
node _T_431 = cvt(_T_430)
node _T_432 = and(_T_431, asSInt(UInt<17>(0h100c0)))
node _T_433 = asSInt(_T_432)
node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0)))
node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000080))
node _T_436 = cvt(_T_435)
node _T_437 = and(_T_436, asSInt(UInt<29>(0h100000c0)))
node _T_438 = asSInt(_T_437)
node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0)))
node _T_440 = or(_T_434, _T_439)
node _T_441 = and(_T_429, _T_440)
node _T_442 = or(UInt<1>(0h0), _T_441)
node _T_443 = and(_T_428, _T_442)
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_443, UInt<1>(0h1), "") : assert_46
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(is_aligned, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_453, UInt<1>(0h1), "") : assert_49
node _T_457 = eq(io.in.a.bits.mask, mask)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_457, UInt<1>(0h1), "") : assert_50
node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_461, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_465, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 3)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h4))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_469 :
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_473, UInt<1>(0h1), "") : assert_54
node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_477, UInt<1>(0h1), "") : assert_55
node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_481, UInt<1>(0h1), "") : assert_56
node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_485, UInt<1>(0h1), "") : assert_57
node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_489 :
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(sink_ok, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_496, UInt<1>(0h1), "") : assert_60
node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_500, UInt<1>(0h1), "") : assert_61
node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_504, UInt<1>(0h1), "") : assert_62
node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_509 = asUInt(reset)
node _T_510 = eq(_T_509, UInt<1>(0h0))
when _T_510 :
node _T_511 = eq(_T_508, UInt<1>(0h0))
when _T_511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_508, UInt<1>(0h1), "") : assert_63
node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_513 = or(UInt<1>(0h1), _T_512)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_513, UInt<1>(0h1), "") : assert_64
node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_517 :
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(sink_ok, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_524, UInt<1>(0h1), "") : assert_67
node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_528, UInt<1>(0h1), "") : assert_68
node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_532, UInt<1>(0h1), "") : assert_69
node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_537 = or(_T_536, io.in.d.bits.corrupt)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_537, UInt<1>(0h1), "") : assert_70
node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_542 = or(UInt<1>(0h1), _T_541)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_542, UInt<1>(0h1), "") : assert_71
node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_546 :
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_550, UInt<1>(0h1), "") : assert_73
node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_554, UInt<1>(0h1), "") : assert_74
node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_559 = or(UInt<1>(0h1), _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_559, UInt<1>(0h1), "") : assert_75
node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_563 :
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_567, UInt<1>(0h1), "") : assert_77
node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_572 = or(_T_571, io.in.d.bits.corrupt)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_572, UInt<1>(0h1), "") : assert_78
node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_577 = or(UInt<1>(0h1), _T_576)
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_577, UInt<1>(0h1), "") : assert_79
node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_581 :
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_585, UInt<1>(0h1), "") : assert_81
node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_589, UInt<1>(0h1), "") : assert_82
node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_594 = or(UInt<1>(0h1), _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_594, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_598, UInt<1>(0h1), "") : assert_84
node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_602 = shr(io.in.b.bits.source, 3)
node _T_603 = eq(_T_602, UInt<1>(0h0))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_9, UInt<3>(0h4))
node _T_607 = and(_T_605, _T_606)
node _T_608 = eq(_T_607, UInt<1>(0h0))
node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<1>(0h0)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_608, _T_613)
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_614, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0)
node _legal_source_T = shr(io.in.b.bits.source, 3)
node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0))
node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2)
node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4))
node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4)
wire _legal_source_WIRE : UInt<1>[1]
connect _legal_source_WIRE[0], _legal_source_T_5
node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source)
node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_618 :
node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_622 = and(_T_620, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h100c0)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<29>(0h100000c0)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = or(_T_628, _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = or(UInt<1>(0h0), _T_635)
node _T_637 = and(_T_619, _T_636)
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(_T_637, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_637, UInt<1>(0h1), "") : assert_86
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(address_ok, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(legal_source, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(is_aligned_1, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_650, UInt<1>(0h1), "") : assert_90
node _T_654 = eq(io.in.b.bits.mask, mask_1)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_654, UInt<1>(0h1), "") : assert_91
node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_659 = asUInt(reset)
node _T_660 = eq(_T_659, UInt<1>(0h0))
when _T_660 :
node _T_661 = eq(_T_658, UInt<1>(0h0))
when _T_661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_658, UInt<1>(0h1), "") : assert_92
node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_662 :
node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_665 = and(_T_663, _T_664)
node _T_666 = or(UInt<1>(0h0), _T_665)
node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_668 = cvt(_T_667)
node _T_669 = and(_T_668, asSInt(UInt<17>(0h100c0)))
node _T_670 = asSInt(_T_669)
node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0)))
node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_673 = cvt(_T_672)
node _T_674 = and(_T_673, asSInt(UInt<29>(0h100000c0)))
node _T_675 = asSInt(_T_674)
node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0)))
node _T_677 = or(_T_671, _T_676)
node _T_678 = and(_T_666, _T_677)
node _T_679 = or(UInt<1>(0h0), _T_678)
node _T_680 = and(UInt<1>(0h0), _T_679)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_680, UInt<1>(0h1), "") : assert_93
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(address_ok, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(legal_source, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(is_aligned_1, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_693, UInt<1>(0h1), "") : assert_97
node _T_697 = eq(io.in.b.bits.mask, mask_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_697, UInt<1>(0h1), "") : assert_98
node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_701, UInt<1>(0h1), "") : assert_99
node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_705 :
node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_708 = and(_T_706, _T_707)
node _T_709 = or(UInt<1>(0h0), _T_708)
node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<17>(0h100c0)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<29>(0h100000c0)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = or(_T_714, _T_719)
node _T_721 = and(_T_709, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = and(UInt<1>(0h0), _T_722)
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(_T_723, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_723, UInt<1>(0h1), "") : assert_100
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(address_ok, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(legal_source, UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned_1, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_736, UInt<1>(0h1), "") : assert_104
node _T_740 = eq(io.in.b.bits.mask, mask_1)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_740, UInt<1>(0h1), "") : assert_105
node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = or(UInt<1>(0h0), _T_747)
node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_750 = cvt(_T_749)
node _T_751 = and(_T_750, asSInt(UInt<17>(0h100c0)))
node _T_752 = asSInt(_T_751)
node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0)))
node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<29>(0h100000c0)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = or(_T_753, _T_758)
node _T_760 = and(_T_748, _T_759)
node _T_761 = or(UInt<1>(0h0), _T_760)
node _T_762 = and(UInt<1>(0h0), _T_761)
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_762, UInt<1>(0h1), "") : assert_106
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(address_ok, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(legal_source, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(is_aligned_1, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_775, UInt<1>(0h1), "") : assert_110
node _T_779 = not(mask_1)
node _T_780 = and(io.in.b.bits.mask, _T_779)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_781, UInt<1>(0h1), "") : assert_111
node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_785 :
node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<17>(0h100c0)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h100000c0)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_794, _T_799)
node _T_801 = and(_T_789, _T_800)
node _T_802 = or(UInt<1>(0h0), _T_801)
node _T_803 = and(UInt<1>(0h0), _T_802)
node _T_804 = asUInt(reset)
node _T_805 = eq(_T_804, UInt<1>(0h0))
when _T_805 :
node _T_806 = eq(_T_803, UInt<1>(0h0))
when _T_806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_803, UInt<1>(0h1), "") : assert_112
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(address_ok, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(legal_source, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(is_aligned_1, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(_T_816, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_816, UInt<1>(0h1), "") : assert_116
node _T_820 = eq(io.in.b.bits.mask, mask_1)
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_820, UInt<1>(0h1), "") : assert_117
node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_824 :
node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_827 = and(_T_825, _T_826)
node _T_828 = or(UInt<1>(0h0), _T_827)
node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<17>(0h100c0)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<29>(0h100000c0)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = or(_T_833, _T_838)
node _T_840 = and(_T_828, _T_839)
node _T_841 = or(UInt<1>(0h0), _T_840)
node _T_842 = and(UInt<1>(0h0), _T_841)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_842, UInt<1>(0h1), "") : assert_118
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(address_ok, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_849 = asUInt(reset)
node _T_850 = eq(_T_849, UInt<1>(0h0))
when _T_850 :
node _T_851 = eq(legal_source, UInt<1>(0h0))
when _T_851 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(is_aligned_1, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_855, UInt<1>(0h1), "") : assert_122
node _T_859 = eq(io.in.b.bits.mask, mask_1)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_859, UInt<1>(0h1), "") : assert_123
node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_863 :
node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_866 = and(_T_864, _T_865)
node _T_867 = or(UInt<1>(0h0), _T_866)
node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<17>(0h100c0)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<29>(0h100000c0)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = or(_T_872, _T_877)
node _T_879 = and(_T_867, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_879)
node _T_881 = and(UInt<1>(0h0), _T_880)
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_881, UInt<1>(0h1), "") : assert_124
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(address_ok, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(legal_source, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(is_aligned_1, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_894 = eq(io.in.b.bits.mask, mask_1)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_894, UInt<1>(0h1), "") : assert_128
node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_898, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_902, UInt<1>(0h1), "") : assert_130
node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0)
node _source_ok_T_12 = shr(io.in.c.bits.source, 3)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h4))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
wire _source_ok_WIRE_2 : UInt<1>[1]
connect _source_ok_WIRE_2[0], _source_ok_T_17
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0)
node _T_906 = shr(io.in.c.bits.source, 3)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_909 = and(_T_907, _T_908)
node _T_910 = leq(uncommonBits_10, UInt<3>(0h4))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(_T_911, UInt<1>(0h0))
node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_914 = cvt(_T_913)
node _T_915 = and(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = asSInt(_T_915)
node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0)))
node _T_918 = or(_T_912, _T_917)
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_918, UInt<1>(0h1), "") : assert_131
node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_922 :
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(address_ok_1, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133
node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_929, UInt<1>(0h1), "") : assert_134
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(is_aligned_2, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(_T_936, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_936, UInt<1>(0h1), "") : assert_136
node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_940, UInt<1>(0h1), "") : assert_137
node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_944 :
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(address_ok_1, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139
node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_951, UInt<1>(0h1), "") : assert_140
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(is_aligned_2, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_958, UInt<1>(0h1), "") : assert_142
node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_962 :
node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_965 = and(_T_963, _T_964)
node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_966 = shr(io.in.c.bits.source, 3)
node _T_967 = eq(_T_966, UInt<1>(0h0))
node _T_968 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_969 = and(_T_967, _T_968)
node _T_970 = leq(uncommonBits_11, UInt<3>(0h4))
node _T_971 = and(_T_969, _T_970)
node _T_972 = and(_T_965, _T_971)
node _T_973 = or(UInt<1>(0h0), _T_972)
node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_976 = and(_T_974, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_979 = cvt(_T_978)
node _T_980 = and(_T_979, asSInt(UInt<17>(0h100c0)))
node _T_981 = asSInt(_T_980)
node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0)))
node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_984 = cvt(_T_983)
node _T_985 = and(_T_984, asSInt(UInt<29>(0h100000c0)))
node _T_986 = asSInt(_T_985)
node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0)))
node _T_988 = or(_T_982, _T_987)
node _T_989 = and(_T_977, _T_988)
node _T_990 = or(UInt<1>(0h0), _T_989)
node _T_991 = and(_T_973, _T_990)
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_991, UInt<1>(0h1), "") : assert_143
node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_998 = and(_T_996, _T_997)
node _T_999 = or(UInt<1>(0h0), _T_998)
node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_1001 = cvt(_T_1000)
node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h100c0)))
node _T_1003 = asSInt(_T_1002)
node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0)))
node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_1006 = cvt(_T_1005)
node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h100000c0)))
node _T_1008 = asSInt(_T_1007)
node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0)))
node _T_1010 = or(_T_1004, _T_1009)
node _T_1011 = and(_T_999, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = and(_T_995, _T_1012)
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145
node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148
node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149
node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1035 :
node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1038 = and(_T_1036, _T_1037)
node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_1039 = shr(io.in.c.bits.source, 3)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = leq(uncommonBits_12, UInt<3>(0h4))
node _T_1044 = and(_T_1042, _T_1043)
node _T_1045 = and(_T_1038, _T_1044)
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = or(UInt<1>(0h0), _T_1049)
node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_1052 = cvt(_T_1051)
node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h100c0)))
node _T_1054 = asSInt(_T_1053)
node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0)))
node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_1057 = cvt(_T_1056)
node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h100000c0)))
node _T_1059 = asSInt(_T_1058)
node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0)))
node _T_1061 = or(_T_1055, _T_1060)
node _T_1062 = and(_T_1050, _T_1061)
node _T_1063 = or(UInt<1>(0h0), _T_1062)
node _T_1064 = and(_T_1046, _T_1063)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150
node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = or(UInt<1>(0h0), _T_1071)
node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _T_1074 = cvt(_T_1073)
node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h100c0)))
node _T_1076 = asSInt(_T_1075)
node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0)))
node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _T_1079 = cvt(_T_1078)
node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h100000c0)))
node _T_1081 = asSInt(_T_1080)
node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0)))
node _T_1083 = or(_T_1077, _T_1082)
node _T_1084 = and(_T_1072, _T_1083)
node _T_1085 = or(UInt<1>(0h0), _T_1084)
node _T_1086 = and(_T_1068, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152
node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155
node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(address_ok_1, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159
node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160
node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_1122 :
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(address_ok_1, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164
node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_1136 :
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(address_ok_1, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168
node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(sink_ok_1, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1157 = eq(a_first, UInt<1>(0h0))
node _T_1158 = and(io.in.a.valid, _T_1157)
when _T_1158 :
node _T_1159 = eq(io.in.a.bits.opcode, opcode)
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171
node _T_1163 = eq(io.in.a.bits.param, param)
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172
node _T_1167 = eq(io.in.a.bits.size, size)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173
node _T_1171 = eq(io.in.a.bits.source, source)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174
node _T_1175 = eq(io.in.a.bits.address, address)
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175
node _T_1179 = and(io.in.a.ready, io.in.a.valid)
node _T_1180 = and(_T_1179, a_first)
when _T_1180 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1181 = eq(d_first, UInt<1>(0h0))
node _T_1182 = and(io.in.d.valid, _T_1181)
when _T_1182 :
node _T_1183 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(_T_1183, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176
node _T_1187 = eq(io.in.d.bits.param, param_1)
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177
node _T_1191 = eq(io.in.d.bits.size, size_1)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178
node _T_1195 = eq(io.in.d.bits.source, source_1)
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179
node _T_1199 = eq(io.in.d.bits.sink, sink)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180
node _T_1203 = eq(io.in.d.bits.denied, denied)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181
node _T_1207 = and(io.in.d.ready, io.in.d.valid)
node _T_1208 = and(_T_1207, d_first)
when _T_1208 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_1209 = eq(b_first, UInt<1>(0h0))
node _T_1210 = and(io.in.b.valid, _T_1209)
when _T_1210 :
node _T_1211 = eq(io.in.b.bits.opcode, opcode_2)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182
node _T_1215 = eq(io.in.b.bits.param, param_2)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183
node _T_1219 = eq(io.in.b.bits.size, size_2)
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184
node _T_1223 = eq(io.in.b.bits.source, source_2)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185
node _T_1227 = eq(io.in.b.bits.address, address_1)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186
node _T_1231 = and(io.in.b.ready, io.in.b.valid)
node _T_1232 = and(_T_1231, b_first)
when _T_1232 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_1233 = eq(c_first, UInt<1>(0h0))
node _T_1234 = and(io.in.c.valid, _T_1233)
when _T_1234 :
node _T_1235 = eq(io.in.c.bits.opcode, opcode_3)
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187
node _T_1239 = eq(io.in.c.bits.param, param_3)
node _T_1240 = asUInt(reset)
node _T_1241 = eq(_T_1240, UInt<1>(0h0))
when _T_1241 :
node _T_1242 = eq(_T_1239, UInt<1>(0h0))
when _T_1242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188
node _T_1243 = eq(io.in.c.bits.size, size_3)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189
node _T_1247 = eq(io.in.c.bits.source, source_3)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190
node _T_1251 = eq(io.in.c.bits.address, address_2)
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191
node _T_1255 = and(io.in.c.ready, io.in.c.valid)
node _T_1256 = and(_T_1255, c_first)
when _T_1256 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes : UInt<20>, clock, reset, UInt<20>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<5>
connect a_set, UInt<5>(0h0)
wire a_set_wo_ready : UInt<5>
connect a_set_wo_ready, UInt<5>(0h0)
wire a_opcodes_set : UInt<20>
connect a_opcodes_set, UInt<20>(0h0)
wire a_sizes_set : UInt<20>
connect a_sizes_set, UInt<20>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1257 = and(io.in.a.valid, a_first_1)
node _T_1258 = and(_T_1257, UInt<1>(0h1))
when _T_1258 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1259 = and(io.in.a.ready, io.in.a.valid)
node _T_1260 = and(_T_1259, a_first_1)
node _T_1261 = and(_T_1260, UInt<1>(0h1))
when _T_1261 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1262 = dshr(inflight, io.in.a.bits.source)
node _T_1263 = bits(_T_1262, 0, 0)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<5>
connect d_clr, UInt<5>(0h0)
wire d_clr_wo_ready : UInt<5>
connect d_clr_wo_ready, UInt<5>(0h0)
wire d_opcodes_clr : UInt<20>
connect d_opcodes_clr, UInt<20>(0h0)
wire d_sizes_clr : UInt<20>
connect d_sizes_clr, UInt<20>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1268 = and(io.in.d.valid, d_first_1)
node _T_1269 = and(_T_1268, UInt<1>(0h1))
node _T_1270 = eq(d_release_ack, UInt<1>(0h0))
node _T_1271 = and(_T_1269, _T_1270)
when _T_1271 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1272 = and(io.in.d.ready, io.in.d.valid)
node _T_1273 = and(_T_1272, d_first_1)
node _T_1274 = and(_T_1273, UInt<1>(0h1))
node _T_1275 = eq(d_release_ack, UInt<1>(0h0))
node _T_1276 = and(_T_1274, _T_1275)
when _T_1276 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1277 = and(io.in.d.valid, d_first_1)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = eq(d_release_ack, UInt<1>(0h0))
node _T_1280 = and(_T_1278, _T_1279)
when _T_1280 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1281 = dshr(inflight, io.in.d.bits.source)
node _T_1282 = bits(_T_1281, 0, 0)
node _T_1283 = or(_T_1282, same_cycle_resp)
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194
node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195
else :
node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1299 = or(_T_1297, _T_1298)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196
node _T_1303 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197
node _T_1307 = and(io.in.d.valid, d_first_1)
node _T_1308 = and(_T_1307, a_first_1)
node _T_1309 = and(_T_1308, io.in.a.valid)
node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = eq(d_release_ack, UInt<1>(0h0))
node _T_1313 = and(_T_1311, _T_1312)
when _T_1313 :
node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1315 = or(_T_1314, io.in.a.ready)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198
node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1320 = orr(a_set_wo_ready)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
node _T_1322 = or(_T_1319, _T_1321)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_183
node _T_1326 = orr(inflight)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1329 = or(_T_1327, _T_1328)
node _T_1330 = lt(watchdog, plusarg_reader.out)
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1335 = and(io.in.a.ready, io.in.a.valid)
node _T_1336 = and(io.in.d.ready, io.in.d.valid)
node _T_1337 = or(_T_1335, _T_1336)
when _T_1337 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0)
regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_sizes_1 : UInt<20>, clock, reset, UInt<20>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<5>
connect c_set, UInt<5>(0h0)
wire c_set_wo_ready : UInt<5>
connect c_set_wo_ready, UInt<5>(0h0)
wire c_opcodes_set : UInt<20>
connect c_opcodes_set, UInt<20>(0h0)
wire c_sizes_set : UInt<20>
connect c_sizes_set, UInt<20>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_1338 = and(io.in.c.valid, c_first_1)
node _T_1339 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1340 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1341 = and(_T_1339, _T_1340)
node _T_1342 = and(_T_1338, _T_1341)
when _T_1342 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_1343 = and(io.in.c.ready, io.in.c.valid)
node _T_1344 = and(_T_1343, c_first_1)
node _T_1345 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1346 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1347 = and(_T_1345, _T_1346)
node _T_1348 = and(_T_1344, _T_1347)
when _T_1348 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_1349 = dshr(inflight_1, io.in.c.bits.source)
node _T_1350 = bits(_T_1349, 0, 0)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<5>
connect d_clr_1, UInt<5>(0h0)
wire d_clr_wo_ready_1 : UInt<5>
connect d_clr_wo_ready_1, UInt<5>(0h0)
wire d_opcodes_clr_1 : UInt<20>
connect d_opcodes_clr_1, UInt<20>(0h0)
wire d_sizes_clr_1 : UInt<20>
connect d_sizes_clr_1, UInt<20>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1355 = and(io.in.d.valid, d_first_2)
node _T_1356 = and(_T_1355, UInt<1>(0h1))
node _T_1357 = and(_T_1356, d_release_ack_1)
when _T_1357 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1358 = and(io.in.d.ready, io.in.d.valid)
node _T_1359 = and(_T_1358, d_first_2)
node _T_1360 = and(_T_1359, UInt<1>(0h1))
node _T_1361 = and(_T_1360, d_release_ack_1)
when _T_1361 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1362 = and(io.in.d.valid, d_first_2)
node _T_1363 = and(_T_1362, UInt<1>(0h1))
node _T_1364 = and(_T_1363, d_release_ack_1)
when _T_1364 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1365 = dshr(inflight_1, io.in.d.bits.source)
node _T_1366 = bits(_T_1365, 0, 0)
node _T_1367 = or(_T_1366, same_cycle_resp_1)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203
else :
node _T_1375 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204
node _T_1379 = and(io.in.d.valid, d_first_2)
node _T_1380 = and(_T_1379, c_first_1)
node _T_1381 = and(_T_1380, io.in.c.valid)
node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_1383 = and(_T_1381, _T_1382)
node _T_1384 = and(_T_1383, d_release_ack_1)
node _T_1385 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1386 = and(_T_1384, _T_1385)
when _T_1386 :
node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1388 = or(_T_1387, io.in.c.ready)
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205
node _T_1392 = orr(c_set_wo_ready)
when _T_1392 :
node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_184
node _T_1397 = orr(inflight_1)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1400 = or(_T_1398, _T_1399)
node _T_1401 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_1406 = and(io.in.c.ready, io.in.c.valid)
node _T_1407 = and(io.in.d.ready, io.in.d.valid)
node _T_1408 = or(_T_1406, _T_1407)
when _T_1408 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = and(_T_1409, d_first_3)
node _T_1411 = bits(io.in.d.bits.opcode, 2, 2)
node _T_1412 = bits(io.in.d.bits.opcode, 1, 1)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
node _T_1414 = and(_T_1411, _T_1413)
node _T_1415 = and(_T_1410, _T_1414)
when _T_1415 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_1416 = dshr(inflight_2, io.in.d.bits.sink)
node _T_1417 = bits(_T_1416, 0, 0)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_1422 = and(io.in.e.ready, io.in.e.valid)
node _T_1423 = and(_T_1422, UInt<1>(0h1))
node _T_1424 = and(_T_1423, UInt<1>(0h1))
when _T_1424 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_1425 = or(d_set, inflight_2)
node _T_1426 = dshr(_T_1425, io.in.e.bits.sink)
node _T_1427 = bits(_T_1426, 0, 0)
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_185 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_186 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_60( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [2:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [2:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [2:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [4:0] inflight; // @[Monitor.scala:614:27]
reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [19:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [4:0] inflight_1; // @[Monitor.scala:726:35]
reg [19:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_67 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5))
node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4)
node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4)
node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit)
node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2)
node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T)
node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit)
node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2)
node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1)
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2)
node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2)
node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2)
node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2)
node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2)
node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2)
node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit)
node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2)
node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8)
node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit)
node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2)
node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9)
node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit)
node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2)
node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10)
node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit)
node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2)
node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11)
node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit)
node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2)
node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12)
node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit)
node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2)
node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13)
node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit)
node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2)
node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14)
node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit)
node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2)
node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_eq_16 = and(mask_sub_8_2, mask_nbit)
node _mask_acc_T_16 = and(mask_size, mask_eq_16)
node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_8_2, mask_bit)
node _mask_acc_T_17 = and(mask_size, mask_eq_17)
node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_9_2, mask_nbit)
node _mask_acc_T_18 = and(mask_size, mask_eq_18)
node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_9_2, mask_bit)
node _mask_acc_T_19 = and(mask_size, mask_eq_19)
node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_10_2, mask_nbit)
node _mask_acc_T_20 = and(mask_size, mask_eq_20)
node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_10_2, mask_bit)
node _mask_acc_T_21 = and(mask_size, mask_eq_21)
node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_11_2, mask_nbit)
node _mask_acc_T_22 = and(mask_size, mask_eq_22)
node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_11_2, mask_bit)
node _mask_acc_T_23 = and(mask_size, mask_eq_23)
node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_12_2, mask_nbit)
node _mask_acc_T_24 = and(mask_size, mask_eq_24)
node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_12_2, mask_bit)
node _mask_acc_T_25 = and(mask_size, mask_eq_25)
node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_13_2, mask_nbit)
node _mask_acc_T_26 = and(mask_size, mask_eq_26)
node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_13_2, mask_bit)
node _mask_acc_T_27 = and(mask_size, mask_eq_27)
node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_14_2, mask_nbit)
node _mask_acc_T_28 = and(mask_size, mask_eq_28)
node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_14_2, mask_bit)
node _mask_acc_T_29 = and(mask_size, mask_eq_29)
node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_15_2, mask_nbit)
node _mask_acc_T_30 = and(mask_size, mask_eq_30)
node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_15_2, mask_bit)
node _mask_acc_T_31 = and(mask_size, mask_eq_31)
node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31)
node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo)
node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo)
node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16)
node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18)
node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo)
node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20)
node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22)
node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24)
node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26)
node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo)
node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_24 = shr(io.in.a.bits.source, 2)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_69 = cvt(_T_68)
node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000)))
node _T_71 = asSInt(_T_70)
node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0)))
node _T_73 = or(_T_37, _T_42)
node _T_74 = or(_T_73, _T_47)
node _T_75 = or(_T_74, _T_52)
node _T_76 = or(_T_75, _T_57)
node _T_77 = or(_T_76, _T_62)
node _T_78 = or(_T_77, _T_67)
node _T_79 = or(_T_78, _T_72)
node _T_80 = and(_T_32, _T_79)
node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_82 = or(UInt<1>(0h0), _T_81)
node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_84 = cvt(_T_83)
node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000)))
node _T_86 = asSInt(_T_85)
node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0)))
node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_89 = cvt(_T_88)
node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000)))
node _T_91 = asSInt(_T_90)
node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = or(_T_87, _T_92)
node _T_94 = and(_T_82, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_80)
node _T_96 = or(_T_95, _T_94)
node _T_97 = and(_T_31, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_97, UInt<1>(0h1), "") : assert_2
node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_103 = and(_T_101, _T_102)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_151 = cvt(_T_150)
node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000)))
node _T_153 = asSInt(_T_152)
node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0)))
node _T_155 = or(_T_109, _T_114)
node _T_156 = or(_T_155, _T_119)
node _T_157 = or(_T_156, _T_124)
node _T_158 = or(_T_157, _T_129)
node _T_159 = or(_T_158, _T_134)
node _T_160 = or(_T_159, _T_139)
node _T_161 = or(_T_160, _T_144)
node _T_162 = or(_T_161, _T_149)
node _T_163 = or(_T_162, _T_154)
node _T_164 = and(_T_104, _T_163)
node _T_165 = or(UInt<1>(0h0), _T_164)
node _T_166 = and(UInt<1>(0h0), _T_165)
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(_T_166, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_166, UInt<1>(0h1), "") : assert_3
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5))
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_173, UInt<1>(0h1), "") : assert_5
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(is_aligned, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_180, UInt<1>(0h1), "") : assert_7
node _T_184 = not(io.in.a.bits.mask)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_185, UInt<1>(0h1), "") : assert_8
node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_189, UInt<1>(0h1), "") : assert_9
node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_193 :
node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_197 = shr(io.in.a.bits.source, 2)
node _T_198 = eq(_T_197, UInt<1>(0h0))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_202 = and(_T_200, _T_201)
node _T_203 = and(_T_196, _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = or(_T_210, _T_215)
node _T_247 = or(_T_246, _T_220)
node _T_248 = or(_T_247, _T_225)
node _T_249 = or(_T_248, _T_230)
node _T_250 = or(_T_249, _T_235)
node _T_251 = or(_T_250, _T_240)
node _T_252 = or(_T_251, _T_245)
node _T_253 = and(_T_205, _T_252)
node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_255 = or(UInt<1>(0h0), _T_254)
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_260, _T_265)
node _T_267 = and(_T_255, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_253)
node _T_269 = or(_T_268, _T_267)
node _T_270 = and(_T_204, _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_270, UInt<1>(0h1), "") : assert_10
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = or(_T_282, _T_287)
node _T_329 = or(_T_328, _T_292)
node _T_330 = or(_T_329, _T_297)
node _T_331 = or(_T_330, _T_302)
node _T_332 = or(_T_331, _T_307)
node _T_333 = or(_T_332, _T_312)
node _T_334 = or(_T_333, _T_317)
node _T_335 = or(_T_334, _T_322)
node _T_336 = or(_T_335, _T_327)
node _T_337 = and(_T_277, _T_336)
node _T_338 = or(UInt<1>(0h0), _T_337)
node _T_339 = and(UInt<1>(0h0), _T_338)
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_339, UInt<1>(0h1), "") : assert_11
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_346, UInt<1>(0h1), "") : assert_13
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(is_aligned, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(_T_353, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_353, UInt<1>(0h1), "") : assert_15
node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_357, UInt<1>(0h1), "") : assert_16
node _T_361 = not(io.in.a.bits.mask)
node _T_362 = eq(_T_361, UInt<1>(0h0))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_362, UInt<1>(0h1), "") : assert_17
node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_366, UInt<1>(0h1), "") : assert_18
node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_370 :
node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_373 = and(_T_371, _T_372)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_374 = shr(io.in.a.bits.source, 2)
node _T_375 = eq(_T_374, UInt<1>(0h0))
node _T_376 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_377 = and(_T_375, _T_376)
node _T_378 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_379 = and(_T_377, _T_378)
node _T_380 = and(_T_373, _T_379)
node _T_381 = or(UInt<1>(0h0), _T_380)
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_381, UInt<1>(0h1), "") : assert_19
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = and(_T_388, _T_393)
node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_397 = and(_T_395, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = or(_T_403, _T_408)
node _T_445 = or(_T_444, _T_413)
node _T_446 = or(_T_445, _T_418)
node _T_447 = or(_T_446, _T_423)
node _T_448 = or(_T_447, _T_428)
node _T_449 = or(_T_448, _T_433)
node _T_450 = or(_T_449, _T_438)
node _T_451 = or(_T_450, _T_443)
node _T_452 = and(_T_398, _T_451)
node _T_453 = or(UInt<1>(0h0), _T_394)
node _T_454 = or(_T_453, _T_452)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_454, UInt<1>(0h1), "") : assert_20
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(is_aligned, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_464, UInt<1>(0h1), "") : assert_23
node _T_468 = eq(io.in.a.bits.mask, mask)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_468, UInt<1>(0h1), "") : assert_24
node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_472, UInt<1>(0h1), "") : assert_25
node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_476 :
node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_480 = shr(io.in.a.bits.source, 2)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_485 = and(_T_483, _T_484)
node _T_486 = and(_T_479, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_490 = and(_T_488, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = and(_T_491, _T_496)
node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_500 = and(_T_498, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_523 = cvt(_T_522)
node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000)))
node _T_525 = asSInt(_T_524)
node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0)))
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = or(_T_506, _T_511)
node _T_543 = or(_T_542, _T_516)
node _T_544 = or(_T_543, _T_521)
node _T_545 = or(_T_544, _T_526)
node _T_546 = or(_T_545, _T_531)
node _T_547 = or(_T_546, _T_536)
node _T_548 = or(_T_547, _T_541)
node _T_549 = and(_T_501, _T_548)
node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_497)
node _T_558 = or(_T_557, _T_549)
node _T_559 = or(_T_558, _T_556)
node _T_560 = and(_T_487, _T_559)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_560, UInt<1>(0h1), "") : assert_26
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(is_aligned, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_570, UInt<1>(0h1), "") : assert_29
node _T_574 = eq(io.in.a.bits.mask, mask)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_574, UInt<1>(0h1), "") : assert_30
node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_578 :
node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<1>(0h0))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _T_588 = and(_T_581, _T_587)
node _T_589 = or(UInt<1>(0h0), _T_588)
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = and(_T_593, _T_598)
node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_602 = and(_T_600, _T_601)
node _T_603 = or(UInt<1>(0h0), _T_602)
node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = or(_T_608, _T_613)
node _T_645 = or(_T_644, _T_618)
node _T_646 = or(_T_645, _T_623)
node _T_647 = or(_T_646, _T_628)
node _T_648 = or(_T_647, _T_633)
node _T_649 = or(_T_648, _T_638)
node _T_650 = or(_T_649, _T_643)
node _T_651 = and(_T_603, _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_599)
node _T_660 = or(_T_659, _T_651)
node _T_661 = or(_T_660, _T_658)
node _T_662 = and(_T_589, _T_661)
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(_T_662, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_662, UInt<1>(0h1), "") : assert_31
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(is_aligned, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_672, UInt<1>(0h1), "") : assert_34
node _T_676 = not(mask)
node _T_677 = and(io.in.a.bits.mask, _T_676)
node _T_678 = eq(_T_677, UInt<1>(0h0))
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_678, UInt<1>(0h1), "") : assert_35
node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_686 = shr(io.in.a.bits.source, 2)
node _T_687 = eq(_T_686, UInt<1>(0h0))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_691 = and(_T_689, _T_690)
node _T_692 = and(_T_685, _T_691)
node _T_693 = or(UInt<1>(0h0), _T_692)
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_696 = and(_T_694, _T_695)
node _T_697 = or(UInt<1>(0h0), _T_696)
node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = or(_T_702, _T_707)
node _T_744 = or(_T_743, _T_712)
node _T_745 = or(_T_744, _T_717)
node _T_746 = or(_T_745, _T_722)
node _T_747 = or(_T_746, _T_727)
node _T_748 = or(_T_747, _T_732)
node _T_749 = or(_T_748, _T_737)
node _T_750 = or(_T_749, _T_742)
node _T_751 = and(_T_697, _T_750)
node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = and(_T_752, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_751)
node _T_760 = or(_T_759, _T_758)
node _T_761 = and(_T_693, _T_760)
node _T_762 = asUInt(reset)
node _T_763 = eq(_T_762, UInt<1>(0h0))
when _T_763 :
node _T_764 = eq(_T_761, UInt<1>(0h0))
when _T_764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_761, UInt<1>(0h1), "") : assert_36
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(is_aligned, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_771, UInt<1>(0h1), "") : assert_39
node _T_775 = eq(io.in.a.bits.mask, mask)
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_775, UInt<1>(0h1), "") : assert_40
node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_779 :
node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_782 = and(_T_780, _T_781)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_783 = shr(io.in.a.bits.source, 2)
node _T_784 = eq(_T_783, UInt<1>(0h0))
node _T_785 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_786 = and(_T_784, _T_785)
node _T_787 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_788 = and(_T_786, _T_787)
node _T_789 = and(_T_782, _T_788)
node _T_790 = or(UInt<1>(0h0), _T_789)
node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_793 = and(_T_791, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_836 = cvt(_T_835)
node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000)))
node _T_838 = asSInt(_T_837)
node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0)))
node _T_840 = or(_T_799, _T_804)
node _T_841 = or(_T_840, _T_809)
node _T_842 = or(_T_841, _T_814)
node _T_843 = or(_T_842, _T_819)
node _T_844 = or(_T_843, _T_824)
node _T_845 = or(_T_844, _T_829)
node _T_846 = or(_T_845, _T_834)
node _T_847 = or(_T_846, _T_839)
node _T_848 = and(_T_794, _T_847)
node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_851 = cvt(_T_850)
node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000)))
node _T_853 = asSInt(_T_852)
node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0)))
node _T_855 = and(_T_849, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_848)
node _T_857 = or(_T_856, _T_855)
node _T_858 = and(_T_790, _T_857)
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_858, UInt<1>(0h1), "") : assert_41
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(is_aligned, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_868, UInt<1>(0h1), "") : assert_44
node _T_872 = eq(io.in.a.bits.mask, mask)
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_872, UInt<1>(0h1), "") : assert_45
node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_876 :
node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_880 = shr(io.in.a.bits.source, 2)
node _T_881 = eq(_T_880, UInt<1>(0h0))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_885 = and(_T_883, _T_884)
node _T_886 = and(_T_879, _T_885)
node _T_887 = or(UInt<1>(0h0), _T_886)
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = and(_T_891, _T_896)
node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = or(_T_903, _T_908)
node _T_935 = or(_T_934, _T_913)
node _T_936 = or(_T_935, _T_918)
node _T_937 = or(_T_936, _T_923)
node _T_938 = or(_T_937, _T_928)
node _T_939 = or(_T_938, _T_933)
node _T_940 = and(_T_898, _T_939)
node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_943 = and(_T_941, _T_942)
node _T_944 = or(UInt<1>(0h0), _T_943)
node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_951 = cvt(_T_950)
node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000)))
node _T_953 = asSInt(_T_952)
node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0)))
node _T_955 = or(_T_949, _T_954)
node _T_956 = and(_T_944, _T_955)
node _T_957 = or(UInt<1>(0h0), _T_897)
node _T_958 = or(_T_957, _T_940)
node _T_959 = or(_T_958, _T_956)
node _T_960 = and(_T_887, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_960, UInt<1>(0h1), "") : assert_46
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(is_aligned, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_970, UInt<1>(0h1), "") : assert_49
node _T_974 = eq(io.in.a.bits.mask, mask)
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_974, UInt<1>(0h1), "") : assert_50
node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_978, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_982, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_986 :
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_990, UInt<1>(0h1), "") : assert_54
node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_994, UInt<1>(0h1), "") : assert_55
node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_998, UInt<1>(0h1), "") : assert_56
node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57
node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1006 :
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(sink_ok, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60
node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61
node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62
node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63
node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1030 = or(UInt<1>(0h1), _T_1029)
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64
node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1034 :
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(sink_ok, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67
node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68
node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71
node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75
node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1080 :
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77
node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1089 = or(_T_1088, io.in.d.bits.corrupt)
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_T_1089, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78
node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1094 = or(UInt<1>(0h1), _T_1093)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79
node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1098 :
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81
node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82
node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1111 = or(UInt<1>(0h1), _T_1110)
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<256>(0h0)
connect _WIRE.bits.mask, UInt<32>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<2>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<256>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<2>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1127 = eq(a_first, UInt<1>(0h0))
node _T_1128 = and(io.in.a.valid, _T_1127)
when _T_1128 :
node _T_1129 = eq(io.in.a.bits.opcode, opcode)
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87
node _T_1133 = eq(io.in.a.bits.param, param)
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88
node _T_1137 = eq(io.in.a.bits.size, size)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89
node _T_1141 = eq(io.in.a.bits.source, source)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90
node _T_1145 = eq(io.in.a.bits.address, address)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91
node _T_1149 = and(io.in.a.ready, io.in.a.valid)
node _T_1150 = and(_T_1149, a_first)
when _T_1150 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1151 = eq(d_first, UInt<1>(0h0))
node _T_1152 = and(io.in.d.valid, _T_1151)
when _T_1152 :
node _T_1153 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92
node _T_1157 = eq(io.in.d.bits.param, param_1)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93
node _T_1161 = eq(io.in.d.bits.size, size_1)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94
node _T_1165 = eq(io.in.d.bits.source, source_1)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95
node _T_1169 = eq(io.in.d.bits.sink, sink)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96
node _T_1173 = eq(io.in.d.bits.denied, denied)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97
node _T_1177 = and(io.in.d.ready, io.in.d.valid)
node _T_1178 = and(_T_1177, d_first)
when _T_1178 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<4>
connect a_set, UInt<4>(0h0)
wire a_set_wo_ready : UInt<4>
connect a_set_wo_ready, UInt<4>(0h0)
wire a_opcodes_set : UInt<16>
connect a_opcodes_set, UInt<16>(0h0)
wire a_sizes_set : UInt<32>
connect a_sizes_set, UInt<32>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1179 = and(io.in.a.valid, a_first_1)
node _T_1180 = and(_T_1179, UInt<1>(0h1))
when _T_1180 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1181 = and(io.in.a.ready, io.in.a.valid)
node _T_1182 = and(_T_1181, a_first_1)
node _T_1183 = and(_T_1182, UInt<1>(0h1))
when _T_1183 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1184 = dshr(inflight, io.in.a.bits.source)
node _T_1185 = bits(_T_1184, 0, 0)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<4>
connect d_clr, UInt<4>(0h0)
wire d_clr_wo_ready : UInt<4>
connect d_clr_wo_ready, UInt<4>(0h0)
wire d_opcodes_clr : UInt<16>
connect d_opcodes_clr, UInt<16>(0h0)
wire d_sizes_clr : UInt<32>
connect d_sizes_clr, UInt<32>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1190 = and(io.in.d.valid, d_first_1)
node _T_1191 = and(_T_1190, UInt<1>(0h1))
node _T_1192 = eq(d_release_ack, UInt<1>(0h0))
node _T_1193 = and(_T_1191, _T_1192)
when _T_1193 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1194 = and(io.in.d.ready, io.in.d.valid)
node _T_1195 = and(_T_1194, d_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
node _T_1197 = eq(d_release_ack, UInt<1>(0h0))
node _T_1198 = and(_T_1196, _T_1197)
when _T_1198 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1199 = and(io.in.d.valid, d_first_1)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = eq(d_release_ack, UInt<1>(0h0))
node _T_1202 = and(_T_1200, _T_1201)
when _T_1202 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1203 = dshr(inflight, io.in.d.bits.source)
node _T_1204 = bits(_T_1203, 0, 0)
node _T_1205 = or(_T_1204, same_cycle_resp)
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1211 = or(_T_1209, _T_1210)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100
node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101
else :
node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1221 = or(_T_1219, _T_1220)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102
node _T_1225 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103
node _T_1229 = and(io.in.d.valid, d_first_1)
node _T_1230 = and(_T_1229, a_first_1)
node _T_1231 = and(_T_1230, io.in.a.valid)
node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1233 = and(_T_1231, _T_1232)
node _T_1234 = eq(d_release_ack, UInt<1>(0h0))
node _T_1235 = and(_T_1233, _T_1234)
when _T_1235 :
node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1237 = or(_T_1236, io.in.a.ready)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104
node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1242 = orr(a_set_wo_ready)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
node _T_1244 = or(_T_1241, _T_1243)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_134
node _T_1248 = orr(inflight)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1251 = or(_T_1249, _T_1250)
node _T_1252 = lt(watchdog, plusarg_reader.out)
node _T_1253 = or(_T_1251, _T_1252)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1257 = and(io.in.a.ready, io.in.a.valid)
node _T_1258 = and(io.in.d.ready, io.in.d.valid)
node _T_1259 = or(_T_1257, _T_1258)
when _T_1259 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<256>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<2>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<256>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<4>
connect c_set, UInt<4>(0h0)
wire c_set_wo_ready : UInt<4>
connect c_set_wo_ready, UInt<4>(0h0)
wire c_opcodes_set : UInt<16>
connect c_opcodes_set, UInt<16>(0h0)
wire c_sizes_set : UInt<32>
connect c_sizes_set, UInt<32>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<256>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<2>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1260 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<256>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<2>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = and(_T_1260, _T_1263)
when _T_1264 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<256>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<2>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1266 = and(_T_1265, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<256>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<2>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1269 = and(_T_1267, _T_1268)
node _T_1270 = and(_T_1266, _T_1269)
when _T_1270 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<256>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<2>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<256>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<2>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1272 = bits(_T_1271, 0, 0)
node _T_1273 = eq(_T_1272, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<4>
connect d_clr_1, UInt<4>(0h0)
wire d_clr_wo_ready_1 : UInt<4>
connect d_clr_wo_ready_1, UInt<4>(0h0)
wire d_opcodes_clr_1 : UInt<16>
connect d_opcodes_clr_1, UInt<16>(0h0)
wire d_sizes_clr_1 : UInt<32>
connect d_sizes_clr_1, UInt<32>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1277 = and(io.in.d.valid, d_first_2)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = and(_T_1278, d_release_ack_1)
when _T_1279 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1280 = and(io.in.d.ready, io.in.d.valid)
node _T_1281 = and(_T_1280, d_first_2)
node _T_1282 = and(_T_1281, UInt<1>(0h1))
node _T_1283 = and(_T_1282, d_release_ack_1)
when _T_1283 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1284 = and(io.in.d.valid, d_first_2)
node _T_1285 = and(_T_1284, UInt<1>(0h1))
node _T_1286 = and(_T_1285, d_release_ack_1)
when _T_1286 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1287 = dshr(inflight_1, io.in.d.bits.source)
node _T_1288 = bits(_T_1287, 0, 0)
node _T_1289 = or(_T_1288, same_cycle_resp_1)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<256>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<2>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109
else :
node _T_1297 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110
node _T_1301 = and(io.in.d.valid, d_first_2)
node _T_1302 = and(_T_1301, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<256>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<2>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1303 = and(_T_1302, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<256>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<2>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = and(_T_1305, d_release_ack_1)
node _T_1307 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1308 = and(_T_1306, _T_1307)
when _T_1308 :
node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<256>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<2>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1310 = or(_T_1309, _WIRE_23.ready)
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111
node _T_1314 = orr(c_set_wo_ready)
when _T_1314 :
node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_135
node _T_1319 = orr(inflight_1)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1322 = or(_T_1320, _T_1321)
node _T_1323 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1324 = or(_T_1322, _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:68:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<256>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<2>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1329 = and(io.in.d.ready, io.in.d.valid)
node _T_1330 = or(_T_1328, _T_1329)
when _T_1330 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_67( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59]
wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14]
wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27]
wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25]
wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28]
wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28]
wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34]
wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79]
wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77]
wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35]
wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49]
wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [6:0] a_first_counter; // @[Edges.scala:229:27]
wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [1:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [1:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [3:0] inflight; // @[Monitor.scala:614:27]
reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [31:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [6:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46]
wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] a_set; // @[Monitor.scala:626:34]
wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [31:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [3:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [3:0] d_clr; // @[Monitor.scala:664:34]
wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [3:0] inflight_1; // @[Monitor.scala:726:35]
wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46]
wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] d_clr_1; // @[Monitor.scala:774:34]
wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113]
wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_1 :
input clock : Clock
input reset : Reset
output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : { bits : UInt<32>}, clock
when io.en :
connect reg.bits, _reg_T_1.bits
connect io.outU, reg
connect io.outL, reg | module PE_1( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [31:0] io_inR_bits, // @[Transposer.scala:101:16]
input [31:0] io_inD_bits, // @[Transposer.scala:101:16]
output [31:0] io_outL_bits, // @[Transposer.scala:101:16]
output [31:0] io_outU_bits, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9]
wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9]
wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [31:0] reg_bits; // @[Transposer.scala:110:24]
assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24]
assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9]
assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_32 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_32( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61]
wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35]
wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17]
assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_11 :
input clock : Clock
input reset : Reset
output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1]}, credit_alloc : { `3` : { alloc : UInt<1>, tail : UInt<1>}[1], `2` : { alloc : UInt<1>, tail : UInt<1>}[3], `1` : { alloc : UInt<1>, tail : UInt<1>}[3], `0` : { alloc : UInt<1>, tail : UInt<1>}[3]}, switch_sel : { `3` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}}
inst arbs_0 of SwitchArbiter_90
connect arbs_0.clock, clock
connect arbs_0.reset, reset
inst arbs_1 of SwitchArbiter_91
connect arbs_1.clock, clock
connect arbs_1.reset, reset
inst arbs_2 of SwitchArbiter_92
connect arbs_2.clock, clock
connect arbs_2.reset, reset
inst arbs_3 of SwitchArbiter_93
connect arbs_3.clock, clock
connect arbs_3.reset, reset
connect arbs_0.io.out[0].ready, UInt<1>(0h1)
connect arbs_1.io.out[0].ready, UInt<1>(0h1)
connect arbs_2.io.out[0].ready, UInt<1>(0h1)
connect arbs_3.io.out[0].ready, UInt<1>(0h1)
wire fires : UInt<1>[4]
node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_0_valid_T_2 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_1)
connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_2
connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[0].bits.vc_sel.`1`[1], io.req.`0`[0].bits.vc_sel.`1`[1]
connect arbs_0.io.in[0].bits.vc_sel.`1`[2], io.req.`0`[0].bits.vc_sel.`1`[2]
connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
connect arbs_0.io.in[0].bits.vc_sel.`2`[1], io.req.`0`[0].bits.vc_sel.`2`[1]
connect arbs_0.io.in[0].bits.vc_sel.`2`[2], io.req.`0`[0].bits.vc_sel.`2`[2]
connect arbs_0.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0]
node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid)
connect fires[0], _fires_0_T
node _arbs_1_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[1])
node _arbs_1_io_in_0_valid_T_1 = or(_arbs_1_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`1`[2])
node _arbs_1_io_in_0_valid_T_2 = and(io.req.`0`[0].valid, _arbs_1_io_in_0_valid_T_1)
connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T_2
connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[0].bits.vc_sel.`1`[1], io.req.`0`[0].bits.vc_sel.`1`[1]
connect arbs_1.io.in[0].bits.vc_sel.`1`[2], io.req.`0`[0].bits.vc_sel.`1`[2]
connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
connect arbs_1.io.in[0].bits.vc_sel.`2`[1], io.req.`0`[0].bits.vc_sel.`2`[1]
connect arbs_1.io.in[0].bits.vc_sel.`2`[2], io.req.`0`[0].bits.vc_sel.`2`[2]
connect arbs_1.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0]
node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid)
connect fires[1], _fires_1_T
node _arbs_2_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[1])
node _arbs_2_io_in_0_valid_T_1 = or(_arbs_2_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`2`[2])
node _arbs_2_io_in_0_valid_T_2 = and(io.req.`0`[0].valid, _arbs_2_io_in_0_valid_T_1)
connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T_2
connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[0].bits.vc_sel.`1`[1], io.req.`0`[0].bits.vc_sel.`1`[1]
connect arbs_2.io.in[0].bits.vc_sel.`1`[2], io.req.`0`[0].bits.vc_sel.`1`[2]
connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
connect arbs_2.io.in[0].bits.vc_sel.`2`[1], io.req.`0`[0].bits.vc_sel.`2`[1]
connect arbs_2.io.in[0].bits.vc_sel.`2`[2], io.req.`0`[0].bits.vc_sel.`2`[2]
connect arbs_2.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0]
node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid)
connect fires[2], _fires_2_T
node _arbs_3_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`3`[0])
connect arbs_3.io.in[0].valid, _arbs_3_io_in_0_valid_T
connect arbs_3.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_3.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_3.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_3.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_3.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_3.io.in[0].bits.vc_sel.`1`[1], io.req.`0`[0].bits.vc_sel.`1`[1]
connect arbs_3.io.in[0].bits.vc_sel.`1`[2], io.req.`0`[0].bits.vc_sel.`1`[2]
connect arbs_3.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
connect arbs_3.io.in[0].bits.vc_sel.`2`[1], io.req.`0`[0].bits.vc_sel.`2`[1]
connect arbs_3.io.in[0].bits.vc_sel.`2`[2], io.req.`0`[0].bits.vc_sel.`2`[2]
connect arbs_3.io.in[0].bits.vc_sel.`3`[0], io.req.`0`[0].bits.vc_sel.`3`[0]
node _fires_3_T = and(arbs_3.io.in[0].ready, arbs_3.io.in[0].valid)
connect fires[3], _fires_3_T
node _io_req_0_0_ready_T = or(fires[0], fires[1])
node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2])
node _io_req_0_0_ready_T_2 = or(_io_req_0_0_ready_T_1, fires[3])
connect io.req.`0`[0].ready, _io_req_0_0_ready_T_2
wire fires_1 : UInt<1>[4]
node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_1_valid_T_2 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_1)
connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_2
connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[1].bits.vc_sel.`1`[1], io.req.`1`[0].bits.vc_sel.`1`[1]
connect arbs_0.io.in[1].bits.vc_sel.`1`[2], io.req.`1`[0].bits.vc_sel.`1`[2]
connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
connect arbs_0.io.in[1].bits.vc_sel.`2`[1], io.req.`1`[0].bits.vc_sel.`2`[1]
connect arbs_0.io.in[1].bits.vc_sel.`2`[2], io.req.`1`[0].bits.vc_sel.`2`[2]
connect arbs_0.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0]
node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid)
connect fires_1[0], _fires_0_T_1
node _arbs_1_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[1])
node _arbs_1_io_in_1_valid_T_1 = or(_arbs_1_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`1`[2])
node _arbs_1_io_in_1_valid_T_2 = and(io.req.`1`[0].valid, _arbs_1_io_in_1_valid_T_1)
connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T_2
connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[1].bits.vc_sel.`1`[1], io.req.`1`[0].bits.vc_sel.`1`[1]
connect arbs_1.io.in[1].bits.vc_sel.`1`[2], io.req.`1`[0].bits.vc_sel.`1`[2]
connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
connect arbs_1.io.in[1].bits.vc_sel.`2`[1], io.req.`1`[0].bits.vc_sel.`2`[1]
connect arbs_1.io.in[1].bits.vc_sel.`2`[2], io.req.`1`[0].bits.vc_sel.`2`[2]
connect arbs_1.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0]
node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid)
connect fires_1[1], _fires_1_T_1
node _arbs_2_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[1])
node _arbs_2_io_in_1_valid_T_1 = or(_arbs_2_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`2`[2])
node _arbs_2_io_in_1_valid_T_2 = and(io.req.`1`[0].valid, _arbs_2_io_in_1_valid_T_1)
connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T_2
connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[1].bits.vc_sel.`1`[1], io.req.`1`[0].bits.vc_sel.`1`[1]
connect arbs_2.io.in[1].bits.vc_sel.`1`[2], io.req.`1`[0].bits.vc_sel.`1`[2]
connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
connect arbs_2.io.in[1].bits.vc_sel.`2`[1], io.req.`1`[0].bits.vc_sel.`2`[1]
connect arbs_2.io.in[1].bits.vc_sel.`2`[2], io.req.`1`[0].bits.vc_sel.`2`[2]
connect arbs_2.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0]
node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid)
connect fires_1[2], _fires_2_T_1
node _arbs_3_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`3`[0])
connect arbs_3.io.in[1].valid, _arbs_3_io_in_1_valid_T
connect arbs_3.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_3.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_3.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_3.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_3.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_3.io.in[1].bits.vc_sel.`1`[1], io.req.`1`[0].bits.vc_sel.`1`[1]
connect arbs_3.io.in[1].bits.vc_sel.`1`[2], io.req.`1`[0].bits.vc_sel.`1`[2]
connect arbs_3.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
connect arbs_3.io.in[1].bits.vc_sel.`2`[1], io.req.`1`[0].bits.vc_sel.`2`[1]
connect arbs_3.io.in[1].bits.vc_sel.`2`[2], io.req.`1`[0].bits.vc_sel.`2`[2]
connect arbs_3.io.in[1].bits.vc_sel.`3`[0], io.req.`1`[0].bits.vc_sel.`3`[0]
node _fires_3_T_1 = and(arbs_3.io.in[1].ready, arbs_3.io.in[1].valid)
connect fires_1[3], _fires_3_T_1
node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1])
node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2])
node _io_req_1_0_ready_T_2 = or(_io_req_1_0_ready_T_1, fires_1[3])
connect io.req.`1`[0].ready, _io_req_1_0_ready_T_2
wire fires_2 : UInt<1>[4]
node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_2_valid_T_2 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_1)
connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_2
connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[2].bits.vc_sel.`1`[1], io.req.`2`[0].bits.vc_sel.`1`[1]
connect arbs_0.io.in[2].bits.vc_sel.`1`[2], io.req.`2`[0].bits.vc_sel.`1`[2]
connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
connect arbs_0.io.in[2].bits.vc_sel.`2`[1], io.req.`2`[0].bits.vc_sel.`2`[1]
connect arbs_0.io.in[2].bits.vc_sel.`2`[2], io.req.`2`[0].bits.vc_sel.`2`[2]
connect arbs_0.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0]
node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid)
connect fires_2[0], _fires_0_T_2
node _arbs_1_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[1])
node _arbs_1_io_in_2_valid_T_1 = or(_arbs_1_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`1`[2])
node _arbs_1_io_in_2_valid_T_2 = and(io.req.`2`[0].valid, _arbs_1_io_in_2_valid_T_1)
connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T_2
connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[2].bits.vc_sel.`1`[1], io.req.`2`[0].bits.vc_sel.`1`[1]
connect arbs_1.io.in[2].bits.vc_sel.`1`[2], io.req.`2`[0].bits.vc_sel.`1`[2]
connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
connect arbs_1.io.in[2].bits.vc_sel.`2`[1], io.req.`2`[0].bits.vc_sel.`2`[1]
connect arbs_1.io.in[2].bits.vc_sel.`2`[2], io.req.`2`[0].bits.vc_sel.`2`[2]
connect arbs_1.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0]
node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid)
connect fires_2[1], _fires_1_T_2
node _arbs_2_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[1])
node _arbs_2_io_in_2_valid_T_1 = or(_arbs_2_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`2`[2])
node _arbs_2_io_in_2_valid_T_2 = and(io.req.`2`[0].valid, _arbs_2_io_in_2_valid_T_1)
connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T_2
connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[2].bits.vc_sel.`1`[1], io.req.`2`[0].bits.vc_sel.`1`[1]
connect arbs_2.io.in[2].bits.vc_sel.`1`[2], io.req.`2`[0].bits.vc_sel.`1`[2]
connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
connect arbs_2.io.in[2].bits.vc_sel.`2`[1], io.req.`2`[0].bits.vc_sel.`2`[1]
connect arbs_2.io.in[2].bits.vc_sel.`2`[2], io.req.`2`[0].bits.vc_sel.`2`[2]
connect arbs_2.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0]
node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid)
connect fires_2[2], _fires_2_T_2
node _arbs_3_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`3`[0])
connect arbs_3.io.in[2].valid, _arbs_3_io_in_2_valid_T
connect arbs_3.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_3.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_3.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_3.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_3.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_3.io.in[2].bits.vc_sel.`1`[1], io.req.`2`[0].bits.vc_sel.`1`[1]
connect arbs_3.io.in[2].bits.vc_sel.`1`[2], io.req.`2`[0].bits.vc_sel.`1`[2]
connect arbs_3.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
connect arbs_3.io.in[2].bits.vc_sel.`2`[1], io.req.`2`[0].bits.vc_sel.`2`[1]
connect arbs_3.io.in[2].bits.vc_sel.`2`[2], io.req.`2`[0].bits.vc_sel.`2`[2]
connect arbs_3.io.in[2].bits.vc_sel.`3`[0], io.req.`2`[0].bits.vc_sel.`3`[0]
node _fires_3_T_2 = and(arbs_3.io.in[2].ready, arbs_3.io.in[2].valid)
connect fires_2[3], _fires_3_T_2
node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1])
node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2])
node _io_req_2_0_ready_T_2 = or(_io_req_2_0_ready_T_1, fires_2[3])
connect io.req.`2`[0].ready, _io_req_2_0_ready_T_2
wire fires_3 : UInt<1>[4]
node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_3_valid_T_1 = or(_arbs_0_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_3_valid_T_2 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T_1)
connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_2
connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail
connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[3].bits.vc_sel.`1`[1], io.req.`3`[0].bits.vc_sel.`1`[1]
connect arbs_0.io.in[3].bits.vc_sel.`1`[2], io.req.`3`[0].bits.vc_sel.`1`[2]
connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0]
connect arbs_0.io.in[3].bits.vc_sel.`2`[1], io.req.`3`[0].bits.vc_sel.`2`[1]
connect arbs_0.io.in[3].bits.vc_sel.`2`[2], io.req.`3`[0].bits.vc_sel.`2`[2]
connect arbs_0.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0]
node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid)
connect fires_3[0], _fires_0_T_3
node _arbs_1_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[1])
node _arbs_1_io_in_3_valid_T_1 = or(_arbs_1_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`1`[2])
node _arbs_1_io_in_3_valid_T_2 = and(io.req.`3`[0].valid, _arbs_1_io_in_3_valid_T_1)
connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T_2
connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail
connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[3].bits.vc_sel.`1`[1], io.req.`3`[0].bits.vc_sel.`1`[1]
connect arbs_1.io.in[3].bits.vc_sel.`1`[2], io.req.`3`[0].bits.vc_sel.`1`[2]
connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0]
connect arbs_1.io.in[3].bits.vc_sel.`2`[1], io.req.`3`[0].bits.vc_sel.`2`[1]
connect arbs_1.io.in[3].bits.vc_sel.`2`[2], io.req.`3`[0].bits.vc_sel.`2`[2]
connect arbs_1.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0]
node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid)
connect fires_3[1], _fires_1_T_3
node _arbs_2_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[1])
node _arbs_2_io_in_3_valid_T_1 = or(_arbs_2_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`2`[2])
node _arbs_2_io_in_3_valid_T_2 = and(io.req.`3`[0].valid, _arbs_2_io_in_3_valid_T_1)
connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T_2
connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail
connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[3].bits.vc_sel.`1`[1], io.req.`3`[0].bits.vc_sel.`1`[1]
connect arbs_2.io.in[3].bits.vc_sel.`1`[2], io.req.`3`[0].bits.vc_sel.`1`[2]
connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0]
connect arbs_2.io.in[3].bits.vc_sel.`2`[1], io.req.`3`[0].bits.vc_sel.`2`[1]
connect arbs_2.io.in[3].bits.vc_sel.`2`[2], io.req.`3`[0].bits.vc_sel.`2`[2]
connect arbs_2.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0]
node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid)
connect fires_3[2], _fires_2_T_3
node _arbs_3_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`3`[0])
connect arbs_3.io.in[3].valid, _arbs_3_io_in_3_valid_T
connect arbs_3.io.in[3].bits.tail, io.req.`3`[0].bits.tail
connect arbs_3.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0]
connect arbs_3.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1]
connect arbs_3.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2]
connect arbs_3.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0]
connect arbs_3.io.in[3].bits.vc_sel.`1`[1], io.req.`3`[0].bits.vc_sel.`1`[1]
connect arbs_3.io.in[3].bits.vc_sel.`1`[2], io.req.`3`[0].bits.vc_sel.`1`[2]
connect arbs_3.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0]
connect arbs_3.io.in[3].bits.vc_sel.`2`[1], io.req.`3`[0].bits.vc_sel.`2`[1]
connect arbs_3.io.in[3].bits.vc_sel.`2`[2], io.req.`3`[0].bits.vc_sel.`2`[2]
connect arbs_3.io.in[3].bits.vc_sel.`3`[0], io.req.`3`[0].bits.vc_sel.`3`[0]
node _fires_3_T_3 = and(arbs_3.io.in[3].ready, arbs_3.io.in[3].valid)
connect fires_3[3], _fires_3_T_3
node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1])
node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2])
node _io_req_3_0_ready_T_2 = or(_io_req_3_0_ready_T_1, fires_3[3])
connect io.req.`3`[0].ready, _io_req_3_0_ready_T_2
node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0)
node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T)
node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2
node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1)
node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T)
node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2
node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2)
node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T)
node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2
node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3)
node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T)
node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2
node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0)
node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T)
node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2
node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1)
node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T)
node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2
node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2)
node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T)
node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2
node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3)
node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T)
node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2
node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0)
node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T)
node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2
node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1)
node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T)
node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2
node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2)
node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T)
node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2
node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3)
node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T)
node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2
node _io_switch_sel_3_0_0_0_T = bits(arbs_3.io.chosen_oh[0], 0, 0)
node _io_switch_sel_3_0_0_0_T_1 = and(arbs_3.io.in[0].valid, _io_switch_sel_3_0_0_0_T)
node _io_switch_sel_3_0_0_0_T_2 = and(_io_switch_sel_3_0_0_0_T_1, arbs_3.io.out[0].valid)
connect io.switch_sel.`3`[0].`0`[0], _io_switch_sel_3_0_0_0_T_2
node _io_switch_sel_3_0_1_0_T = bits(arbs_3.io.chosen_oh[0], 1, 1)
node _io_switch_sel_3_0_1_0_T_1 = and(arbs_3.io.in[1].valid, _io_switch_sel_3_0_1_0_T)
node _io_switch_sel_3_0_1_0_T_2 = and(_io_switch_sel_3_0_1_0_T_1, arbs_3.io.out[0].valid)
connect io.switch_sel.`3`[0].`1`[0], _io_switch_sel_3_0_1_0_T_2
node _io_switch_sel_3_0_2_0_T = bits(arbs_3.io.chosen_oh[0], 2, 2)
node _io_switch_sel_3_0_2_0_T_1 = and(arbs_3.io.in[2].valid, _io_switch_sel_3_0_2_0_T)
node _io_switch_sel_3_0_2_0_T_2 = and(_io_switch_sel_3_0_2_0_T_1, arbs_3.io.out[0].valid)
connect io.switch_sel.`3`[0].`2`[0], _io_switch_sel_3_0_2_0_T_2
node _io_switch_sel_3_0_3_0_T = bits(arbs_3.io.chosen_oh[0], 3, 3)
node _io_switch_sel_3_0_3_0_T_1 = and(arbs_3.io.in[3].valid, _io_switch_sel_3_0_3_0_T)
node _io_switch_sel_3_0_3_0_T_2 = and(_io_switch_sel_3_0_3_0_T_1, arbs_3.io.out[0].valid)
connect io.switch_sel.`3`[0].`3`[0], _io_switch_sel_3_0_3_0_T_2
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`3`[0].tail, UInt<1>(0h0)
node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0])
when _T :
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail
node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1])
when _T_1 :
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail
node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2])
when _T_2 :
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail
node _T_3 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0])
when _T_3 :
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail
node _T_4 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[1])
when _T_4 :
connect io.credit_alloc.`1`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[1].tail, arbs_1.io.out[0].bits.tail
node _T_5 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[2])
when _T_5 :
connect io.credit_alloc.`1`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[2].tail, arbs_1.io.out[0].bits.tail
node _T_6 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0])
when _T_6 :
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail
node _T_7 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[1])
when _T_7 :
connect io.credit_alloc.`2`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[1].tail, arbs_2.io.out[0].bits.tail
node _T_8 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[2])
when _T_8 :
connect io.credit_alloc.`2`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[2].tail, arbs_2.io.out[0].bits.tail
node _T_9 = and(arbs_3.io.out[0].valid, arbs_3.io.out[0].bits.vc_sel.`3`[0])
when _T_9 :
connect io.credit_alloc.`3`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`3`[0].tail, arbs_3.io.out[0].bits.tail | module SwitchAllocator_11( // @[SwitchAllocator.scala:64:7]
input clock, // @[SwitchAllocator.scala:64:7]
input reset, // @[SwitchAllocator.scala:64:7]
output io_req_3_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_3_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_3_0_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_1_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_2_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_3_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_3_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_3_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_3_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14]
);
wire _arbs_3_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_3_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_3_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_3_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_3_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_2; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_0 | io_req_0_0_bits_vc_sel_0_1 | io_req_0_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_1_0 | io_req_0_0_bits_vc_sel_1_1 | io_req_0_0_bits_vc_sel_1_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_2_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_2_0 | io_req_0_0_bits_vc_sel_2_1 | io_req_0_0_bits_vc_sel_2_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_3_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 | io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_1_0 | io_req_1_0_bits_vc_sel_1_1 | io_req_1_0_bits_vc_sel_1_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_2_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_2_0 | io_req_1_0_bits_vc_sel_2_1 | io_req_1_0_bits_vc_sel_2_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_3_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 | io_req_2_0_bits_vc_sel_0_1 | io_req_2_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_1_0 | io_req_2_0_bits_vc_sel_1_1 | io_req_2_0_bits_vc_sel_1_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_2_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_2_0 | io_req_2_0_bits_vc_sel_2_1 | io_req_2_0_bits_vc_sel_2_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_3_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_3_valid = io_req_3_0_valid & (io_req_3_0_bits_vc_sel_0_0 | io_req_3_0_bits_vc_sel_0_1 | io_req_3_0_bits_vc_sel_0_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_3_valid = io_req_3_0_valid & (io_req_3_0_bits_vc_sel_1_0 | io_req_3_0_bits_vc_sel_1_1 | io_req_3_0_bits_vc_sel_1_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_2_io_in_3_valid = io_req_3_0_valid & (io_req_3_0_bits_vc_sel_2_0 | io_req_3_0_bits_vc_sel_2_1 | io_req_3_0_bits_vc_sel_2_2); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_3_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37]
wire io_credit_alloc_3_0_alloc_0 = _arbs_3_io_out_0_valid & _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45, :120:33]
SwitchArbiter_90 arbs_0 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_0_io_in_0_ready),
.io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0),
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1),
.io_in_0_bits_vc_sel_1_2 (io_req_0_0_bits_vc_sel_1_2),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_0_io_in_1_ready),
.io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0),
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1),
.io_in_1_bits_vc_sel_1_2 (io_req_1_0_bits_vc_sel_1_2),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_0_io_in_2_ready),
.io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0),
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_1 (io_req_2_0_bits_vc_sel_1_1),
.io_in_2_bits_vc_sel_1_2 (io_req_2_0_bits_vc_sel_1_2),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_0_io_in_3_ready),
.io_in_3_valid (arbs_0_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0),
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_1 (io_req_3_0_bits_vc_sel_1_1),
.io_in_3_bits_vc_sel_1_2 (io_req_3_0_bits_vc_sel_1_2),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_0_io_out_0_valid),
.io_out_0_bits_vc_sel_3_0 (/* unused */),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_1 (/* unused */),
.io_out_0_bits_vc_sel_1_2 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (_arbs_0_io_out_0_bits_vc_sel_0_0),
.io_out_0_bits_tail (/* unused */),
.io_chosen_oh_0 (_arbs_0_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_90 arbs_1 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_1_io_in_0_ready),
.io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0),
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1),
.io_in_0_bits_vc_sel_1_2 (io_req_0_0_bits_vc_sel_1_2),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_1_io_in_1_ready),
.io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0),
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1),
.io_in_1_bits_vc_sel_1_2 (io_req_1_0_bits_vc_sel_1_2),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_1_io_in_2_ready),
.io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0),
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_1 (io_req_2_0_bits_vc_sel_1_1),
.io_in_2_bits_vc_sel_1_2 (io_req_2_0_bits_vc_sel_1_2),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_1_io_in_3_ready),
.io_in_3_valid (arbs_1_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0),
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_1 (io_req_3_0_bits_vc_sel_1_1),
.io_in_3_bits_vc_sel_1_2 (io_req_3_0_bits_vc_sel_1_2),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_1_io_out_0_valid),
.io_out_0_bits_vc_sel_3_0 (/* unused */),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_1 (_arbs_1_io_out_0_bits_vc_sel_1_1),
.io_out_0_bits_vc_sel_1_2 (_arbs_1_io_out_0_bits_vc_sel_1_2),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_tail (/* unused */),
.io_chosen_oh_0 (_arbs_1_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_90 arbs_2 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_2_io_in_0_ready),
.io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0),
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1),
.io_in_0_bits_vc_sel_1_2 (io_req_0_0_bits_vc_sel_1_2),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_2_io_in_1_ready),
.io_in_1_valid (arbs_2_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0),
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1),
.io_in_1_bits_vc_sel_1_2 (io_req_1_0_bits_vc_sel_1_2),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_2_io_in_2_ready),
.io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0),
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_1 (io_req_2_0_bits_vc_sel_1_1),
.io_in_2_bits_vc_sel_1_2 (io_req_2_0_bits_vc_sel_1_2),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_2_io_in_3_ready),
.io_in_3_valid (arbs_2_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0),
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_1 (io_req_3_0_bits_vc_sel_1_1),
.io_in_3_bits_vc_sel_1_2 (io_req_3_0_bits_vc_sel_1_2),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_2_io_out_0_valid),
.io_out_0_bits_vc_sel_3_0 (/* unused */),
.io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0),
.io_out_0_bits_vc_sel_1_1 (/* unused */),
.io_out_0_bits_vc_sel_1_2 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_tail (/* unused */),
.io_chosen_oh_0 (_arbs_2_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_90 arbs_3 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_3_io_in_0_ready),
.io_in_0_valid (arbs_3_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0),
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_1 (io_req_0_0_bits_vc_sel_1_1),
.io_in_0_bits_vc_sel_1_2 (io_req_0_0_bits_vc_sel_1_2),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_3_io_in_1_ready),
.io_in_1_valid (arbs_3_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0),
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_1 (io_req_1_0_bits_vc_sel_1_1),
.io_in_1_bits_vc_sel_1_2 (io_req_1_0_bits_vc_sel_1_2),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_3_io_in_2_ready),
.io_in_2_valid (arbs_3_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_3_0 (io_req_2_0_bits_vc_sel_3_0),
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_1 (io_req_2_0_bits_vc_sel_1_1),
.io_in_2_bits_vc_sel_1_2 (io_req_2_0_bits_vc_sel_1_2),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_3_io_in_3_ready),
.io_in_3_valid (arbs_3_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0),
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_1 (io_req_3_0_bits_vc_sel_1_1),
.io_in_3_bits_vc_sel_1_2 (io_req_3_0_bits_vc_sel_1_2),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_3_io_out_0_valid),
.io_out_0_bits_vc_sel_3_0 (_arbs_3_io_out_0_bits_vc_sel_3_0),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_1 (/* unused */),
.io_out_0_bits_vc_sel_1_2 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_tail (_arbs_3_io_out_0_bits_tail),
.io_chosen_oh_0 (_arbs_3_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
assign io_req_3_0_ready = _arbs_0_io_in_3_ready & arbs_0_io_in_3_valid | _arbs_1_io_in_3_ready & arbs_1_io_in_3_valid | _arbs_2_io_in_3_ready & arbs_2_io_in_3_valid | _arbs_3_io_in_3_ready & arbs_3_io_in_3_valid; // @[Decoupled.scala:51:35]
assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid | _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid | _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid | _arbs_3_io_in_2_ready & arbs_3_io_in_2_valid; // @[Decoupled.scala:51:35]
assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid | _arbs_2_io_in_1_ready & arbs_2_io_in_1_valid | _arbs_3_io_in_1_ready & arbs_3_io_in_1_valid; // @[Decoupled.scala:51:35]
assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid | _arbs_3_io_in_0_ready & arbs_3_io_in_0_valid; // @[Decoupled.scala:51:35]
assign io_credit_alloc_3_0_alloc = io_credit_alloc_3_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33]
assign io_credit_alloc_3_0_tail = io_credit_alloc_3_0_alloc_0 & _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]
assign io_credit_alloc_2_0_alloc = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_1_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_1_2_alloc = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_0_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_switch_sel_3_0_3_0 = arbs_3_io_in_3_valid & _arbs_3_io_chosen_oh_0[3] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_3_0_2_0 = arbs_3_io_in_2_valid & _arbs_3_io_chosen_oh_0[2] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_3_0_1_0 = arbs_3_io_in_1_valid & _arbs_3_io_chosen_oh_0[1] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_3_0_0_0 = arbs_3_io_in_0_valid & _arbs_3_io_chosen_oh_0[0] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_3_0 = arbs_2_io_in_3_valid & _arbs_2_io_chosen_oh_0[3] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_1_0 = arbs_2_io_in_1_valid & _arbs_2_io_chosen_oh_0[1] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_3_0 = arbs_1_io_in_3_valid & _arbs_1_io_chosen_oh_0[3] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_3_0 = arbs_0_io_in_3_valid & _arbs_0_io_chosen_oh_0[3] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_18 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_36
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_18
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _T_1 = eq(UInt<5>(0h1b), io.in.bits.egress_id)
node _T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id)
node _T_3 = eq(UInt<5>(0h15), io.in.bits.egress_id)
node _T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id)
node _T_5 = or(_T, _T_1)
node _T_6 = or(_T_5, _T_2)
node _T_7 = or(_T_6, _T_3)
node _T_8 = or(_T_7, _T_4)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = and(io.in.valid, _T_9)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_11, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h7)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h1b), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h15), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<2>(0h3), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0h9), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0ha), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7)
node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8)
node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h1b), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h15), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h18), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h7))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6]
connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
node _T_15 = and(io.in.ready, io.in.valid)
node _T_16 = and(_T_15, io.in.bits.head)
node _T_17 = and(_T_16, at_dest)
when _T_17 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
node _T_18 = eq(UInt<4>(0h8), io.in.bits.egress_id)
when _T_18 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_19 = eq(UInt<4>(0h9), io.in.bits.egress_id)
when _T_19 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_21 = and(route_q.io.enq.valid, _T_20)
node _T_22 = eq(_T_21, UInt<1>(0h0))
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
node _T_25 = eq(_T_22, UInt<1>(0h0))
when _T_25 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_22, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_37
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_18
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_27 = and(vcalloc_q.io.enq.valid, _T_26)
node _T_28 = eq(_T_27, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node c_lo = cat(c_lo_hi, c_lo_lo)
node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node c_hi = cat(c_hi_hi, c_hi_lo)
node _c_T = cat(c_hi, c_lo)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node _c_T_1 = cat(c_hi_1, _c_T)
node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1)
node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1)
node _c_T_2 = cat(c_hi_2, c_lo_1)
node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _c_T_3 = cat(c_hi_3, _c_T_2)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo)
node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo)
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_18( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h1B; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h1E; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_11 = {2'h0, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T}}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire [2:0] _GEN_0 = _route_buffer_io_enq_bits_flow_egress_node_T_11[2:0] | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h6 : 3'h0); // @[Mux.scala:30:73]
wire [3:0] _GEN_1 = {_route_buffer_io_enq_bits_flow_egress_node_T_11[3], _GEN_0}; // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_1 == 4'h7; // @[Decoupled.scala:51:35]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_1 != 4'h7; // @[Decoupled.scala:51:35]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_201 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_201( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_121 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_121( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_334 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_334( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_196 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_348
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_196( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_348 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_25 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
inst input_buffer of InputBuffer_25
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter3_RouteComputerReq_25
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _T_12 = and(io.router_req.ready, io.router_req.valid)
when _T_12 :
node _T_13 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_13, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_17 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_18 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_19 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3]
wire vcalloc_vals : UInt<1>[3]
node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12)
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15)
node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_20 = and(io.router_req.ready, io.router_req.valid)
when _T_20 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_22 = or(_T_21, vcalloc_vals[2])
when _T_22 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = bits(vcalloc_sel, 0, 0)
node _mask_T_7 = bits(vcalloc_sel, 1, 1)
node _mask_T_8 = bits(vcalloc_sel, 2, 2)
node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_9, _mask_T_10)
node _mask_T_13 = or(_mask_T_12, _mask_T_11)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_13
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3]
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4)
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3]
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32
connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3]
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42
connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1]
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16
wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62
connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72
connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77
connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_23 = bits(vcalloc_sel, 0, 0)
node _T_24 = and(vcalloc_vals[0], _T_23)
node _T_25 = and(_T_24, io.vcalloc_req.ready)
when _T_25 :
connect states[0].g, UInt<3>(0h3)
node _T_26 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_26 :
connect vcalloc_vals[0], UInt<1>(0h1)
connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[2]
invalidate vcalloc_reqs[1].vc_sel.`3`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_27 = bits(vcalloc_sel, 2, 2)
node _T_28 = and(vcalloc_vals[2], _T_27)
node _T_29 = and(_T_28, io.vcalloc_req.ready)
when _T_29 :
connect states[2].g, UInt<3>(0h3)
node _T_30 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_30 :
connect vcalloc_vals[2], UInt<1>(0h1)
connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready)
node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_5
node _T_31 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_31 :
node _T_32 = bits(vcalloc_sel, 0, 0)
when _T_32 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_33 = bits(vcalloc_sel, 1, 1)
when _T_33 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_34 = bits(vcalloc_sel, 2, 2)
when _T_34 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_62
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1])
node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0])
node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1])
node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0])
node credit_available_hi_2 = cat(states[0].vc_sel.`2`[2], states[0].vc_sel.`2`[1])
node _credit_available_T_2 = cat(credit_available_hi_2, states[0].vc_sel.`2`[0])
node credit_available_lo = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_3 = cat(states[0].vc_sel.`3`[0], _credit_available_T_2)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo)
node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0])
node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1])
node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0])
node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4)
node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_35 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_36 = and(_T_35, input_buffer.io.deq[0].bits.tail)
when _T_36 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0]
node credit_available_hi_8 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1])
node _credit_available_T_9 = cat(credit_available_hi_8, states[2].vc_sel.`0`[0])
node credit_available_hi_9 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1])
node _credit_available_T_10 = cat(credit_available_hi_9, states[2].vc_sel.`1`[0])
node credit_available_hi_10 = cat(states[2].vc_sel.`2`[2], states[2].vc_sel.`2`[1])
node _credit_available_T_11 = cat(credit_available_hi_10, states[2].vc_sel.`2`[0])
node credit_available_lo_2 = cat(_credit_available_T_10, _credit_available_T_9)
node credit_available_hi_11 = cat(states[2].vc_sel.`3`[0], _credit_available_T_11)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_2)
node credit_available_hi_12 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_13 = cat(credit_available_hi_12, io.out_credit_available.`0`[0])
node credit_available_hi_13 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_14 = cat(credit_available_hi_13, io.out_credit_available.`1`[0])
node credit_available_hi_14 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1])
node _credit_available_T_15 = cat(credit_available_hi_14, io.out_credit_available.`2`[0])
node credit_available_lo_3 = cat(_credit_available_T_14, _credit_available_T_13)
node credit_available_hi_15 = cat(io.out_credit_available.`3`[0], _credit_available_T_15)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_3)
node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16)
node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_37 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_38 = and(_T_37, input_buffer.io.deq[2].bits.tail)
when _T_38 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_9
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5)
node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8
node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_10
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _vc_sel_WIRE : UInt<1>[3]
node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4)
node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_7
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_12
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_17
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_4 : UInt<1>[3]
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_22
connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_27
connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6
node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_32
connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7
connect vc_sel.`1`, _vc_sel_WIRE_4
wire _vc_sel_WIRE_8 : UInt<1>[3]
node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_37
connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_42
connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10
node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_47
connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11
connect vc_sel.`2`, _vc_sel_WIRE_8
wire _vc_sel_WIRE_12 : UInt<1>[1]
node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_52
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
connect vc_sel.`3`, _vc_sel_WIRE_12
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2])
node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2])
node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0])
node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2)
node virt_channel_lo = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1])
node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0])
node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2)
node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0)
node _virt_channel_T_6 = orr(virt_channel_hi_3)
node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1)
node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1)
node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8)
node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1])
node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0])
node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0))
node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0))
node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16)
node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17)
node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_21
node _T_39 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_39 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4)
node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5)
wire _salloc_outs_0_flit_payload_WIRE : UInt<145>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4)
node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4)
node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4)
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[2], UInt<1>(0h0)
connect states[0].vc_sel.`2`[1], UInt<1>(0h0)
connect states[0].vc_sel.`2`[2], UInt<1>(0h0)
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`2`[2]
invalidate states[1].vc_sel.`3`[0]
invalidate states[1].g
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[2].vc_sel.`2`[1], UInt<1>(0h0)
connect states[2].vc_sel.`2`[2], UInt<1>(0h0)
node _T_40 = asUInt(reset)
when _T_40 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0) | module InputUnit_25( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [2:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_2_vc_sel_0_2; // @[MixedVec.scala:116:9]
wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _GEN_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_2_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_1 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_2 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_143 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_143( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [4:0] next_uop_ppred = 5'h0; // @[issue-slot.scala:103:21]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_prs3_busy = 1'h0; // @[issue-slot.scala:103:21]
wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21]
wire _p3_T = 1'h1; // @[issue-slot.scala:171:11]
wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = ~io_in_uop_valid_0 & p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = ~io_in_uop_valid_0 & p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :99:29, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_ShuttleTile_i2_o1_a32d64s4k3z4c :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonIn_1.e.bits.sink
invalidate anonIn_1.e.valid
invalidate anonIn_1.e.ready
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.c.bits.corrupt
invalidate anonIn_1.c.bits.data
invalidate anonIn_1.c.bits.address
invalidate anonIn_1.c.bits.source
invalidate anonIn_1.c.bits.size
invalidate anonIn_1.c.bits.param
invalidate anonIn_1.c.bits.opcode
invalidate anonIn_1.c.valid
invalidate anonIn_1.c.ready
invalidate anonIn_1.b.bits.corrupt
invalidate anonIn_1.b.bits.data
invalidate anonIn_1.b.bits.mask
invalidate anonIn_1.b.bits.address
invalidate anonIn_1.b.bits.source
invalidate anonIn_1.b.bits.size
invalidate anonIn_1.b.bits.param
invalidate anonIn_1.b.bits.opcode
invalidate anonIn_1.b.valid
invalidate anonIn_1.b.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor_38
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_39
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink
connect monitor_1.io.in.e.valid, anonIn_1.e.valid
connect monitor_1.io.in.e.ready, anonIn_1.e.ready
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt
connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data
connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address
connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source
connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size
connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param
connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode
connect monitor_1.io.in.c.valid, anonIn_1.c.valid
connect monitor_1.io.in.c.ready, anonIn_1.c.ready
connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt
connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data
connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask
connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address
connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source
connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size
connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param
connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode
connect monitor_1.io.in.b.valid, anonIn_1.b.valid
connect monitor_1.io.in.b.ready, anonIn_1.b.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate anonOut.e.bits.sink
invalidate anonOut.e.valid
invalidate anonOut.e.ready
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.c.bits.corrupt
invalidate anonOut.c.bits.data
invalidate anonOut.c.bits.address
invalidate anonOut.c.bits.source
invalidate anonOut.c.bits.size
invalidate anonOut.c.bits.param
invalidate anonOut.c.bits.opcode
invalidate anonOut.c.valid
invalidate anonOut.c.ready
invalidate anonOut.b.bits.corrupt
invalidate anonOut.b.bits.data
invalidate anonOut.b.bits.mask
invalidate anonOut.b.bits.address
invalidate anonOut.b.bits.source
invalidate anonOut.b.bits.size
invalidate anonOut.b.bits.param
invalidate anonOut.b.bits.opcode
invalidate anonOut.b.valid
invalidate anonOut.b.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<4>(0h8))
connect in[0].a.bits.source, _in_0_a_bits_source_T
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
invalidate in[0].b.valid
invalidate in[0].b.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
connect in[0].b.ready, UInt<1>(0h1)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
invalidate in[0].c.bits.corrupt
invalidate in[0].c.bits.data
invalidate in[0].c.bits.address
invalidate in[0].c.bits.source
invalidate in[0].c.bits.size
invalidate in[0].c.bits.param
invalidate in[0].c.bits.opcode
invalidate in[0].c.valid
invalidate in[0].c.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<1>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<3>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
invalidate _WIRE_5.bits.corrupt
invalidate _WIRE_5.bits.data
invalidate _WIRE_5.bits.address
invalidate _WIRE_5.bits.source
invalidate _WIRE_5.bits.size
invalidate _WIRE_5.bits.param
invalidate _WIRE_5.bits.opcode
invalidate _WIRE_5.valid
invalidate _WIRE_5.ready
connect in[0].c.valid, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
connect anonIn.d.bits.source, UInt<1>(0h0)
invalidate in[0].e.bits.sink
invalidate in[0].e.valid
invalidate in[0].e.ready
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits.sink, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.sink
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
connect in[0].e.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0))
connect in[1].a.bits.source, _in_1_a_bits_source_T
connect anonIn_1.b.bits.corrupt, in[1].b.bits.corrupt
connect anonIn_1.b.bits.data, in[1].b.bits.data
connect anonIn_1.b.bits.mask, in[1].b.bits.mask
connect anonIn_1.b.bits.address, in[1].b.bits.address
connect anonIn_1.b.bits.source, in[1].b.bits.source
connect anonIn_1.b.bits.size, in[1].b.bits.size
connect anonIn_1.b.bits.param, in[1].b.bits.param
connect anonIn_1.b.bits.opcode, in[1].b.bits.opcode
connect anonIn_1.b.valid, in[1].b.valid
connect in[1].b.ready, anonIn_1.b.ready
node _anonIn_b_bits_source_T = bits(in[1].b.bits.source, 2, 0)
connect anonIn_1.b.bits.source, _anonIn_b_bits_source_T
connect in[1].c.bits.corrupt, anonIn_1.c.bits.corrupt
connect in[1].c.bits.data, anonIn_1.c.bits.data
connect in[1].c.bits.address, anonIn_1.c.bits.address
connect in[1].c.bits.source, anonIn_1.c.bits.source
connect in[1].c.bits.size, anonIn_1.c.bits.size
connect in[1].c.bits.param, anonIn_1.c.bits.param
connect in[1].c.bits.opcode, anonIn_1.c.bits.opcode
connect in[1].c.valid, anonIn_1.c.valid
connect anonIn_1.c.ready, in[1].c.ready
node _in_1_c_bits_source_T = or(anonIn_1.c.bits.source, UInt<1>(0h0))
connect in[1].c.bits.source, _in_1_c_bits_source_T
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T = bits(in[1].d.bits.source, 2, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T
connect in[1].e.bits.sink, anonIn_1.e.bits.sink
connect in[1].e.valid, anonIn_1.e.valid
connect anonIn_1.e.ready, in[1].e.ready
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
connect out[0].b.bits.corrupt, anonOut.b.bits.corrupt
connect out[0].b.bits.data, anonOut.b.bits.data
connect out[0].b.bits.mask, anonOut.b.bits.mask
connect out[0].b.bits.address, anonOut.b.bits.address
connect out[0].b.bits.source, anonOut.b.bits.source
connect out[0].b.bits.size, anonOut.b.bits.size
connect out[0].b.bits.param, anonOut.b.bits.param
connect out[0].b.bits.opcode, anonOut.b.bits.opcode
connect out[0].b.valid, anonOut.b.valid
connect anonOut.b.ready, out[0].b.ready
connect anonOut.c.bits.corrupt, out[0].c.bits.corrupt
connect anonOut.c.bits.data, out[0].c.bits.data
connect anonOut.c.bits.address, out[0].c.bits.address
connect anonOut.c.bits.source, out[0].c.bits.source
connect anonOut.c.bits.size, out[0].c.bits.size
connect anonOut.c.bits.param, out[0].c.bits.param
connect anonOut.c.bits.opcode, out[0].c.bits.opcode
connect anonOut.c.valid, out[0].c.valid
connect out[0].c.ready, anonOut.c.ready
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
connect anonOut.e.bits.sink, out[0].e.bits.sink
connect anonOut.e.valid, out[0].e.valid
connect out[0].e.ready, anonOut.e.ready
node _anonOut_e_bits_sink_T = bits(out[0].e.bits.sink, 2, 0)
connect anonOut.e.bits.sink, _anonOut_e_bits_sink_T
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(in[1].c.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
node requestBOI_0_0 = eq(out[0].b.bits.source, UInt<4>(0h8))
node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<3>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 2, 0)
node _requestBOI_T = shr(out[0].b.bits.source, 3)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<3>(0h7))
node requestBOI_0_1 = and(_requestBOI_T_3, _requestBOI_T_4)
node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<4>(0h8))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<3>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 2, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 3)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<3>(0h7))
node requestDOI_0_1 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0)
node _requestEIO_T = shr(in[0].e.bits.sink, 3)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7))
node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4)
node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0)
node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7))
node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0)
node beatsCI_1 = mux(beatsCI_opdata_1, beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[0].bits.data, out[0].b.bits.data
connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[0].bits.address, out[0].b.bits.address
connect portsBIO_filtered[0].bits.source, out[0].b.bits.source
connect portsBIO_filtered[0].bits.size, out[0].b.bits.size
connect portsBIO_filtered[0].bits.param, out[0].b.bits.param
connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt
connect portsBIO_filtered[1].bits.data, out[0].b.bits.data
connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask
connect portsBIO_filtered[1].bits.address, out[0].b.bits.address
connect portsBIO_filtered[1].bits.source, out[0].b.bits.source
connect portsBIO_filtered[1].bits.size, out[0].b.bits.size
connect portsBIO_filtered[1].bits.param, out[0].b.bits.param
connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1)
wire _portsBIO_out_0_b_ready_WIRE : UInt<1>
connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2
connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, in[0].c.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect in[0].c.ready, portsCOI_filtered[0].ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, in[1].c.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect in[1].c.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1]
connect portsEOI_filtered[0].bits, in[0].e.bits
node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect in[0].e.ready, portsEOI_filtered[0].ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1]
connect portsEOI_filtered_1[0].bits, in[1].e.bits
node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect in[1].e.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<4>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
connect out[0].c, portsCOI_filtered_1[0]
connect out[0].e, portsEOI_filtered_1[0]
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
invalidate in[0].b.bits.corrupt
invalidate in[0].b.bits.data
invalidate in[0].b.bits.mask
invalidate in[0].b.bits.address
invalidate in[0].b.bits.source
invalidate in[0].b.bits.size
invalidate in[0].b.bits.param
invalidate in[0].b.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect in[1].b, portsBIO_filtered[1]
connect in[1].d, portsDIO_filtered[1] | module TLXbar_MasterXbar_ShuttleTile_i2_o1_a32d64s4k3z4c( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire [2:0] out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [3:0] in_1_c_bits_source; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_b_ready_0 = auto_anon_in_1_b_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_1_c_valid_0 = auto_anon_in_1_c_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_c_bits_opcode_0 = auto_anon_in_1_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_c_bits_param_0 = auto_anon_in_1_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_c_bits_size_0 = auto_anon_in_1_c_bits_size; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_c_bits_source_0 = auto_anon_in_1_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_c_bits_address_0 = auto_anon_in_1_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_c_bits_data_0 = auto_anon_in_1_c_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_c_bits_corrupt_0 = auto_anon_in_1_c_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_1_e_valid_0 = auto_anon_in_1_e_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_e_bits_sink_0 = auto_anon_in_1_e_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire in_0_b_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_valid = 1'h0; // @[Xbar.scala:159:18]
wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire in_0_e_ready = 1'h0; // @[Xbar.scala:159:18]
wire in_0_e_valid = 1'h0; // @[Xbar.scala:159:18]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_out_0_b_ready_T = 1'h0; // @[Mux.scala:30:73]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire in_0_b_ready = 1'h1; // @[Xbar.scala:159:18]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [2:0] in_0_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_c_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] in_0_e_bits_sink = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] _requestEIO_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29]
wire [2:0] requestEIO_uncommonBits = 3'h0; // @[Parameters.scala:52:56]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsEOI_filtered_0_bits_sink = 3'h0; // @[Xbar.scala:352:24]
wire [63:0] in_0_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] in_0_c_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [31:0] in_0_b_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] in_0_c_bits_address = 32'h0; // @[Xbar.scala:159:18]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [3:0] in_0_b_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_0_b_bits_source = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_0_c_bits_size = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] in_0_c_bits_source = 4'h0; // @[Xbar.scala:159:18]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsCOI_filtered_0_bits_source = 4'h0; // @[Xbar.scala:352:24]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [7:0] in_0_b_bits_mask = 8'h0; // @[Xbar.scala:159:18]
wire [1:0] in_0_b_bits_param = 2'h0; // @[Xbar.scala:159:18]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_b_ready = auto_anon_in_1_b_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_1_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] anonIn_1_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_b_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_1_c_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_c_valid = auto_anon_in_1_c_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_c_bits_opcode = auto_anon_in_1_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_c_bits_param = auto_anon_in_1_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_c_bits_size = auto_anon_in_1_c_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_c_bits_source = auto_anon_in_1_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_c_bits_address = auto_anon_in_1_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_c_bits_data = auto_anon_in_1_c_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_c_bits_corrupt = auto_anon_in_1_c_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_1_e_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_e_valid = auto_anon_in_1_e_valid_0; // @[Xbar.scala:74:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_e_bits_sink = auto_anon_in_1_e_bits_sink_0; // @[Xbar.scala:74:9]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_b_ready; // @[MixedNode.scala:542:17]
wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9]
wire anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9]
wire anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_b_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_b_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_b_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_b_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_b_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_1_b_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_b_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_b_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_b_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_c_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_e_ready_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [2:0] _in_1_a_bits_source_T = anonIn_1_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_b_ready = anonIn_1_b_ready; // @[Xbar.scala:159:18]
wire in_1_b_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_valid_0 = anonIn_1_b_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_b_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_opcode_0 = anonIn_1_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_b_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_param_0 = anonIn_1_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_b_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_size_0 = anonIn_1_b_bits_size; // @[Xbar.scala:74:9]
wire [2:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_1_b_bits_source_0 = anonIn_1_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] in_1_b_bits_address; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_address_0 = anonIn_1_b_bits_address; // @[Xbar.scala:74:9]
wire [7:0] in_1_b_bits_mask; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_mask_0 = anonIn_1_b_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] in_1_b_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_data_0 = anonIn_1_b_bits_data; // @[Xbar.scala:74:9]
wire in_1_b_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_b_bits_corrupt_0 = anonIn_1_b_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_c_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_c_ready_0 = anonIn_1_c_ready; // @[Xbar.scala:74:9]
wire in_1_c_valid = anonIn_1_c_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_opcode = anonIn_1_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_c_bits_param = anonIn_1_c_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_c_bits_size = anonIn_1_c_bits_size; // @[Xbar.scala:159:18]
wire [2:0] _in_1_c_bits_source_T = anonIn_1_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] in_1_c_bits_address = anonIn_1_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] in_1_c_bits_data = anonIn_1_c_bits_data; // @[Xbar.scala:159:18]
wire in_1_c_bits_corrupt = anonIn_1_c_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_e_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_e_ready_0 = anonIn_1_e_ready; // @[Xbar.scala:74:9]
wire in_1_e_valid = anonIn_1_e_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_e_bits_sink = anonIn_1_e_bits_sink; // @[Xbar.scala:159:18]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_b_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9]
wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19]
wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire [7:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19]
wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19]
wire out_0_c_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9]
wire [3:0] out_0_c_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] out_0_c_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9]
wire out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_c_bits_corrupt_0 = anonOut_c_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19]
wire out_0_e_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9]
wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] _in_0_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [2:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_1_ready = in_1_b_ready; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_b_valid = in_1_b_valid; // @[Xbar.scala:159:18]
wire [2:0] portsBIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_opcode = in_1_b_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsBIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_param = in_1_b_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsBIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_size = in_1_b_bits_size; // @[Xbar.scala:159:18]
wire [3:0] portsBIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_address = in_1_b_bits_address; // @[Xbar.scala:159:18]
wire [7:0] portsBIO_filtered_1_bits_mask; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_mask = in_1_b_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] portsBIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_data = in_1_b_bits_data; // @[Xbar.scala:159:18]
wire portsBIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_b_bits_corrupt = in_1_b_bits_corrupt; // @[Xbar.scala:159:18]
wire portsCOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_c_ready = in_1_c_ready; // @[Xbar.scala:159:18]
wire _portsCOI_filtered_0_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsCOI_filtered_1_0_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsCOI_filtered_1_0_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestCIO_T_5 = in_1_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsCOI_filtered_1_0_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsCOI_filtered_1_0_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsCOI_filtered_1_0_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire [2:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsEOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_e_ready = in_1_e_ready; // @[Xbar.scala:159:18]
wire _portsEOI_filtered_0_valid_T_3 = in_1_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] _requestEIO_uncommonBits_T_1 = in_1_e_bits_sink; // @[Xbar.scala:159:18]
wire [2:0] portsEOI_filtered_1_0_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
wire [3:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [3:0] in_1_b_bits_source; // @[Xbar.scala:159:18]
wire [3:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign _in_0_a_bits_source_T = {3'h4, anonIn_a_bits_source}; // @[Xbar.scala:166:55]
assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign in_1_a_bits_source = {1'h0, _in_1_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_b_bits_source_T = in_1_b_bits_source[2:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign in_1_c_bits_source = {1'h0, _in_1_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}]
assign _anonIn_d_bits_source_T = in_1_d_bits_source[2:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19]
wire [2:0] portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
wire [1:0] portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
wire [3:0] portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19]
wire [3:0] portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
wire [31:0] portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
wire [7:0] portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
wire [63:0] portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
wire portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_1_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire portsCOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19]
assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19]
assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19]
assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19]
assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19]
assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19]
assign anonOut_c_bits_corrupt = out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [3:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_1_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24]
wire portsEOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19]
assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestCIO_T_6 = {1'h0, _requestCIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire requestBOI_0_0 = out_0_b_bits_source == 4'h8; // @[Xbar.scala:216:19]
wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54]
wire [2:0] requestBOI_uncommonBits = _requestBOI_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire _requestBOI_T = out_0_b_bits_source[3]; // @[Xbar.scala:216:19]
wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestBOI_0_1 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54]
wire requestDOI_0_0 = out_0_d_bits_source == 4'h8; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire [2:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[3]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_1 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire [2:0] requestEIO_uncommonBits_1 = _requestEIO_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsBO_decode = _beatsBO_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19]
wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF << in_1_c_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsCI_decode_T_4 = _beatsCI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsCI_decode_T_5 = ~_beatsCI_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] beatsCI_decode_1 = _beatsCI_decode_T_5[11:3]; // @[package.scala:243:46]
wire beatsCI_opdata_1 = in_1_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [8:0] beatsCI_1 = beatsCI_opdata_1 ? beatsCI_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_b_valid = portsBIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_opcode = portsBIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_param = portsBIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_size = portsBIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_source = portsBIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_address = portsBIO_filtered_1_bits_address; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_mask = portsBIO_filtered_1_bits_mask; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_data = portsBIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_b_bits_corrupt = portsBIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsBIO_out_0_b_ready_T_1 = requestBOI_0_1 & portsBIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T_1; // @[Mux.scala:30:73]
assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73]
assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73]
assign in_1_c_ready = portsCOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_c_valid = portsCOI_filtered_1_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_opcode = portsCOI_filtered_1_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_param = portsCOI_filtered_1_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_size = portsCOI_filtered_1_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_source = portsCOI_filtered_1_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_address = portsCOI_filtered_1_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_data = portsCOI_filtered_1_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign out_0_c_bits_corrupt = portsCOI_filtered_1_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsCOI_filtered_1_0_valid = _portsCOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign in_1_e_ready = portsEOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
assign out_0_e_valid = portsEOI_filtered_1_0_valid; // @[Xbar.scala:216:19, :352:24]
assign out_0_e_bits_sink = portsEOI_filtered_1_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsEOI_filtered_1_0_valid = _portsEOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_158 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_173
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_158( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_173 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_187 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_187( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_216 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_216( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLUART :
input clock : Clock
input reset : Reset
output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}}
inst buffer of TLBuffer_a29d64s11k1z2u
connect buffer.clock, clock
connect buffer.reset, reset
inst intsource of IntSyncCrossingSource_n1x1_5
connect intsource.clock, clock
connect intsource.reset, reset
wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>}
invalidate ioNodeOut.rxd
invalidate ioNodeOut.txd
wire intnodeOut : UInt<1>[1]
invalidate intnodeOut[0]
wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlNodeIn.d.bits.corrupt
invalidate controlNodeIn.d.bits.data
invalidate controlNodeIn.d.bits.denied
invalidate controlNodeIn.d.bits.sink
invalidate controlNodeIn.d.bits.source
invalidate controlNodeIn.d.bits.size
invalidate controlNodeIn.d.bits.param
invalidate controlNodeIn.d.bits.opcode
invalidate controlNodeIn.d.valid
invalidate controlNodeIn.d.ready
invalidate controlNodeIn.a.bits.corrupt
invalidate controlNodeIn.a.bits.data
invalidate controlNodeIn.a.bits.mask
invalidate controlNodeIn.a.bits.address
invalidate controlNodeIn.a.bits.source
invalidate controlNodeIn.a.bits.size
invalidate controlNodeIn.a.bits.param
invalidate controlNodeIn.a.bits.opcode
invalidate controlNodeIn.a.valid
invalidate controlNodeIn.a.ready
inst monitor of TLMonitor_54
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, controlNodeIn.d.valid
connect monitor.io.in.d.ready, controlNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, controlNodeIn.a.valid
connect monitor.io.in.a.ready, controlNodeIn.a.ready
wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingOut.d.bits.corrupt
invalidate controlXingOut.d.bits.data
invalidate controlXingOut.d.bits.denied
invalidate controlXingOut.d.bits.sink
invalidate controlXingOut.d.bits.source
invalidate controlXingOut.d.bits.size
invalidate controlXingOut.d.bits.param
invalidate controlXingOut.d.bits.opcode
invalidate controlXingOut.d.valid
invalidate controlXingOut.d.ready
invalidate controlXingOut.a.bits.corrupt
invalidate controlXingOut.a.bits.data
invalidate controlXingOut.a.bits.mask
invalidate controlXingOut.a.bits.address
invalidate controlXingOut.a.bits.source
invalidate controlXingOut.a.bits.size
invalidate controlXingOut.a.bits.param
invalidate controlXingOut.a.bits.opcode
invalidate controlXingOut.a.valid
invalidate controlXingOut.a.ready
wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingIn.d.bits.corrupt
invalidate controlXingIn.d.bits.data
invalidate controlXingIn.d.bits.denied
invalidate controlXingIn.d.bits.sink
invalidate controlXingIn.d.bits.source
invalidate controlXingIn.d.bits.size
invalidate controlXingIn.d.bits.param
invalidate controlXingIn.d.bits.opcode
invalidate controlXingIn.d.valid
invalidate controlXingIn.d.ready
invalidate controlXingIn.a.bits.corrupt
invalidate controlXingIn.a.bits.data
invalidate controlXingIn.a.bits.mask
invalidate controlXingIn.a.bits.address
invalidate controlXingIn.a.bits.source
invalidate controlXingIn.a.bits.size
invalidate controlXingIn.a.bits.param
invalidate controlXingIn.a.bits.opcode
invalidate controlXingIn.a.valid
invalidate controlXingIn.a.ready
connect controlXingOut, controlXingIn
wire intXingOut : { sync : UInt<1>[1]}
invalidate intXingOut.sync[0]
wire intXingIn : { sync : UInt<1>[1]}
invalidate intXingIn.sync[0]
connect intXingOut, intXingIn
connect intsource.auto.in[0], intnodeOut[0]
connect buffer.auto.out.d, controlNodeIn.d
connect controlNodeIn.a.bits, buffer.auto.out.a.bits
connect controlNodeIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, controlNodeIn.a.ready
connect buffer.auto.in, controlXingOut
connect intXingIn, intsource.auto.out
connect auto.io_out, ioNodeOut
connect controlXingIn, auto.control_xing_in
connect auto.int_xing_out, intXingOut
inst txm of UARTTx
connect txm.clock, clock
connect txm.reset, reset
inst txq of Queue8_UInt8
connect txq.clock, clock
connect txq.reset, reset
inst rxm of UARTRx
connect rxm.clock, clock
connect rxm.reset, reset
inst rxq of Queue8_UInt8_1
connect rxq.clock, clock
connect rxq.reset, reset
regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4)
regreset txen : UInt<1>, clock, reset, UInt<1>(0h0)
regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0)
regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0)
regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset parity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset errie : UInt<1>, clock, reset, UInt<1>(0h0)
regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0)
regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0)
regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0)
regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1)
connect txm.io.en, txen
connect txm.io.in, txq.io.deq
connect txm.io.div, div
connect txm.io.nstop, nstop
connect ioNodeOut.txd, txm.io.out
connect rxm.io.en, rxen
connect rxm.io.in, ioNodeOut.rxd
connect rxq.io.enq.valid, rxm.io.out.valid
connect rxq.io.enq.bits, rxm.io.out.bits
connect rxm.io.div, div
node _tx_busy_T = orr(txq.io.count)
node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T)
node tx_busy = and(_tx_busy_T_1, txen)
wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>}
connect _ie_WIRE.txwm, UInt<1>(0h0)
connect _ie_WIRE.rxwm, UInt<1>(0h0)
regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE
wire ip : { rxwm : UInt<1>, txwm : UInt<1>}
node _ip_txwm_T = lt(txq.io.count, txwm)
connect ip.txwm, _ip_txwm_T
node _ip_rxwm_T = gt(rxq.io.count, rxwm)
connect ip.rxwm, _ip_rxwm_T
node _intnodeOut_0_T = and(ip.txwm, ie.txwm)
node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm)
node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1)
connect intnodeOut[0], _intnodeOut_0_T_2
wire quash : UInt<1>
node _T = eq(txq.io.enq.ready, UInt<1>(0h0))
node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0))
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, controlNodeIn.a.bits.data
connect in.bits.mask, controlNodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h3))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
node _out_T_2 = eq(out_findex, UInt<9>(0h0))
node _out_T_3 = eq(out_bindex, UInt<9>(0h0))
node _out_T_4 = eq(out_findex, UInt<9>(0h0))
node _out_T_5 = eq(out_bindex, UInt<9>(0h0))
node _out_T_6 = eq(out_findex, UInt<9>(0h0))
node _out_T_7 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[16]
wire out_wivalid : UInt<1>[16]
wire out_roready : UInt<1>[16]
wire out_woready : UInt<1>[16]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 7, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 7, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 7, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 7, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_8 = bits(out_front.bits.data, 7, 0)
node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0))
node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T)
connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1
connect txq.io.enq.bits, _out_T_8
node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1))
node _out_T_10 = and(UInt<1>(0h1), out_f_woready)
node _out_T_11 = eq(out_rimask, UInt<1>(0h0))
node _out_T_12 = eq(out_wimask, UInt<1>(0h0))
node _out_T_13 = eq(out_romask, UInt<1>(0h0))
node _out_T_14 = eq(out_womask, UInt<1>(0h0))
node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0))
node _out_T_16 = bits(_out_T_15, 7, 0)
node _out_rimask_T_1 = bits(out_frontMask, 30, 8)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 30, 8)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 30, 8)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 30, 8)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_17 = bits(out_front.bits.data, 30, 8)
node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1))
node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1)
node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_22 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_23 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_16, UInt<8>(0h0))
node out_prepend = cat(UInt<1>(0h0), _out_prepend_T)
node _out_T_24 = or(out_prepend, UInt<31>(0h0))
node _out_T_25 = bits(_out_T_24, 30, 0)
node _out_rimask_T_2 = bits(out_frontMask, 31, 31)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 31, 31)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 31, 31)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 31, 31)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_26 = bits(out_front.bits.data, 31, 31)
node _out_quash_T = bits(_out_T_26, 0, 0)
node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T)
connect quash, _out_quash_T_1
node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1))
node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2)
node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_31 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_32 = eq(out_womask_2, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0))
node out_prepend_1 = cat(_T, _out_prepend_T_1)
node _out_T_33 = or(out_prepend_1, UInt<32>(0h0))
node _out_T_34 = bits(_out_T_33, 31, 0)
node _out_rimask_T_3 = bits(out_frontMask, 39, 32)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 39, 32)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 39, 32)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 39, 32)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
connect rxq.io.deq.ready, out_f_roready_3
node _out_T_35 = bits(out_front.bits.data, 39, 32)
node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1))
node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3)
node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_40 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_41 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0))
node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2)
node _out_T_42 = or(out_prepend_2, UInt<40>(0h0))
node _out_T_43 = bits(_out_T_42, 39, 0)
node _out_rimask_T_4 = bits(out_frontMask, 62, 40)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 62, 40)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 62, 40)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 62, 40)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
node _out_T_44 = bits(out_front.bits.data, 62, 40)
node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1))
node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4)
node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_49 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_50 = eq(out_womask_4, UInt<1>(0h0))
node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0))
node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3)
node _out_T_51 = or(out_prepend_3, UInt<63>(0h0))
node _out_T_52 = bits(_out_T_51, 62, 0)
node _out_rimask_T_5 = bits(out_frontMask, 63, 63)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 63, 63)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 63, 63)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 63, 63)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_53 = bits(out_front.bits.data, 63, 63)
node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1))
node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5)
node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_58 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_59 = eq(out_womask_5, UInt<1>(0h0))
node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0))
node out_prepend_4 = cat(_T_1, _out_prepend_T_4)
node _out_T_60 = or(out_prepend_4, UInt<64>(0h0))
node _out_T_61 = bits(_out_T_60, 63, 0)
node _out_rimask_T_6 = bits(out_frontMask, 0, 0)
node out_rimask_6 = orr(_out_rimask_T_6)
node _out_wimask_T_6 = bits(out_frontMask, 0, 0)
node out_wimask_6 = andr(_out_wimask_T_6)
node _out_romask_T_6 = bits(out_backMask, 0, 0)
node out_romask_6 = orr(_out_romask_T_6)
node _out_womask_T_6 = bits(out_backMask, 0, 0)
node out_womask_6 = andr(_out_womask_T_6)
node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6)
node out_f_roready_6 = and(out_roready[6], out_romask_6)
node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6)
node out_f_woready_6 = and(out_woready[6], out_womask_6)
node _out_T_62 = bits(out_front.bits.data, 0, 0)
when out_f_woready_6 :
connect txen, _out_T_62
node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1))
node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6)
node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1))
node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6)
node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0))
node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0))
node _out_T_69 = eq(out_romask_6, UInt<1>(0h0))
node _out_T_70 = eq(out_womask_6, UInt<1>(0h0))
node _out_T_71 = or(txen, UInt<1>(0h0))
node _out_T_72 = bits(_out_T_71, 0, 0)
node _out_rimask_T_7 = bits(out_frontMask, 1, 1)
node out_rimask_7 = orr(_out_rimask_T_7)
node _out_wimask_T_7 = bits(out_frontMask, 1, 1)
node out_wimask_7 = andr(_out_wimask_T_7)
node _out_romask_T_7 = bits(out_backMask, 1, 1)
node out_romask_7 = orr(_out_romask_T_7)
node _out_womask_T_7 = bits(out_backMask, 1, 1)
node out_womask_7 = andr(_out_womask_T_7)
node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7)
node out_f_roready_7 = and(out_roready[7], out_romask_7)
node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7)
node out_f_woready_7 = and(out_woready[7], out_womask_7)
node _out_T_73 = bits(out_front.bits.data, 1, 1)
when out_f_woready_7 :
connect nstop, _out_T_73
node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1))
node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7)
node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1))
node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7)
node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0))
node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0))
node _out_T_80 = eq(out_romask_7, UInt<1>(0h0))
node _out_T_81 = eq(out_womask_7, UInt<1>(0h0))
node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0))
node out_prepend_5 = cat(nstop, _out_prepend_T_5)
node _out_T_82 = or(out_prepend_5, UInt<2>(0h0))
node _out_T_83 = bits(_out_T_82, 1, 0)
node _out_rimask_T_8 = bits(out_frontMask, 19, 16)
node out_rimask_8 = orr(_out_rimask_T_8)
node _out_wimask_T_8 = bits(out_frontMask, 19, 16)
node out_wimask_8 = andr(_out_wimask_T_8)
node _out_romask_T_8 = bits(out_backMask, 19, 16)
node out_romask_8 = orr(_out_romask_T_8)
node _out_womask_T_8 = bits(out_backMask, 19, 16)
node out_womask_8 = andr(_out_womask_T_8)
node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8)
node out_f_roready_8 = and(out_roready[8], out_romask_8)
node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8)
node out_f_woready_8 = and(out_woready[8], out_womask_8)
node _out_T_84 = bits(out_front.bits.data, 19, 16)
when out_f_woready_8 :
connect txwm, _out_T_84
node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1))
node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8)
node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1))
node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8)
node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0))
node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0))
node _out_T_91 = eq(out_romask_8, UInt<1>(0h0))
node _out_T_92 = eq(out_womask_8, UInt<1>(0h0))
node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0))
node out_prepend_6 = cat(txwm, _out_prepend_T_6)
node _out_T_93 = or(out_prepend_6, UInt<20>(0h0))
node _out_T_94 = bits(_out_T_93, 19, 0)
node _out_rimask_T_9 = bits(out_frontMask, 32, 32)
node out_rimask_9 = orr(_out_rimask_T_9)
node _out_wimask_T_9 = bits(out_frontMask, 32, 32)
node out_wimask_9 = andr(_out_wimask_T_9)
node _out_romask_T_9 = bits(out_backMask, 32, 32)
node out_romask_9 = orr(_out_romask_T_9)
node _out_womask_T_9 = bits(out_backMask, 32, 32)
node out_womask_9 = andr(_out_womask_T_9)
node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9)
node out_f_roready_9 = and(out_roready[9], out_romask_9)
node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9)
node out_f_woready_9 = and(out_woready[9], out_womask_9)
node _out_T_95 = bits(out_front.bits.data, 32, 32)
when out_f_woready_9 :
connect rxen, _out_T_95
node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1))
node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9)
node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1))
node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9)
node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0))
node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0))
node _out_T_102 = eq(out_romask_9, UInt<1>(0h0))
node _out_T_103 = eq(out_womask_9, UInt<1>(0h0))
node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0))
node out_prepend_7 = cat(rxen, _out_prepend_T_7)
node _out_T_104 = or(out_prepend_7, UInt<33>(0h0))
node _out_T_105 = bits(_out_T_104, 32, 0)
node _out_rimask_T_10 = bits(out_frontMask, 51, 48)
node out_rimask_10 = orr(_out_rimask_T_10)
node _out_wimask_T_10 = bits(out_frontMask, 51, 48)
node out_wimask_10 = andr(_out_wimask_T_10)
node _out_romask_T_10 = bits(out_backMask, 51, 48)
node out_romask_10 = orr(_out_romask_T_10)
node _out_womask_T_10 = bits(out_backMask, 51, 48)
node out_womask_10 = andr(_out_womask_T_10)
node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10)
node out_f_roready_10 = and(out_roready[10], out_romask_10)
node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10)
node out_f_woready_10 = and(out_woready[10], out_womask_10)
node _out_T_106 = bits(out_front.bits.data, 51, 48)
when out_f_woready_10 :
connect rxwm, _out_T_106
node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1))
node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10)
node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1))
node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10)
node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0))
node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0))
node _out_T_113 = eq(out_romask_10, UInt<1>(0h0))
node _out_T_114 = eq(out_womask_10, UInt<1>(0h0))
node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0))
node out_prepend_8 = cat(rxwm, _out_prepend_T_8)
node _out_T_115 = or(out_prepend_8, UInt<52>(0h0))
node _out_T_116 = bits(_out_T_115, 51, 0)
node _out_rimask_T_11 = bits(out_frontMask, 0, 0)
node out_rimask_11 = orr(_out_rimask_T_11)
node _out_wimask_T_11 = bits(out_frontMask, 0, 0)
node out_wimask_11 = andr(_out_wimask_T_11)
node _out_romask_T_11 = bits(out_backMask, 0, 0)
node out_romask_11 = orr(_out_romask_T_11)
node _out_womask_T_11 = bits(out_backMask, 0, 0)
node out_womask_11 = andr(_out_womask_T_11)
node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11)
node out_f_roready_11 = and(out_roready[11], out_romask_11)
node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11)
node out_f_woready_11 = and(out_woready[11], out_womask_11)
node _out_T_117 = bits(out_front.bits.data, 0, 0)
when out_f_woready_11 :
connect ie.txwm, _out_T_117
node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1))
node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11)
node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1))
node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11)
node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0))
node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0))
node _out_T_124 = eq(out_romask_11, UInt<1>(0h0))
node _out_T_125 = eq(out_womask_11, UInt<1>(0h0))
node _out_T_126 = or(ie.txwm, UInt<1>(0h0))
node _out_T_127 = bits(_out_T_126, 0, 0)
node _out_rimask_T_12 = bits(out_frontMask, 1, 1)
node out_rimask_12 = orr(_out_rimask_T_12)
node _out_wimask_T_12 = bits(out_frontMask, 1, 1)
node out_wimask_12 = andr(_out_wimask_T_12)
node _out_romask_T_12 = bits(out_backMask, 1, 1)
node out_romask_12 = orr(_out_romask_T_12)
node _out_womask_T_12 = bits(out_backMask, 1, 1)
node out_womask_12 = andr(_out_womask_T_12)
node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12)
node out_f_roready_12 = and(out_roready[12], out_romask_12)
node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12)
node out_f_woready_12 = and(out_woready[12], out_womask_12)
node _out_T_128 = bits(out_front.bits.data, 1, 1)
when out_f_woready_12 :
connect ie.rxwm, _out_T_128
node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1))
node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12)
node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1))
node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12)
node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0))
node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0))
node _out_T_135 = eq(out_romask_12, UInt<1>(0h0))
node _out_T_136 = eq(out_womask_12, UInt<1>(0h0))
node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0))
node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9)
node _out_T_137 = or(out_prepend_9, UInt<2>(0h0))
node _out_T_138 = bits(_out_T_137, 1, 0)
node _out_rimask_T_13 = bits(out_frontMask, 32, 32)
node out_rimask_13 = orr(_out_rimask_T_13)
node _out_wimask_T_13 = bits(out_frontMask, 32, 32)
node out_wimask_13 = andr(_out_wimask_T_13)
node _out_romask_T_13 = bits(out_backMask, 32, 32)
node out_romask_13 = orr(_out_romask_T_13)
node _out_womask_T_13 = bits(out_backMask, 32, 32)
node out_womask_13 = andr(_out_womask_T_13)
node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13)
node out_f_roready_13 = and(out_roready[13], out_romask_13)
node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13)
node out_f_woready_13 = and(out_woready[13], out_womask_13)
node _out_T_139 = bits(out_front.bits.data, 32, 32)
node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1))
node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13)
node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0))
node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0))
node _out_T_144 = eq(out_romask_13, UInt<1>(0h0))
node _out_T_145 = eq(out_womask_13, UInt<1>(0h0))
node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0))
node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10)
node _out_T_146 = or(out_prepend_10, UInt<33>(0h0))
node _out_T_147 = bits(_out_T_146, 32, 0)
node _out_rimask_T_14 = bits(out_frontMask, 33, 33)
node out_rimask_14 = orr(_out_rimask_T_14)
node _out_wimask_T_14 = bits(out_frontMask, 33, 33)
node out_wimask_14 = andr(_out_wimask_T_14)
node _out_romask_T_14 = bits(out_backMask, 33, 33)
node out_romask_14 = orr(_out_romask_T_14)
node _out_womask_T_14 = bits(out_backMask, 33, 33)
node out_womask_14 = andr(_out_womask_T_14)
node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14)
node out_f_roready_14 = and(out_roready[14], out_romask_14)
node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14)
node out_f_woready_14 = and(out_woready[14], out_womask_14)
node _out_T_148 = bits(out_front.bits.data, 33, 33)
node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1))
node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14)
node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0))
node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0))
node _out_T_153 = eq(out_romask_14, UInt<1>(0h0))
node _out_T_154 = eq(out_womask_14, UInt<1>(0h0))
node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0))
node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11)
node _out_T_155 = or(out_prepend_11, UInt<34>(0h0))
node _out_T_156 = bits(_out_T_155, 33, 0)
node _out_rimask_T_15 = bits(out_frontMask, 15, 0)
node out_rimask_15 = orr(_out_rimask_T_15)
node _out_wimask_T_15 = bits(out_frontMask, 15, 0)
node out_wimask_15 = andr(_out_wimask_T_15)
node _out_romask_T_15 = bits(out_backMask, 15, 0)
node out_romask_15 = orr(_out_romask_T_15)
node _out_womask_T_15 = bits(out_backMask, 15, 0)
node out_womask_15 = andr(_out_womask_T_15)
node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15)
node out_f_roready_15 = and(out_roready[15], out_romask_15)
node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15)
node out_f_woready_15 = and(out_woready[15], out_womask_15)
node _out_T_157 = bits(out_front.bits.data, 15, 0)
when out_f_woready_15 :
connect div, _out_T_157
node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1))
node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15)
node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1))
node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15)
node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0))
node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0))
node _out_T_164 = eq(out_romask_15, UInt<1>(0h0))
node _out_T_165 = eq(out_womask_15, UInt<1>(0h0))
node _out_T_166 = or(div, UInt<16>(0h0))
node _out_T_167 = bits(_out_T_166, 15, 0)
node _out_iindex_T = bits(out_front.bits.index, 0, 0)
node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_iindex = cat(_out_iindex_T_1, _out_iindex_T)
node _out_oindex_T = bits(out_front.bits.index, 0, 0)
node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_oindex = cat(_out_oindex_T_1, _out_oindex_T)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node out_frontSel_2 = bits(_out_frontSel_T, 2, 2)
node out_frontSel_3 = bits(_out_frontSel_T, 3, 3)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node out_backSel_2 = bits(_out_backSel_T, 2, 2)
node out_backSel_3 = bits(_out_backSel_T, 3, 3)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[5], _out_rifireMux_T_3
connect out_rivalid[4], _out_rifireMux_T_3
connect out_rivalid[3], _out_rifireMux_T_3
connect out_rivalid[2], _out_rifireMux_T_3
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2)
connect out_rifireMux_out_1, UInt<1>(0h1)
connect out_rivalid[10], _out_rifireMux_T_7
connect out_rivalid[9], _out_rifireMux_T_7
connect out_rivalid[8], _out_rifireMux_T_7
connect out_rivalid[7], _out_rifireMux_T_7
connect out_rivalid[6], _out_rifireMux_T_7
node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
wire out_rifireMux_out_2 : UInt<1>
node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2)
node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4)
connect out_rifireMux_out_2, UInt<1>(0h1)
connect out_rivalid[14], _out_rifireMux_T_11
connect out_rivalid[13], _out_rifireMux_T_11
connect out_rivalid[12], _out_rifireMux_T_11
connect out_rivalid[11], _out_rifireMux_T_11
node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0))
node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12)
wire out_rifireMux_out_3 : UInt<1>
node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3)
node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6)
connect out_rifireMux_out_3, UInt<1>(0h1)
connect out_rivalid[15], _out_rifireMux_T_15
node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0))
node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16)
node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4))
wire _out_rifireMux_WIRE : UInt<1>[4]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13
connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17
node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[5], _out_wifireMux_T_4
connect out_wivalid[4], _out_wifireMux_T_4
connect out_wivalid[3], _out_wifireMux_T_4
connect out_wivalid[2], _out_wifireMux_T_4
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2)
connect out_wifireMux_out_1, UInt<1>(0h1)
connect out_wivalid[10], _out_wifireMux_T_8
connect out_wivalid[9], _out_wifireMux_T_8
connect out_wivalid[8], _out_wifireMux_T_8
connect out_wivalid[7], _out_wifireMux_T_8
connect out_wivalid[6], _out_wifireMux_T_8
node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
wire out_wifireMux_out_2 : UInt<1>
node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2)
node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4)
connect out_wifireMux_out_2, UInt<1>(0h1)
connect out_wivalid[14], _out_wifireMux_T_12
connect out_wivalid[13], _out_wifireMux_T_12
connect out_wivalid[12], _out_wifireMux_T_12
connect out_wivalid[11], _out_wifireMux_T_12
node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0))
node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13)
wire out_wifireMux_out_3 : UInt<1>
node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3)
node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6)
connect out_wifireMux_out_3, UInt<1>(0h1)
connect out_wivalid[15], _out_wifireMux_T_16
node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0))
node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17)
node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4))
wire _out_wifireMux_WIRE : UInt<1>[4]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14
connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18
node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[5], _out_rofireMux_T_3
connect out_roready[4], _out_rofireMux_T_3
connect out_roready[3], _out_rofireMux_T_3
connect out_roready[2], _out_rofireMux_T_3
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3)
connect out_rofireMux_out_1, UInt<1>(0h1)
connect out_roready[10], _out_rofireMux_T_7
connect out_roready[9], _out_rofireMux_T_7
connect out_roready[8], _out_rofireMux_T_7
connect out_roready[7], _out_rofireMux_T_7
connect out_roready[6], _out_rofireMux_T_7
node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
wire out_rofireMux_out_2 : UInt<1>
node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2)
node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5)
connect out_rofireMux_out_2, UInt<1>(0h1)
connect out_roready[14], _out_rofireMux_T_11
connect out_roready[13], _out_rofireMux_T_11
connect out_roready[12], _out_rofireMux_T_11
connect out_roready[11], _out_rofireMux_T_11
node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0))
node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12)
wire out_rofireMux_out_3 : UInt<1>
node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3)
node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7)
connect out_rofireMux_out_3, UInt<1>(0h1)
connect out_roready[15], _out_rofireMux_T_15
node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0))
node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16)
node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4))
wire _out_rofireMux_WIRE : UInt<1>[4]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13
connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17
node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[5], _out_wofireMux_T_4
connect out_woready[4], _out_wofireMux_T_4
connect out_woready[3], _out_wofireMux_T_4
connect out_woready[2], _out_wofireMux_T_4
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3)
connect out_wofireMux_out_1, UInt<1>(0h1)
connect out_woready[10], _out_wofireMux_T_8
connect out_woready[9], _out_wofireMux_T_8
connect out_woready[8], _out_wofireMux_T_8
connect out_woready[7], _out_wofireMux_T_8
connect out_woready[6], _out_wofireMux_T_8
node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
wire out_wofireMux_out_2 : UInt<1>
node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2)
node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5)
connect out_wofireMux_out_2, UInt<1>(0h1)
connect out_woready[14], _out_wofireMux_T_12
connect out_woready[13], _out_wofireMux_T_12
connect out_woready[12], _out_wofireMux_T_12
connect out_woready[11], _out_wofireMux_T_12
node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0))
node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13)
wire out_wofireMux_out_3 : UInt<1>
node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3)
node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7)
connect out_wofireMux_out_3, UInt<1>(0h1)
connect out_woready[15], _out_wofireMux_T_16
node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0))
node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17)
node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4))
wire _out_wofireMux_WIRE : UInt<1>[4]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14
connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18
node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE : UInt<1>[4]
connect _out_out_bits_data_WIRE[0], _out_T_1
connect _out_out_bits_data_WIRE[1], _out_T_3
connect _out_out_bits_data_WIRE[2], _out_T_5
connect _out_out_bits_data_WIRE[3], _out_T_7
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE_1 : UInt<64>[4]
connect _out_out_bits_data_WIRE_1[0], _out_T_61
connect _out_out_bits_data_WIRE_1[1], _out_T_116
connect _out_out_bits_data_WIRE_1[2], _out_T_156
connect _out_out_bits_data_WIRE_1[3], _out_T_167
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, controlNodeIn.a.valid
connect controlNodeIn.a.ready, in.ready
connect controlNodeIn.d.valid, out.valid
connect out.ready, controlNodeIn.d.ready
wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.param, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate controlNodeIn_d_bits_d.data
connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt
connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data
connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied
connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink
connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source
connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size
connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param
connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode
connect controlNodeIn.d.bits.data, out.bits.data
node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLUART( // @[UART.scala:127:25]
input clock, // @[UART.scala:127:25]
input reset, // @[UART.scala:127:25]
output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_io_out_txd, // @[LazyModuleImp.scala:107:25]
input auto_io_out_rxd // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [10:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire _rxq_io_deq_valid; // @[UART.scala:133:19]
wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19]
wire [3:0] _rxq_io_count; // @[UART.scala:133:19]
wire _rxm_io_out_valid; // @[UART.scala:132:19]
wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19]
wire _txq_io_enq_ready; // @[UART.scala:130:19]
wire _txq_io_deq_valid; // @[UART.scala:130:19]
wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19]
wire [3:0] _txq_io_count; // @[UART.scala:130:19]
wire _txm_io_in_ready; // @[UART.scala:129:19]
wire _txm_io_tx_busy; // @[UART.scala:129:19]
wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25]
wire [10:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25]
wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25]
wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25]
wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25]
wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25]
wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25]
wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25]
wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32]
wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25]
wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire controlXingIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25]
wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25]
wire [10:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25]
wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25]
wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25]
wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25]
wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25]
wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25]
wire controlXingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire ioNodeOut_txd; // @[MixedNode.scala:542:17]
wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25]
wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
wire [10:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
wire auto_io_out_txd_0; // @[UART.scala:127:25]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [10:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlXingOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [10:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [10:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [10:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25]
wire _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9]
wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9]
wire [10:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9]
assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25]
assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
reg [15:0] div; // @[UART.scala:135:20]
wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24]
reg txen; // @[UART.scala:141:21]
wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24]
reg rxen; // @[UART.scala:142:21]
reg [3:0] txwm; // @[UART.scala:149:21]
reg [3:0] rxwm; // @[UART.scala:150:21]
reg nstop; // @[UART.scala:151:22]
wire _tx_busy_T = |_txq_io_count; // @[UART.scala:130:19, :175:49]
wire _tx_busy_T_1 = _txm_io_tx_busy | _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}]
wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}]
reg ie_rxwm; // @[UART.scala:186:19]
reg ie_txwm; // @[UART.scala:186:19]
wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24]
wire _ip_rxwm_T; // @[UART.scala:190:28]
wire _ip_txwm_T; // @[UART.scala:189:28]
wire ip_rxwm; // @[UART.scala:187:16]
wire ip_txwm; // @[UART.scala:187:16]
assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28]
assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28]
assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28]
assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28]
wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29]
wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53]
assign _intnodeOut_0_T_2 = _intnodeOut_0_T | _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}]
assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26]
wire quash; // @[RegMapFIFO.scala:11:21]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33]
wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24]
wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24]
assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24]
assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26]
wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48]
wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24]
wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24]
wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24]
wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48]
wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
always @(posedge clock) begin // @[UART.scala:127:25]
if (reset) begin // @[UART.scala:127:25]
div <= 16'h10F4; // @[UART.scala:135:20]
txen <= 1'h0; // @[UART.scala:141:21]
rxen <= 1'h0; // @[UART.scala:142:21]
txwm <= 4'h0; // @[UART.scala:149:21]
rxwm <= 4'h0; // @[UART.scala:150:21]
nstop <= 1'h0; // @[UART.scala:151:22]
ie_rxwm <= 1'h0; // @[UART.scala:186:19]
ie_txwm <= 1'h0; // @[UART.scala:186:19]
end
else begin // @[UART.scala:127:25]
if (out_f_woready_15) // @[RegisterRouter.scala:87:24]
div <= _out_T_157; // @[RegisterRouter.scala:87:24]
if (out_f_woready_6) // @[RegisterRouter.scala:87:24]
txen <= _out_T_62; // @[RegisterRouter.scala:87:24]
if (out_f_woready_9) // @[RegisterRouter.scala:87:24]
rxen <= _out_T_95; // @[RegisterRouter.scala:87:24]
if (out_f_woready_8) // @[RegisterRouter.scala:87:24]
txwm <= _out_T_84; // @[RegisterRouter.scala:87:24]
if (out_f_woready_10) // @[RegisterRouter.scala:87:24]
rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24]
if (out_f_woready_7) // @[RegisterRouter.scala:87:24]
nstop <= _out_T_73; // @[RegisterRouter.scala:87:24]
if (out_f_woready_12) // @[RegisterRouter.scala:87:24]
ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24]
if (out_f_woready_11) // @[RegisterRouter.scala:87:24]
ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24]
end
always @(posedge)
IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31]
.clock (clock),
.reset (reset),
.auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17]
.auto_out_sync_0 (intXingIn_sync_0)
); // @[Crossing.scala:29:31]
TLMonitor_54 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
UARTTx txm ( // @[UART.scala:129:19]
.clock (clock),
.reset (reset),
.io_en (txen), // @[UART.scala:141:21]
.io_in_ready (_txm_io_in_ready),
.io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19]
.io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19]
.io_out (ioNodeOut_txd),
.io_div (div), // @[UART.scala:135:20]
.io_nstop (nstop), // @[UART.scala:151:22]
.io_tx_busy (_txm_io_tx_busy)
); // @[UART.scala:129:19]
Queue8_UInt8 txq ( // @[UART.scala:130:19]
.clock (clock),
.reset (reset),
.io_enq_ready (_txq_io_enq_ready),
.io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30]
.io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19]
.io_deq_valid (_txq_io_deq_valid),
.io_deq_bits (_txq_io_deq_bits),
.io_count (_txq_io_count)
); // @[UART.scala:130:19]
UARTRx rxm ( // @[UART.scala:132:19]
.clock (clock),
.reset (reset),
.io_en (rxen), // @[UART.scala:142:21]
.io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17]
.io_out_valid (_rxm_io_out_valid),
.io_out_bits (_rxm_io_out_bits),
.io_div (div) // @[UART.scala:135:20]
); // @[UART.scala:132:19]
Queue8_UInt8_1 rxq ( // @[UART.scala:133:19]
.clock (clock),
.reset (reset),
.io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19]
.io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19]
.io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_rxq_io_deq_valid),
.io_deq_bits (_rxq_io_deq_bits),
.io_count (_rxq_io_count)
); // @[UART.scala:133:19]
assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_457 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_457( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_PTE :
input clock : Clock
input reset : Reset
output io : { flip x : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, y : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_PTE( // @[package.scala:267:30]
input [43:0] io_x_ppn, // @[package.scala:268:18]
input io_x_d, // @[package.scala:268:18]
input io_x_a, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_x, // @[package.scala:268:18]
input io_x_w, // @[package.scala:268:18]
input io_x_r, // @[package.scala:268:18]
input io_x_v, // @[package.scala:268:18]
output [43:0] io_y_ppn, // @[package.scala:268:18]
output io_y_d, // @[package.scala:268:18]
output io_y_a, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_x, // @[package.scala:268:18]
output io_y_w, // @[package.scala:268:18]
output io_y_r, // @[package.scala:268:18]
output io_y_v // @[package.scala:268:18]
);
assign io_y_ppn = io_x_ppn; // @[package.scala:267:30]
assign io_y_d = io_x_d; // @[package.scala:267:30]
assign io_y_a = io_x_a; // @[package.scala:267:30]
assign io_y_g = io_x_g; // @[package.scala:267:30]
assign io_y_u = io_x_u; // @[package.scala:267:30]
assign io_y_x = io_x_x; // @[package.scala:267:30]
assign io_y_w = io_x_w; // @[package.scala:267:30]
assign io_y_r = io_x_r; // @[package.scala:267:30]
assign io_y_v = io_x_v; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_199 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_199( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_12 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_45 = and(_T_43, _T_44)
node _T_46 = or(_T_17, _T_24)
node _T_47 = or(_T_46, _T_31)
node _T_48 = or(_T_47, _T_38)
node _T_49 = or(_T_48, _T_45)
node _T_50 = or(_T_10, _T_49)
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_50, UInt<1>(0h1), "") : assert_2
node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_61, _T_68)
node _T_91 = or(_T_90, _T_75)
node _T_92 = or(_T_91, _T_82)
node _T_93 = or(_T_92, _T_89)
node _T_94 = or(_T_54, _T_93)
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_94, UInt<1>(0h1), "") : assert_3
node _T_98 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_105 = and(_T_103, _T_104)
node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_112 = and(_T_110, _T_111)
node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_161 = and(_T_159, _T_160)
node _T_162 = or(_T_105, _T_112)
node _T_163 = or(_T_162, _T_119)
node _T_164 = or(_T_163, _T_126)
node _T_165 = or(_T_164, _T_133)
node _T_166 = or(_T_165, _T_140)
node _T_167 = or(_T_166, _T_147)
node _T_168 = or(_T_167, _T_154)
node _T_169 = or(_T_168, _T_161)
node _T_170 = or(_T_98, _T_169)
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_170, UInt<1>(0h1), "") : assert_4
node _T_174 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_176 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_179 = and(_T_177, _T_178)
node _T_180 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_183 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_190 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_193 = and(_T_191, _T_192)
node _T_194 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_197 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_200 = and(_T_198, _T_199)
node _T_201 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_204 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_230 = and(_T_228, _T_229)
node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_232 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_235 = and(_T_233, _T_234)
node _T_236 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_237 = and(_T_235, _T_236)
node _T_238 = or(_T_181, _T_188)
node _T_239 = or(_T_238, _T_195)
node _T_240 = or(_T_239, _T_202)
node _T_241 = or(_T_240, _T_209)
node _T_242 = or(_T_241, _T_216)
node _T_243 = or(_T_242, _T_223)
node _T_244 = or(_T_243, _T_230)
node _T_245 = or(_T_244, _T_237)
node _T_246 = or(_T_174, _T_245)
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_246, UInt<1>(0h1), "") : assert_5
node _T_250 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_313 = and(_T_311, _T_312)
node _T_314 = or(_T_257, _T_264)
node _T_315 = or(_T_314, _T_271)
node _T_316 = or(_T_315, _T_278)
node _T_317 = or(_T_316, _T_285)
node _T_318 = or(_T_317, _T_292)
node _T_319 = or(_T_318, _T_299)
node _T_320 = or(_T_319, _T_306)
node _T_321 = or(_T_320, _T_313)
node _T_322 = or(_T_250, _T_321)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_322, UInt<1>(0h1), "") : assert_6
node _T_326 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_327 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_328 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_329 = and(_T_327, _T_328)
node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_331 = and(_T_329, _T_330)
node _T_332 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_335 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_336 = and(_T_334, _T_335)
node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_338 = and(_T_336, _T_337)
node _T_339 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_342 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_349 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_356 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_363 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_364 = and(_T_362, _T_363)
node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_370 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_371 = and(_T_369, _T_370)
node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_377 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_378 = and(_T_376, _T_377)
node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_384 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_385 = and(_T_383, _T_384)
node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_387 = and(_T_385, _T_386)
node _T_388 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_389 = and(_T_387, _T_388)
node _T_390 = or(_T_333, _T_340)
node _T_391 = or(_T_390, _T_347)
node _T_392 = or(_T_391, _T_354)
node _T_393 = or(_T_392, _T_361)
node _T_394 = or(_T_393, _T_368)
node _T_395 = or(_T_394, _T_375)
node _T_396 = or(_T_395, _T_382)
node _T_397 = or(_T_396, _T_389)
node _T_398 = or(_T_326, _T_397)
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_398, UInt<1>(0h1), "") : assert_7
node _T_402 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_404 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_411 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_414 = and(_T_412, _T_413)
node _T_415 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_418 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_423 = and(_T_421, _T_422)
node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_425 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_430 = and(_T_428, _T_429)
node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_435 = and(_T_433, _T_434)
node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_437 = and(_T_435, _T_436)
node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_449 = and(_T_447, _T_448)
node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_456 = and(_T_454, _T_455)
node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_460 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_461 = and(_T_459, _T_460)
node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_463 = and(_T_461, _T_462)
node _T_464 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(_T_409, _T_416)
node _T_467 = or(_T_466, _T_423)
node _T_468 = or(_T_467, _T_430)
node _T_469 = or(_T_468, _T_437)
node _T_470 = or(_T_469, _T_444)
node _T_471 = or(_T_470, _T_451)
node _T_472 = or(_T_471, _T_458)
node _T_473 = or(_T_472, _T_465)
node _T_474 = or(_T_402, _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_474, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_12( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_37 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
inst input_buffer of InputBuffer_37
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter3_RouteComputerReq_37
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
node _T_11 = and(io.router_req.ready, io.router_req.valid)
when _T_11 :
node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_12, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3]
wire vcalloc_vals : UInt<1>[3]
node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12)
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15)
node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_19 = and(io.router_req.ready, io.router_req.valid)
when _T_19 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_21 = or(_T_20, vcalloc_vals[2])
when _T_21 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = bits(vcalloc_sel, 0, 0)
node _mask_T_7 = bits(vcalloc_sel, 1, 1)
node _mask_T_8 = bits(vcalloc_sel, 2, 2)
node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_9, _mask_T_10)
node _mask_T_13 = or(_mask_T_12, _mask_T_11)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_13
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3]
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4)
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3]
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32
connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[1]
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_12
wire _io_vcalloc_req_bits_WIRE_13 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_13.egress_node_id, _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_13.egress_node, _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57
connect _io_vcalloc_req_bits_WIRE_13.ingress_node_id, _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_62
connect _io_vcalloc_req_bits_WIRE_13.ingress_node, _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_13.vnet_id, _io_vcalloc_req_bits_WIRE_18
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_13
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_22 = bits(vcalloc_sel, 0, 0)
node _T_23 = and(vcalloc_vals[0], _T_22)
node _T_24 = and(_T_23, io.vcalloc_req.ready)
when _T_24 :
connect states[0].g, UInt<3>(0h3)
node _T_25 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_25 :
connect vcalloc_vals[0], UInt<1>(0h1)
connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].vc_sel.`1`[1]
invalidate vcalloc_reqs[2].vc_sel.`1`[2]
invalidate vcalloc_reqs[2].vc_sel.`2`[0]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready)
node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_5
node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_26 :
node _T_27 = bits(vcalloc_sel, 0, 0)
when _T_27 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_28 = bits(vcalloc_sel, 1, 1)
when _T_28 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_29 = bits(vcalloc_sel, 2, 2)
when _T_29 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_94
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1])
node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0])
node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1])
node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0])
node credit_available_hi_2 = cat(states[0].vc_sel.`2`[0], _credit_available_T_1)
node _credit_available_T_2 = cat(credit_available_hi_2, _credit_available_T)
node credit_available_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_3 = cat(credit_available_hi_3, io.out_credit_available.`0`[0])
node credit_available_hi_4 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`1`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`2`[0], _credit_available_T_4)
node _credit_available_T_5 = cat(credit_available_hi_5, _credit_available_T_3)
node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5)
node credit_available = neq(_credit_available_T_6, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_30 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_31 = and(_T_30, input_buffer.io.deq[0].bits.tail)
when _T_31 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0]
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_9
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5)
node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8
node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_10
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _vc_sel_WIRE : UInt<1>[3]
node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4)
node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_7
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_12
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_17
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_4 : UInt<1>[3]
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_22
connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_27
connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6
node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_32
connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7
connect vc_sel.`1`, _vc_sel_WIRE_4
wire _vc_sel_WIRE_8 : UInt<1>[1]
node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_37
connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9
connect vc_sel.`2`, _vc_sel_WIRE_8
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2])
node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0])
node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2)
node virt_channel_lo = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1])
node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0])
node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2)
node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0)
node _virt_channel_T_6 = orr(virt_channel_hi_3)
node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1)
node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1)
node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8)
node _virt_channel_T_10 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_11 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0))
node _virt_channel_T_12 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_13 = or(_virt_channel_T_10, _virt_channel_T_11)
node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_12)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_14
node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_32 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4)
node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5)
wire _salloc_outs_0_flit_payload_WIRE : UInt<145>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4)
node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4)
node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4)
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[0], UInt<1>(0h0)
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[2], UInt<1>(0h0)
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].g
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].vc_sel.`1`[1]
invalidate states[2].vc_sel.`1`[2]
invalidate states[2].vc_sel.`2`[0]
invalidate states[2].g
node _T_33 = asUInt(reset)
when _T_33 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0) | module InputUnit_37( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [2:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_121 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_135
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_121( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_135 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_118 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_133
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_118( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_133 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module GenericDeserializer_TLBeatw88_f32_3 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}, busy : UInt<1>}
reg data : UInt<32>[2], clock
regreset beat : UInt<2>, clock, reset, UInt<2>(0h0)
node _io_in_ready_T = neq(beat, UInt<2>(0h2))
node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T)
connect io.in.ready, _io_in_ready_T_1
node _io_out_valid_T = eq(beat, UInt<2>(0h2))
node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T)
connect io.out.valid, _io_out_valid_T_1
node _io_out_bits_T = cat(data[1], data[0])
node _io_out_bits_T_1 = cat(io.in.bits.flit, _io_out_bits_T)
wire _io_out_bits_WIRE : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}
wire _io_out_bits_WIRE_1 : UInt<88>
connect _io_out_bits_WIRE_1, _io_out_bits_T_1
node _io_out_bits_T_2 = bits(_io_out_bits_WIRE_1, 0, 0)
connect _io_out_bits_WIRE.tail, _io_out_bits_T_2
node _io_out_bits_T_3 = bits(_io_out_bits_WIRE_1, 1, 1)
connect _io_out_bits_WIRE.head, _io_out_bits_T_3
node _io_out_bits_T_4 = bits(_io_out_bits_WIRE_1, 87, 2)
connect _io_out_bits_WIRE.payload, _io_out_bits_T_4
connect io.out.bits, _io_out_bits_WIRE
node _T = and(io.in.ready, io.in.valid)
when _T :
node _beat_T = eq(beat, UInt<2>(0h2))
node _beat_T_1 = add(beat, UInt<1>(0h1))
node _beat_T_2 = tail(_beat_T_1, 1)
node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2)
connect beat, _beat_T_3
node _T_1 = neq(beat, UInt<2>(0h2))
when _T_1 :
node _T_2 = bits(beat, 0, 0)
connect data[_T_2], io.in.bits.flit
node _io_busy_T = neq(beat, UInt<1>(0h0))
connect io.busy, _io_busy_T | module GenericDeserializer_TLBeatw88_f32_3( // @[Serdes.scala:37:7]
input clock, // @[Serdes.scala:37:7]
input reset, // @[Serdes.scala:37:7]
output io_in_ready, // @[Serdes.scala:39:14]
input io_in_valid, // @[Serdes.scala:39:14]
input [31:0] io_in_bits_flit, // @[Serdes.scala:39:14]
input io_out_ready, // @[Serdes.scala:39:14]
output io_out_valid, // @[Serdes.scala:39:14]
output [85:0] io_out_bits_payload, // @[Serdes.scala:39:14]
output io_out_bits_head, // @[Serdes.scala:39:14]
output io_out_bits_tail, // @[Serdes.scala:39:14]
output io_busy // @[Serdes.scala:39:14]
);
wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:37:7]
wire [31:0] io_in_bits_flit_0 = io_in_bits_flit; // @[Serdes.scala:37:7]
wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:37:7]
wire _io_in_ready_T_1; // @[Serdes.scala:51:31]
wire _io_out_valid_T_1; // @[Serdes.scala:52:31]
wire [85:0] _io_out_bits_WIRE_payload; // @[Serdes.scala:56:47]
wire _io_out_bits_WIRE_head; // @[Serdes.scala:56:47]
wire _io_out_bits_WIRE_tail; // @[Serdes.scala:56:47]
wire _io_busy_T; // @[Serdes.scala:68:19]
wire io_in_ready_0; // @[Serdes.scala:37:7]
wire [85:0] io_out_bits_payload_0; // @[Serdes.scala:37:7]
wire io_out_bits_head_0; // @[Serdes.scala:37:7]
wire io_out_bits_tail_0; // @[Serdes.scala:37:7]
wire io_out_valid_0; // @[Serdes.scala:37:7]
wire io_busy_0; // @[Serdes.scala:37:7]
reg [31:0] data_0; // @[Serdes.scala:48:17]
reg [31:0] data_1; // @[Serdes.scala:48:17]
reg [1:0] beat; // @[Serdes.scala:49:21]
wire _io_in_ready_T = beat != 2'h2; // @[Serdes.scala:49:21, :51:39]
assign _io_in_ready_T_1 = io_out_ready_0 | _io_in_ready_T; // @[Serdes.scala:37:7, :51:{31,39}]
assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:37:7, :51:31]
wire _GEN = beat == 2'h2; // @[Serdes.scala:49:21, :52:39]
wire _io_out_valid_T; // @[Serdes.scala:52:39]
assign _io_out_valid_T = _GEN; // @[Serdes.scala:52:39]
wire _beat_T; // @[Serdes.scala:60:22]
assign _beat_T = _GEN; // @[Serdes.scala:52:39, :60:22]
assign _io_out_valid_T_1 = io_in_valid_0 & _io_out_valid_T; // @[Serdes.scala:37:7, :52:{31,39}]
assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:37:7, :52:31]
wire [63:0] _io_out_bits_T = {data_1, data_0}; // @[Serdes.scala:48:17, :56:31]
wire [95:0] _io_out_bits_T_1 = {io_in_bits_flit_0, _io_out_bits_T}; // @[Serdes.scala:37:7, :56:{8,31}]
wire [85:0] _io_out_bits_T_4; // @[Serdes.scala:56:47]
assign io_out_bits_payload_0 = _io_out_bits_WIRE_payload; // @[Serdes.scala:37:7, :56:47]
wire _io_out_bits_T_3; // @[Serdes.scala:56:47]
assign io_out_bits_head_0 = _io_out_bits_WIRE_head; // @[Serdes.scala:37:7, :56:47]
wire _io_out_bits_T_2; // @[Serdes.scala:56:47]
assign io_out_bits_tail_0 = _io_out_bits_WIRE_tail; // @[Serdes.scala:37:7, :56:47]
wire [87:0] _io_out_bits_WIRE_1 = _io_out_bits_T_1[87:0]; // @[Serdes.scala:56:{8,47}]
assign _io_out_bits_T_2 = _io_out_bits_WIRE_1[0]; // @[Serdes.scala:56:47]
assign _io_out_bits_WIRE_tail = _io_out_bits_T_2; // @[Serdes.scala:56:47]
assign _io_out_bits_T_3 = _io_out_bits_WIRE_1[1]; // @[Serdes.scala:56:47]
assign _io_out_bits_WIRE_head = _io_out_bits_T_3; // @[Serdes.scala:56:47]
assign _io_out_bits_T_4 = _io_out_bits_WIRE_1[87:2]; // @[Serdes.scala:56:47]
assign _io_out_bits_WIRE_payload = _io_out_bits_T_4; // @[Serdes.scala:56:47]
wire [2:0] _beat_T_1 = {1'h0, beat} + 3'h1; // @[Serdes.scala:49:21, :60:53]
wire [1:0] _beat_T_2 = _beat_T_1[1:0]; // @[Serdes.scala:60:53]
wire [1:0] _beat_T_3 = _beat_T ? 2'h0 : _beat_T_2; // @[Serdes.scala:60:{16,22,53}]
assign _io_busy_T = |beat; // @[Serdes.scala:49:21, :68:19]
assign io_busy_0 = _io_busy_T; // @[Serdes.scala:37:7, :68:19]
wire _T = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Serdes.scala:37:7]
if (~_T | _GEN | beat[0]) begin // @[Decoupled.scala:51:35]
end
else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47]
data_0 <= io_in_bits_flit_0; // @[Serdes.scala:37:7, :48:17]
if (~_T | _GEN | ~(beat[0])) begin // @[Decoupled.scala:51:35]
end
else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47]
data_1 <= io_in_bits_flit_0; // @[Serdes.scala:37:7, :48:17]
if (reset) // @[Serdes.scala:37:7]
beat <= 2'h0; // @[Serdes.scala:49:21]
else if (_T) // @[Decoupled.scala:51:35]
beat <= _beat_T_3; // @[Serdes.scala:49:21, :60:16]
always @(posedge)
assign io_in_ready = io_in_ready_0; // @[Serdes.scala:37:7]
assign io_out_valid = io_out_valid_0; // @[Serdes.scala:37:7]
assign io_out_bits_payload = io_out_bits_payload_0; // @[Serdes.scala:37:7]
assign io_out_bits_head = io_out_bits_head_0; // @[Serdes.scala:37:7]
assign io_out_bits_tail = io_out_bits_tail_0; // @[Serdes.scala:37:7]
assign io_busy = io_busy_0; // @[Serdes.scala:37:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_11 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_11
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_26
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_11( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_11 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_26 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}}
wire _in_flight_WIRE : UInt<1>[3]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_33 = and(_T_31, _T_32)
node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_47 = and(_T_45, _T_46)
node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_61 = and(_T_59, _T_60)
node _T_62 = or(_T_12, _T_19)
node _T_63 = or(_T_62, _T_26)
node _T_64 = or(_T_63, _T_33)
node _T_65 = or(_T_64, _T_40)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_54)
node _T_68 = or(_T_67, _T_61)
node _T_69 = or(_T_5, _T_68)
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_69, UInt<1>(0h1), "") : assert_1
node _T_73 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_74 = or(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_74, UInt<1>(0h1), "") : assert_2
node _T_78 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_80 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_83 = and(_T_81, _T_82)
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_87 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_90 = and(_T_88, _T_89)
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_94 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_97 = and(_T_95, _T_96)
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_101 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_102 = and(_T_100, _T_101)
node _T_103 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_104 = and(_T_102, _T_103)
node _T_105 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_108 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_109 = and(_T_107, _T_108)
node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_111 = and(_T_109, _T_110)
node _T_112 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_115 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_116 = and(_T_114, _T_115)
node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_118 = and(_T_116, _T_117)
node _T_119 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_122 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_123 = and(_T_121, _T_122)
node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hf))
node _T_129 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_134 = and(_T_132, _T_133)
node _T_135 = or(_T_85, _T_92)
node _T_136 = or(_T_135, _T_99)
node _T_137 = or(_T_136, _T_106)
node _T_138 = or(_T_137, _T_113)
node _T_139 = or(_T_138, _T_120)
node _T_140 = or(_T_139, _T_127)
node _T_141 = or(_T_140, _T_134)
node _T_142 = or(_T_78, _T_141)
node _T_143 = asUInt(reset)
node _T_144 = eq(_T_143, UInt<1>(0h0))
when _T_144 :
node _T_145 = eq(_T_142, UInt<1>(0h0))
when _T_145 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_142, UInt<1>(0h1), "") : assert_3 | module NoCMonitor_1( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_SlaveXbar_IbexTile_i0_o0_a1d8s1k1z1u :
input clock : Clock
input reset : Reset
output auto : { }
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0]
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<1>, source : UInt<1>, address : UInt<1>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<1>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}[0] | module TLXbar_SlaveXbar_IbexTile_i0_o0_a1d8s1k1z1u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset // @[Xbar.scala:74:9]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_48 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_48(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_78 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_78( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_7 :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<40>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<2>, offset : UInt<2>}}, flip lb_resp : UInt<128>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<2>, offset : UInt<2>, data : UInt<128>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 11, 6)
node req_tag = shr(req.addr, 12)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 4)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 4)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue_11
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal
connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr
connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br
connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned
connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned
connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state
connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std
connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta
connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load
connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd
connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw
connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn
connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel
connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel
connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel
connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type
connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code
connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<4>}}, clock
reg refill_ctr : UInt<2>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
invalidate io.meta_write.bits.data.tag
invalidate io.meta_write.bits.data.coh.state
invalidate io.meta_write.bits.tag
invalidate io.meta_write.bits.way_en
invalidate io.meta_write.bits.idx
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
invalidate io.mem_acquire.bits.corrupt
invalidate io.mem_acquire.bits.data
invalidate io.mem_acquire.bits.mask
invalidate io.mem_acquire.bits.address
invalidate io.mem_acquire.bits.source
invalidate io.mem_acquire.bits.size
invalidate io.mem_acquire.bits.param
invalidate io.mem_acquire.bits.opcode
connect io.refill.valid, UInt<1>(0h0)
invalidate io.refill.bits.data
invalidate io.refill.bits.wmask
invalidate io.refill.bits.addr
invalidate io.refill.bits.way_en
connect io.replay.valid, UInt<1>(0h0)
invalidate io.replay.bits.sdq_id
invalidate io.replay.bits.way_en
invalidate io.replay.bits.old_meta.tag
invalidate io.replay.bits.old_meta.coh.state
invalidate io.replay.bits.tag_match
invalidate io.replay.bits.is_hella
invalidate io.replay.bits.data
invalidate io.replay.bits.addr
invalidate io.replay.bits.uop.debug_tsrc
invalidate io.replay.bits.uop.debug_fsrc
invalidate io.replay.bits.uop.bp_xcpt_if
invalidate io.replay.bits.uop.bp_debug_if
invalidate io.replay.bits.uop.xcpt_ma_if
invalidate io.replay.bits.uop.xcpt_ae_if
invalidate io.replay.bits.uop.xcpt_pf_if
invalidate io.replay.bits.uop.fp_single
invalidate io.replay.bits.uop.fp_val
invalidate io.replay.bits.uop.frs3_en
invalidate io.replay.bits.uop.lrs2_rtype
invalidate io.replay.bits.uop.lrs1_rtype
invalidate io.replay.bits.uop.dst_rtype
invalidate io.replay.bits.uop.ldst_val
invalidate io.replay.bits.uop.lrs3
invalidate io.replay.bits.uop.lrs2
invalidate io.replay.bits.uop.lrs1
invalidate io.replay.bits.uop.ldst
invalidate io.replay.bits.uop.ldst_is_rs1
invalidate io.replay.bits.uop.flush_on_commit
invalidate io.replay.bits.uop.is_unique
invalidate io.replay.bits.uop.is_sys_pc2epc
invalidate io.replay.bits.uop.uses_stq
invalidate io.replay.bits.uop.uses_ldq
invalidate io.replay.bits.uop.is_amo
invalidate io.replay.bits.uop.is_fencei
invalidate io.replay.bits.uop.is_fence
invalidate io.replay.bits.uop.mem_signed
invalidate io.replay.bits.uop.mem_size
invalidate io.replay.bits.uop.mem_cmd
invalidate io.replay.bits.uop.bypassable
invalidate io.replay.bits.uop.exc_cause
invalidate io.replay.bits.uop.exception
invalidate io.replay.bits.uop.stale_pdst
invalidate io.replay.bits.uop.ppred_busy
invalidate io.replay.bits.uop.prs3_busy
invalidate io.replay.bits.uop.prs2_busy
invalidate io.replay.bits.uop.prs1_busy
invalidate io.replay.bits.uop.ppred
invalidate io.replay.bits.uop.prs3
invalidate io.replay.bits.uop.prs2
invalidate io.replay.bits.uop.prs1
invalidate io.replay.bits.uop.pdst
invalidate io.replay.bits.uop.rxq_idx
invalidate io.replay.bits.uop.stq_idx
invalidate io.replay.bits.uop.ldq_idx
invalidate io.replay.bits.uop.rob_idx
invalidate io.replay.bits.uop.csr_addr
invalidate io.replay.bits.uop.imm_packed
invalidate io.replay.bits.uop.taken
invalidate io.replay.bits.uop.pc_lob
invalidate io.replay.bits.uop.edge_inst
invalidate io.replay.bits.uop.ftq_idx
invalidate io.replay.bits.uop.br_tag
invalidate io.replay.bits.uop.br_mask
invalidate io.replay.bits.uop.is_sfb
invalidate io.replay.bits.uop.is_jal
invalidate io.replay.bits.uop.is_jalr
invalidate io.replay.bits.uop.is_br
invalidate io.replay.bits.uop.iw_p2_poisoned
invalidate io.replay.bits.uop.iw_p1_poisoned
invalidate io.replay.bits.uop.iw_state
invalidate io.replay.bits.uop.ctrl.is_std
invalidate io.replay.bits.uop.ctrl.is_sta
invalidate io.replay.bits.uop.ctrl.is_load
invalidate io.replay.bits.uop.ctrl.csr_cmd
invalidate io.replay.bits.uop.ctrl.fcn_dw
invalidate io.replay.bits.uop.ctrl.op_fcn
invalidate io.replay.bits.uop.ctrl.imm_sel
invalidate io.replay.bits.uop.ctrl.op2_sel
invalidate io.replay.bits.uop.ctrl.op1_sel
invalidate io.replay.bits.uop.ctrl.br_type
invalidate io.replay.bits.uop.fu_code
invalidate io.replay.bits.uop.iq_type
invalidate io.replay.bits.uop.debug_pc
invalidate io.replay.bits.uop.is_rvc
invalidate io.replay.bits.uop.debug_inst
invalidate io.replay.bits.uop.inst
invalidate io.replay.bits.uop.uopc
connect io.wb_req.valid, UInt<1>(0h0)
invalidate io.wb_req.bits.voluntary
invalidate io.wb_req.bits.way_en
invalidate io.wb_req.bits.param
invalidate io.wb_req.bits.source
invalidate io.wb_req.bits.idx
invalidate io.wb_req.bits.tag
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.is_hella
invalidate io.resp.bits.data
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
invalidate io.meta_read.bits.tag
invalidate io.meta_read.bits.way_en
invalidate io.meta_read.bits.idx
connect io.mem_finish.valid, UInt<1>(0h0)
invalidate io.mem_finish.bits.sink
connect io.lb_write.valid, UInt<1>(0h0)
invalidate io.lb_write.bits.data
invalidate io.lb_write.bits.offset
invalidate io.lb_write.bits.id
connect io.lb_read.valid, UInt<1>(0h0)
invalidate io.lb_read.bits.offset
invalidate io.lb_read.bits.id
connect io.mem_grant.ready, UInt<1>(0h0)
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000))
node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6)
node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000)))
node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8)
node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000))
node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10)
node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15)
node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17)
node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19)
node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000))
node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21)
node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000)))
node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23)
node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26)
node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28)
node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30)
node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31)
node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 3, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4))
node io_mem_acquire_bits_a_mask_sub_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 3, 3)
node io_mem_acquire_bits_a_mask_sub_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 3, 3)
node io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_sub_4_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_4 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_4_2)
node io_mem_acquire_bits_a_mask_sub_4_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_4)
node io_mem_acquire_bits_a_mask_sub_5_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_5 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_5_2)
node io_mem_acquire_bits_a_mask_sub_5_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_5)
node io_mem_acquire_bits_a_mask_sub_6_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_6 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_6_2)
node io_mem_acquire_bits_a_mask_sub_6_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_6)
node io_mem_acquire_bits_a_mask_sub_7_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_7 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_7_2)
node io_mem_acquire_bits_a_mask_sub_7_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_7)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_eq_8 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_8 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_8)
node io_mem_acquire_bits_a_mask_acc_8 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_8)
node io_mem_acquire_bits_a_mask_eq_9 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_9 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_9)
node io_mem_acquire_bits_a_mask_acc_9 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_9)
node io_mem_acquire_bits_a_mask_eq_10 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_10 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_10)
node io_mem_acquire_bits_a_mask_acc_10 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_10)
node io_mem_acquire_bits_a_mask_eq_11 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_11 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_11)
node io_mem_acquire_bits_a_mask_acc_11 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_11)
node io_mem_acquire_bits_a_mask_eq_12 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_12 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_12)
node io_mem_acquire_bits_a_mask_acc_12 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_12)
node io_mem_acquire_bits_a_mask_eq_13 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_13 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_13)
node io_mem_acquire_bits_a_mask_acc_13 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_13)
node io_mem_acquire_bits_a_mask_eq_14 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_14 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_14)
node io_mem_acquire_bits_a_mask_acc_14 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_14)
node io_mem_acquire_bits_a_mask_eq_15 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_15 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_15)
node io_mem_acquire_bits_a_mask_acc_15 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_15)
node io_mem_acquire_bits_a_mask_lo_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_lo_lo_hi, io_mem_acquire_bits_a_mask_lo_lo_lo)
node io_mem_acquire_bits_a_mask_lo_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_lo_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_lo_hi_hi, io_mem_acquire_bits_a_mask_lo_hi_lo)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_9, io_mem_acquire_bits_a_mask_acc_8)
node io_mem_acquire_bits_a_mask_hi_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_11, io_mem_acquire_bits_a_mask_acc_10)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_hi_lo_hi, io_mem_acquire_bits_a_mask_hi_lo_lo)
node io_mem_acquire_bits_a_mask_hi_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_13, io_mem_acquire_bits_a_mask_acc_12)
node io_mem_acquire_bits_a_mask_hi_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_15, io_mem_acquire_bits_a_mask_acc_14)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_hi_hi_hi, io_mem_acquire_bits_a_mask_hi_hi_lo)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.mem_grant.ready, io.lb_write.ready
connect io.lb_write.valid, io.mem_grant.valid
connect io.lb_write.bits.id, io.id
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 4)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<4>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node word_idx = bits(rp_addr, 3, 3)
node _data_word_T = cat(word_idx, UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready)
node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1
node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.lb_read.valid, _io_lb_read_valid_T
connect io.lb_read.bits.id, io.id
node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 4)
connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T
node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid)
node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T)
node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load)
connect io.resp.valid, _io_resp_valid_T_2
connect io.resp.bits.uop, rpq.io.deq.bits.uop
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 11, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.valid, UInt<1>(0h1)
connect io.lb_read.bits.id, io.id
connect io.lb_read.bits.offset, refill_ctr
node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid)
connect io.refill.valid, _io_refill_valid_T
node _io_refill_bits_addr_T = shl(refill_ctr, 4)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<2>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<2>(0h3))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
connect io.mem_finish.bits, grantack.bits
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR_7( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_br, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_jalr, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_jal, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_fp_single, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14]
input io_brupdate_b2_valid, // @[mshrs.scala:39:14]
input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14]
input io_brupdate_b2_taken, // @[mshrs.scala:39:14]
input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14]
input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14]
input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14]
input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14]
input io_exception, // @[mshrs.scala:39:14]
input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [39:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [7:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [5:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [7:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [27:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [39:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [1:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [127:0] io_lb_resp, // @[mshrs.scala:39:14]
input io_lb_write_ready, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7]
wire io_exception_0 = io_exception; // @[mshrs.scala:36:7]
wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire [1:0] io_id = 2'h3; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7]
wire [1:0] io_lb_read_bits_id = 2'h3; // @[mshrs.scala:36:7]
wire [1:0] io_lb_write_bits_id = 2'h3; // @[mshrs.scala:36:7]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:342:30]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [2:0] io_mem_acquire_bits_source = 3'h3; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_source = 3'h3; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_source = 3'h3; // @[Edges.scala:346:17]
wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7]
wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17]
wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7]
wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [19:0] io_meta_write_bits_tag = 20'h0; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [5:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [27:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [39:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [1:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [39:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [7:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34]
wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] r_counter; // @[Edges.scala:229:27]
wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [1:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [33:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [33:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [33:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42]
wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire word_idx = rp_addr[3]; // @[mshrs.scala:261:22, :262:56]
wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:262:56, :264:32]
wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :264:{26,32}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [35:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[1:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :340:59]
wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :345:32]
wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module BranchPredictor_1 :
input clock : Clock
input reset : Reset
output io : { flip f0_req : { valid : UInt<1>, bits : { pc : UInt<40>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}}}, resp : { f1 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], meta : UInt<120>[1], lhist : UInt<1>[1]}, f2 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], meta : UInt<120>[1], lhist : UInt<1>[1]}, f3 : { pc : UInt<40>, preds : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], meta : UInt<120>[1], lhist : UInt<1>[1]}}, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, lhist : UInt<1>[1], target : UInt<40>, meta : UInt<120>[1]}}}
inst banked_predictors_0 of ComposedBranchPredictorBank_1
connect banked_predictors_0.clock, clock
connect banked_predictors_0.reset, reset
inst banked_lhist_providers_0 of NullLocalBranchPredictorBank_1
connect banked_lhist_providers_0.clock, clock
connect banked_lhist_providers_0.reset, reset
connect banked_lhist_providers_0.io.f0_valid, io.f0_req.valid
node _banked_lhist_providers_0_io_f0_pc_T = not(io.f0_req.bits.pc)
node _banked_lhist_providers_0_io_f0_pc_T_1 = or(_banked_lhist_providers_0_io_f0_pc_T, UInt<3>(0h7))
node _banked_lhist_providers_0_io_f0_pc_T_2 = not(_banked_lhist_providers_0_io_f0_pc_T_1)
connect banked_lhist_providers_0.io.f0_pc, _banked_lhist_providers_0_io_f0_pc_T_2
connect banked_predictors_0.io.f0_valid, io.f0_req.valid
node _banked_predictors_0_io_f0_pc_T = not(io.f0_req.bits.pc)
node _banked_predictors_0_io_f0_pc_T_1 = or(_banked_predictors_0_io_f0_pc_T, UInt<3>(0h7))
node _banked_predictors_0_io_f0_pc_T_2 = not(_banked_predictors_0_io_f0_pc_T_1)
connect banked_predictors_0.io.f0_pc, _banked_predictors_0_io_f0_pc_T_2
node banked_predictors_0_io_f0_mask_idx = bits(io.f0_req.bits.pc, 2, 1)
node _banked_predictors_0_io_f0_mask_T = dshl(UInt<4>(0hf), banked_predictors_0_io_f0_mask_idx)
connect banked_predictors_0.io.f0_mask, _banked_predictors_0_io_f0_mask_T
reg banked_predictors_0_io_f1_ghist_REG : UInt, clock
connect banked_predictors_0_io_f1_ghist_REG, io.f0_req.bits.ghist.old_history
connect banked_predictors_0.io.f1_ghist, banked_predictors_0_io_f1_ghist_REG
connect banked_predictors_0.io.f1_lhist, banked_lhist_providers_0.io.f1_lhist
wire _banked_predictors_0_io_resp_in_0_WIRE : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits, UInt<40>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br, UInt<1>(0h0)
connect _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken, UInt<1>(0h0)
connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_jal
connect banked_predictors_0.io.resp_in[0].f3[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].is_br
connect banked_predictors_0.io.resp_in[0].f3[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[0].taken
connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_jal
connect banked_predictors_0.io.resp_in[0].f3[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].is_br
connect banked_predictors_0.io.resp_in[0].f3[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[1].taken
connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_jal
connect banked_predictors_0.io.resp_in[0].f3[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].is_br
connect banked_predictors_0.io.resp_in[0].f3[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[2].taken
connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f3[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f3[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_jal
connect banked_predictors_0.io.resp_in[0].f3[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].is_br
connect banked_predictors_0.io.resp_in[0].f3[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f3[3].taken
connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_jal
connect banked_predictors_0.io.resp_in[0].f2[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].is_br
connect banked_predictors_0.io.resp_in[0].f2[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[0].taken
connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_jal
connect banked_predictors_0.io.resp_in[0].f2[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].is_br
connect banked_predictors_0.io.resp_in[0].f2[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[1].taken
connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_jal
connect banked_predictors_0.io.resp_in[0].f2[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].is_br
connect banked_predictors_0.io.resp_in[0].f2[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[2].taken
connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f2[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f2[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_jal
connect banked_predictors_0.io.resp_in[0].f2[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].is_br
connect banked_predictors_0.io.resp_in[0].f2[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f2[3].taken
connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[0].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[0].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_jal
connect banked_predictors_0.io.resp_in[0].f1[0].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].is_br
connect banked_predictors_0.io.resp_in[0].f1[0].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[0].taken
connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[1].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[1].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_jal
connect banked_predictors_0.io.resp_in[0].f1[1].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].is_br
connect banked_predictors_0.io.resp_in[0].f1[1].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[1].taken
connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[2].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[2].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_jal
connect banked_predictors_0.io.resp_in[0].f1[2].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].is_br
connect banked_predictors_0.io.resp_in[0].f1[2].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[2].taken
connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.bits, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.bits
connect banked_predictors_0.io.resp_in[0].f1[3].predicted_pc.valid, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].predicted_pc.valid
connect banked_predictors_0.io.resp_in[0].f1[3].is_jal, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_jal
connect banked_predictors_0.io.resp_in[0].f1[3].is_br, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].is_br
connect banked_predictors_0.io.resp_in[0].f1[3].taken, _banked_predictors_0_io_resp_in_0_WIRE.f1[3].taken
node _banked_lhist_providers_0_io_f3_taken_br_T = and(banked_predictors_0.io.resp.f3[0].is_br, banked_predictors_0.io.resp.f3[0].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_1 = and(_banked_lhist_providers_0_io_f3_taken_br_T, banked_predictors_0.io.resp.f3[0].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_2 = and(banked_predictors_0.io.resp.f3[1].is_br, banked_predictors_0.io.resp.f3[1].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_3 = and(_banked_lhist_providers_0_io_f3_taken_br_T_2, banked_predictors_0.io.resp.f3[1].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_4 = and(banked_predictors_0.io.resp.f3[2].is_br, banked_predictors_0.io.resp.f3[2].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_5 = and(_banked_lhist_providers_0_io_f3_taken_br_T_4, banked_predictors_0.io.resp.f3[2].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_6 = and(banked_predictors_0.io.resp.f3[3].is_br, banked_predictors_0.io.resp.f3[3].predicted_pc.valid)
node _banked_lhist_providers_0_io_f3_taken_br_T_7 = and(_banked_lhist_providers_0_io_f3_taken_br_T_6, banked_predictors_0.io.resp.f3[3].taken)
node _banked_lhist_providers_0_io_f3_taken_br_T_8 = or(_banked_lhist_providers_0_io_f3_taken_br_T_1, _banked_lhist_providers_0_io_f3_taken_br_T_3)
node _banked_lhist_providers_0_io_f3_taken_br_T_9 = or(_banked_lhist_providers_0_io_f3_taken_br_T_8, _banked_lhist_providers_0_io_f3_taken_br_T_5)
node _banked_lhist_providers_0_io_f3_taken_br_T_10 = or(_banked_lhist_providers_0_io_f3_taken_br_T_9, _banked_lhist_providers_0_io_f3_taken_br_T_7)
connect banked_lhist_providers_0.io.f3_taken_br, _banked_lhist_providers_0_io_f3_taken_br_T_10
connect io.resp.f1.preds, banked_predictors_0.io.resp.f1
connect io.resp.f2.preds, banked_predictors_0.io.resp.f2
connect io.resp.f3.preds, banked_predictors_0.io.resp.f3
connect io.resp.f3.meta[0], banked_predictors_0.io.f3_meta
connect io.resp.f3.lhist[0], banked_lhist_providers_0.io.f3_lhist
connect banked_predictors_0.io.f3_fire, io.f3_fire
connect banked_lhist_providers_0.io.f3_fire, io.f3_fire
reg io_resp_f1_pc_REG : UInt, clock
connect io_resp_f1_pc_REG, io.f0_req.bits.pc
connect io.resp.f1.pc, io_resp_f1_pc_REG
reg io_resp_f2_pc_REG : UInt, clock
connect io_resp_f2_pc_REG, io.resp.f1.pc
connect io.resp.f2.pc, io_resp_f2_pc_REG
reg io_resp_f3_pc_REG : UInt, clock
connect io_resp_f3_pc_REG, io.resp.f2.pc
connect io.resp.f3.pc, io_resp_f3_pc_REG
invalidate io.resp.f1.meta[0]
invalidate io.resp.f2.meta[0]
invalidate io.resp.f1.lhist[0]
invalidate io.resp.f2.lhist[0]
connect banked_predictors_0.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect banked_predictors_0.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect banked_predictors_0.io.update.bits.meta, io.update.bits.meta[0]
connect banked_predictors_0.io.update.bits.lhist, io.update.bits.lhist[0]
connect banked_predictors_0.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect banked_predictors_0.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect banked_predictors_0.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect banked_predictors_0.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect banked_predictors_0.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect banked_predictors_0.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect banked_predictors_0.io.update.bits.target, io.update.bits.target
connect banked_lhist_providers_0.io.update.mispredict, io.update.bits.is_mispredict_update
connect banked_lhist_providers_0.io.update.repair, io.update.bits.is_repair_update
connect banked_lhist_providers_0.io.update.lhist, io.update.bits.lhist[0]
connect banked_predictors_0.io.update.valid, io.update.valid
node _banked_predictors_0_io_update_bits_pc_T = not(io.update.bits.pc)
node _banked_predictors_0_io_update_bits_pc_T_1 = or(_banked_predictors_0_io_update_bits_pc_T, UInt<3>(0h7))
node _banked_predictors_0_io_update_bits_pc_T_2 = not(_banked_predictors_0_io_update_bits_pc_T_1)
connect banked_predictors_0.io.update.bits.pc, _banked_predictors_0_io_update_bits_pc_T_2
connect banked_predictors_0.io.update.bits.br_mask, io.update.bits.br_mask
connect banked_predictors_0.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect banked_predictors_0.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect banked_predictors_0.io.update.bits.ghist, io.update.bits.ghist.old_history
node _banked_lhist_providers_0_io_update_valid_T = neq(io.update.bits.br_mask, UInt<1>(0h0))
node _banked_lhist_providers_0_io_update_valid_T_1 = and(io.update.valid, _banked_lhist_providers_0_io_update_valid_T)
connect banked_lhist_providers_0.io.update.valid, _banked_lhist_providers_0_io_update_valid_T_1
node _banked_lhist_providers_0_io_update_pc_T = not(io.update.bits.pc)
node _banked_lhist_providers_0_io_update_pc_T_1 = or(_banked_lhist_providers_0_io_update_pc_T, UInt<3>(0h7))
node _banked_lhist_providers_0_io_update_pc_T_2 = not(_banked_lhist_providers_0_io_update_pc_T_1)
connect banked_lhist_providers_0.io.update.pc, _banked_lhist_providers_0_io_update_pc_T_2
when io.update.valid :
node _T = and(io.update.bits.cfi_is_br, io.update.bits.cfi_idx.valid)
when _T :
node _T_1 = dshr(io.update.bits.br_mask, io.update.bits.cfi_idx.bits)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at predictor.scala:468 assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert | module BranchPredictor_1( // @[predictor.scala:194:7]
input clock, // @[predictor.scala:194:7]
input reset, // @[predictor.scala:194:7]
input io_f0_req_valid, // @[predictor.scala:197:14]
input [39:0] io_f0_req_bits_pc, // @[predictor.scala:197:14]
input [63:0] io_f0_req_bits_ghist_old_history, // @[predictor.scala:197:14]
input io_f0_req_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_f0_req_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_f0_req_bits_ghist_new_saw_branch_taken, // @[predictor.scala:197:14]
input [4:0] io_f0_req_bits_ghist_ras_idx, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_0_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_0_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_1_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_1_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_2_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_2_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_taken, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_is_br, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_is_jal, // @[predictor.scala:197:14]
output io_resp_f1_preds_3_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f1_preds_3_predicted_pc_bits, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_pc, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_0_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_0_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_1_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_1_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_2_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_2_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_taken, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_is_br, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_is_jal, // @[predictor.scala:197:14]
output io_resp_f2_preds_3_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f2_preds_3_predicted_pc_bits, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_pc, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_0_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_0_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_1_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_1_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_2_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_2_predicted_pc_bits, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_taken, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_is_br, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_is_jal, // @[predictor.scala:197:14]
output io_resp_f3_preds_3_predicted_pc_valid, // @[predictor.scala:197:14]
output [39:0] io_resp_f3_preds_3_predicted_pc_bits, // @[predictor.scala:197:14]
output [119:0] io_resp_f3_meta_0, // @[predictor.scala:197:14]
input io_f3_fire, // @[predictor.scala:197:14]
input io_update_valid, // @[predictor.scala:197:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:197:14]
input io_update_bits_is_repair_update, // @[predictor.scala:197:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:197:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:197:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:197:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:197:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:197:14]
input io_update_bits_cfi_taken, // @[predictor.scala:197:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:197:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:197:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:197:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:197:14]
input [63:0] io_update_bits_ghist_old_history, // @[predictor.scala:197:14]
input io_update_bits_ghist_current_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_update_bits_ghist_new_saw_branch_not_taken, // @[predictor.scala:197:14]
input io_update_bits_ghist_new_saw_branch_taken, // @[predictor.scala:197:14]
input [4:0] io_update_bits_ghist_ras_idx, // @[predictor.scala:197:14]
input io_update_bits_lhist_0, // @[predictor.scala:197:14]
input [39:0] io_update_bits_target, // @[predictor.scala:197:14]
input [119:0] io_update_bits_meta_0 // @[predictor.scala:197:14]
);
wire _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_0_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_1_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_2_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_3_is_br; // @[predictor.scala:218:19]
wire _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:218:19]
wire io_f0_req_valid_0 = io_f0_req_valid; // @[predictor.scala:194:7]
wire [39:0] io_f0_req_bits_pc_0 = io_f0_req_bits_pc; // @[predictor.scala:194:7]
wire [63:0] io_f0_req_bits_ghist_old_history_0 = io_f0_req_bits_ghist_old_history; // @[predictor.scala:194:7]
wire io_f0_req_bits_ghist_current_saw_branch_not_taken_0 = io_f0_req_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_f0_req_bits_ghist_new_saw_branch_not_taken_0 = io_f0_req_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_f0_req_bits_ghist_new_saw_branch_taken_0 = io_f0_req_bits_ghist_new_saw_branch_taken; // @[predictor.scala:194:7]
wire [4:0] io_f0_req_bits_ghist_ras_idx_0 = io_f0_req_bits_ghist_ras_idx; // @[predictor.scala:194:7]
wire io_f3_fire_0 = io_f3_fire; // @[predictor.scala:194:7]
wire io_update_valid_0 = io_update_valid; // @[predictor.scala:194:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[predictor.scala:194:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[predictor.scala:194:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[predictor.scala:194:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[predictor.scala:194:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[predictor.scala:194:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[predictor.scala:194:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[predictor.scala:194:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[predictor.scala:194:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[predictor.scala:194:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[predictor.scala:194:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[predictor.scala:194:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[predictor.scala:194:7]
wire [63:0] io_update_bits_ghist_old_history_0 = io_update_bits_ghist_old_history; // @[predictor.scala:194:7]
wire io_update_bits_ghist_current_saw_branch_not_taken_0 = io_update_bits_ghist_current_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_update_bits_ghist_new_saw_branch_not_taken_0 = io_update_bits_ghist_new_saw_branch_not_taken; // @[predictor.scala:194:7]
wire io_update_bits_ghist_new_saw_branch_taken_0 = io_update_bits_ghist_new_saw_branch_taken; // @[predictor.scala:194:7]
wire [4:0] io_update_bits_ghist_ras_idx_0 = io_update_bits_ghist_ras_idx; // @[predictor.scala:194:7]
wire io_update_bits_lhist_0_0 = io_update_bits_lhist_0; // @[predictor.scala:194:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[predictor.scala:194:7]
wire [119:0] io_update_bits_meta_0_0 = io_update_bits_meta_0; // @[predictor.scala:194:7]
wire [119:0] io_resp_f1_meta_0 = 120'h0; // @[predictor.scala:194:7]
wire [119:0] io_resp_f2_meta_0 = 120'h0; // @[predictor.scala:194:7]
wire io_resp_f1_lhist_0 = 1'h0; // @[predictor.scala:194:7]
wire io_resp_f2_lhist_0 = 1'h0; // @[predictor.scala:194:7]
wire io_resp_f3_lhist_0 = 1'h0; // @[predictor.scala:194:7]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_taken = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_br = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_is_jal = 1'h0; // @[predictor.scala:242:67]
wire _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire [39:0] _banked_predictors_0_io_resp_in_0_WIRE_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:242:67]
wire io_resp_f1_preds_0_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_0_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_0_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_0_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_0_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_1_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_1_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_2_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_2_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_preds_3_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_taken_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f1_preds_3_is_jal_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f1_pc; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_0_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_0_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_1_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_1_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_2_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_2_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_preds_3_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_taken_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f2_preds_3_is_jal_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f2_pc_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_0_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_0_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_1_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_1_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_2_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_2_is_jal_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_predicted_pc_valid_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_preds_3_predicted_pc_bits_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_taken_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_is_br_0; // @[predictor.scala:194:7]
wire io_resp_f3_preds_3_is_jal_0; // @[predictor.scala:194:7]
wire [119:0] io_resp_f3_meta_0_0; // @[predictor.scala:194:7]
wire [39:0] io_resp_f3_pc_0; // @[predictor.scala:194:7]
wire [39:0] _banked_lhist_providers_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_1 = {_banked_lhist_providers_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_lhist_providers_0_io_f0_pc_T_2 = ~_banked_lhist_providers_0_io_f0_pc_T_1; // @[frontend.scala:160:{31,39}]
wire [39:0] _banked_predictors_0_io_f0_pc_T = ~io_f0_req_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_predictors_0_io_f0_pc_T_1 = {_banked_predictors_0_io_f0_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_predictors_0_io_f0_pc_T_2 = ~_banked_predictors_0_io_f0_pc_T_1; // @[frontend.scala:160:{31,39}]
wire [1:0] banked_predictors_0_io_f0_mask_idx = io_f0_req_bits_pc_0[2:1]; // @[package.scala:163:13]
wire [6:0] _banked_predictors_0_io_f0_mask_T = 7'hF << banked_predictors_0_io_f0_mask_idx; // @[package.scala:163:13]
reg [63:0] banked_predictors_0_io_f1_ghist_REG; // @[predictor.scala:239:48]
wire _banked_lhist_providers_0_io_f3_taken_br_T = _banked_predictors_0_io_resp_f3_0_is_br & _banked_predictors_0_io_resp_f3_0_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_1 = _banked_lhist_providers_0_io_f3_taken_br_T & _banked_predictors_0_io_resp_f3_0_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_2 = _banked_predictors_0_io_resp_f3_1_is_br & _banked_predictors_0_io_resp_f3_1_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_3 = _banked_lhist_providers_0_io_f3_taken_br_T_2 & _banked_predictors_0_io_resp_f3_1_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_4 = _banked_predictors_0_io_resp_f3_2_is_br & _banked_predictors_0_io_resp_f3_2_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_5 = _banked_lhist_providers_0_io_f3_taken_br_T_4 & _banked_predictors_0_io_resp_f3_2_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_6 = _banked_predictors_0_io_resp_f3_3_is_br & _banked_predictors_0_io_resp_f3_3_predicted_pc_valid; // @[predictor.scala:218:19, :293:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_7 = _banked_lhist_providers_0_io_f3_taken_br_T_6 & _banked_predictors_0_io_resp_f3_3_taken; // @[predictor.scala:218:19, :293:{15,39}]
wire _banked_lhist_providers_0_io_f3_taken_br_T_8 = _banked_lhist_providers_0_io_f3_taken_br_T_1 | _banked_lhist_providers_0_io_f3_taken_br_T_3; // @[predictor.scala:293:39, :294:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_9 = _banked_lhist_providers_0_io_f3_taken_br_T_8 | _banked_lhist_providers_0_io_f3_taken_br_T_5; // @[predictor.scala:293:39, :294:15]
wire _banked_lhist_providers_0_io_f3_taken_br_T_10 = _banked_lhist_providers_0_io_f3_taken_br_T_9 | _banked_lhist_providers_0_io_f3_taken_br_T_7; // @[predictor.scala:293:39, :294:15]
reg [39:0] io_resp_f1_pc_REG; // @[predictor.scala:362:27]
assign io_resp_f1_pc = io_resp_f1_pc_REG; // @[predictor.scala:194:7, :362:27]
reg [39:0] io_resp_f2_pc_REG; // @[predictor.scala:363:27]
assign io_resp_f2_pc_0 = io_resp_f2_pc_REG; // @[predictor.scala:194:7, :363:27]
reg [39:0] io_resp_f3_pc_REG; // @[predictor.scala:364:27]
assign io_resp_f3_pc_0 = io_resp_f3_pc_REG; // @[predictor.scala:194:7, :364:27]
wire [39:0] _banked_predictors_0_io_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_predictors_0_io_update_bits_pc_T_1 = {_banked_predictors_0_io_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_predictors_0_io_update_bits_pc_T_2 = ~_banked_predictors_0_io_update_bits_pc_T_1; // @[frontend.scala:160:{31,39}]
wire _banked_lhist_providers_0_io_update_valid_T = |io_update_bits_br_mask_0; // @[predictor.scala:194:7, :401:92]
wire _banked_lhist_providers_0_io_update_valid_T_1 = io_update_valid_0 & _banked_lhist_providers_0_io_update_valid_T; // @[predictor.scala:194:7, :401:{66,92}]
wire [39:0] _banked_lhist_providers_0_io_update_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:160:33]
wire [39:0] _banked_lhist_providers_0_io_update_pc_T_1 = {_banked_lhist_providers_0_io_update_pc_T[39:3], 3'h7}; // @[frontend.scala:160:{33,39}]
wire [39:0] _banked_lhist_providers_0_io_update_pc_T_2 = ~_banked_lhist_providers_0_io_update_pc_T_1; // @[frontend.scala:160:{31,39}] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_9 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_9( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_266 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_494
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_266( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_494 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_64 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_64( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_router_8ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, routers_egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip routers_ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip routers_ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_8
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in
connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free
connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return
connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit
connect routers.auto.ingress_nodes_in_0, auto.routers_ingress_nodes_in_0
connect routers.auto.ingress_nodes_in_1, auto.routers_ingress_nodes_in_1
connect auto.routers_egress_nodes_out_0.flit.bits, routers.auto.egress_nodes_out_0.flit.bits
connect auto.routers_egress_nodes_out_0.flit.valid, routers.auto.egress_nodes_out_0.flit.valid
connect routers.auto.egress_nodes_out_0.flit.ready, auto.routers_egress_nodes_out_0.flit.ready
connect auto.routers_egress_nodes_out_1.flit.bits, routers.auto.egress_nodes_out_1.flit.bits
connect auto.routers_egress_nodes_out_1.flit.valid, routers.auto.egress_nodes_out_1.flit.valid
connect routers.auto.egress_nodes_out_1.flit.ready, auto.routers_egress_nodes_out_1.flit.ready
connect auto.routers_egress_nodes_out_2.flit.bits, routers.auto.egress_nodes_out_2.flit.bits
connect auto.routers_egress_nodes_out_2.flit.valid, routers.auto.egress_nodes_out_2.flit.valid
connect routers.auto.egress_nodes_out_2.flit.ready, auto.routers_egress_nodes_out_2.flit.ready
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_router_8ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [3:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_routers_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_8 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_egress_nodes_out_2_flit_valid (auto_routers_egress_nodes_out_2_flit_valid),
.auto_egress_nodes_out_2_flit_bits_head (auto_routers_egress_nodes_out_2_flit_bits_head),
.auto_egress_nodes_out_2_flit_bits_tail (auto_routers_egress_nodes_out_2_flit_bits_tail),
.auto_egress_nodes_out_2_flit_bits_payload (auto_routers_egress_nodes_out_2_flit_bits_payload),
.auto_egress_nodes_out_1_flit_ready (auto_routers_egress_nodes_out_1_flit_ready),
.auto_egress_nodes_out_1_flit_valid (auto_routers_egress_nodes_out_1_flit_valid),
.auto_egress_nodes_out_1_flit_bits_head (auto_routers_egress_nodes_out_1_flit_bits_head),
.auto_egress_nodes_out_1_flit_bits_tail (auto_routers_egress_nodes_out_1_flit_bits_tail),
.auto_egress_nodes_out_1_flit_bits_payload (auto_routers_egress_nodes_out_1_flit_bits_payload),
.auto_egress_nodes_out_0_flit_ready (auto_routers_egress_nodes_out_0_flit_ready),
.auto_egress_nodes_out_0_flit_valid (auto_routers_egress_nodes_out_0_flit_valid),
.auto_egress_nodes_out_0_flit_bits_head (auto_routers_egress_nodes_out_0_flit_bits_head),
.auto_egress_nodes_out_0_flit_bits_tail (auto_routers_egress_nodes_out_0_flit_bits_tail),
.auto_egress_nodes_out_0_flit_bits_payload (auto_routers_egress_nodes_out_0_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_ready (auto_routers_ingress_nodes_in_1_flit_ready),
.auto_ingress_nodes_in_1_flit_valid (auto_routers_ingress_nodes_in_1_flit_valid),
.auto_ingress_nodes_in_1_flit_bits_head (auto_routers_ingress_nodes_in_1_flit_bits_head),
.auto_ingress_nodes_in_1_flit_bits_tail (auto_routers_ingress_nodes_in_1_flit_bits_tail),
.auto_ingress_nodes_in_1_flit_bits_payload (auto_routers_ingress_nodes_in_1_flit_bits_payload),
.auto_ingress_nodes_in_1_flit_bits_egress_id (auto_routers_ingress_nodes_in_1_flit_bits_egress_id),
.auto_ingress_nodes_in_0_flit_ready (auto_routers_ingress_nodes_in_0_flit_ready),
.auto_ingress_nodes_in_0_flit_valid (auto_routers_ingress_nodes_in_0_flit_valid),
.auto_ingress_nodes_in_0_flit_bits_head (auto_routers_ingress_nodes_in_0_flit_bits_head),
.auto_ingress_nodes_in_0_flit_bits_tail (auto_routers_ingress_nodes_in_0_flit_bits_tail),
.auto_ingress_nodes_in_0_flit_bits_payload (auto_routers_ingress_nodes_in_0_flit_bits_payload),
.auto_ingress_nodes_in_0_flit_bits_egress_id (auto_routers_ingress_nodes_in_0_flit_bits_egress_id),
.auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid),
.auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head),
.auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail),
.auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload),
.auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return),
.auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free),
.auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid),
.auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head),
.auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail),
.auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload),
.auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return),
.auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE : UInt<1>[3]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
connect _source_ok_WIRE[2], _source_ok_T_2
node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_23 = cvt(_T_22)
node _T_24 = and(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = asSInt(_T_24)
node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = or(_T_21, _T_26)
node _T_28 = and(_T_11, _T_19)
node _T_29 = and(_T_28, _T_27)
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_29, UInt<1>(0h1), "") : assert_1
node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_33 :
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_40 = or(_T_37, _T_38)
node _T_41 = or(_T_40, _T_39)
node _T_42 = and(_T_36, _T_41)
node _T_43 = or(UInt<1>(0h0), _T_42)
node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_56 = cvt(_T_55)
node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000)))
node _T_58 = asSInt(_T_57)
node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0)))
node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_61 = cvt(_T_60)
node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000)))
node _T_63 = asSInt(_T_62)
node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0)))
node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = or(_T_49, _T_54)
node _T_86 = or(_T_85, _T_59)
node _T_87 = or(_T_86, _T_64)
node _T_88 = or(_T_87, _T_69)
node _T_89 = or(_T_88, _T_74)
node _T_90 = or(_T_89, _T_79)
node _T_91 = or(_T_90, _T_84)
node _T_92 = and(_T_44, _T_91)
node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = and(_T_94, _T_105)
node _T_107 = or(UInt<1>(0h0), _T_92)
node _T_108 = or(_T_107, _T_106)
node _T_109 = and(_T_43, _T_108)
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_109, UInt<1>(0h1), "") : assert_2
node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE : UInt<1>[3]
connect _WIRE[0], _T_113
connect _WIRE[1], _T_114
connect _WIRE[2], _T_115
node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0))
node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_120 = or(_T_117, _T_118)
node _T_121 = or(_T_120, _T_119)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_121
node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_124 = and(_T_122, _T_123)
node _T_125 = or(UInt<1>(0h0), _T_124)
node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = or(_T_130, _T_135)
node _T_177 = or(_T_176, _T_140)
node _T_178 = or(_T_177, _T_145)
node _T_179 = or(_T_178, _T_150)
node _T_180 = or(_T_179, _T_155)
node _T_181 = or(_T_180, _T_160)
node _T_182 = or(_T_181, _T_165)
node _T_183 = or(_T_182, _T_170)
node _T_184 = or(_T_183, _T_175)
node _T_185 = and(_T_125, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(_WIRE_1, _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_187, UInt<1>(0h1), "") : assert_3
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(source_ok, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_194, UInt<1>(0h1), "") : assert_5
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(is_aligned, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_201, UInt<1>(0h1), "") : assert_7
node _T_205 = not(io.in.a.bits.mask)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_206, UInt<1>(0h1), "") : assert_8
node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_210, UInt<1>(0h1), "") : assert_9
node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_214 :
node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_221 = or(_T_218, _T_219)
node _T_222 = or(_T_221, _T_220)
node _T_223 = and(_T_217, _T_222)
node _T_224 = or(UInt<1>(0h0), _T_223)
node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_252 = cvt(_T_251)
node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000)))
node _T_254 = asSInt(_T_253)
node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_230, _T_235)
node _T_267 = or(_T_266, _T_240)
node _T_268 = or(_T_267, _T_245)
node _T_269 = or(_T_268, _T_250)
node _T_270 = or(_T_269, _T_255)
node _T_271 = or(_T_270, _T_260)
node _T_272 = or(_T_271, _T_265)
node _T_273 = and(_T_225, _T_272)
node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_275 = or(UInt<1>(0h0), _T_274)
node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_277 = cvt(_T_276)
node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000)))
node _T_279 = asSInt(_T_278)
node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0)))
node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = or(_T_280, _T_285)
node _T_287 = and(_T_275, _T_286)
node _T_288 = or(UInt<1>(0h0), _T_273)
node _T_289 = or(_T_288, _T_287)
node _T_290 = and(_T_224, _T_289)
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_290, UInt<1>(0h1), "") : assert_10
node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE_2 : UInt<1>[3]
connect _WIRE_2[0], _T_294
connect _WIRE_2[1], _T_295
connect _WIRE_2[2], _T_296
node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0))
node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = or(_T_298, _T_299)
node _T_302 = or(_T_301, _T_300)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_302
node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_305 = and(_T_303, _T_304)
node _T_306 = or(UInt<1>(0h0), _T_305)
node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_328 = cvt(_T_327)
node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000)))
node _T_330 = asSInt(_T_329)
node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0)))
node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_353 = cvt(_T_352)
node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000)))
node _T_355 = asSInt(_T_354)
node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0)))
node _T_357 = or(_T_311, _T_316)
node _T_358 = or(_T_357, _T_321)
node _T_359 = or(_T_358, _T_326)
node _T_360 = or(_T_359, _T_331)
node _T_361 = or(_T_360, _T_336)
node _T_362 = or(_T_361, _T_341)
node _T_363 = or(_T_362, _T_346)
node _T_364 = or(_T_363, _T_351)
node _T_365 = or(_T_364, _T_356)
node _T_366 = and(_T_306, _T_365)
node _T_367 = or(UInt<1>(0h0), _T_366)
node _T_368 = and(_WIRE_3, _T_367)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_368, UInt<1>(0h1), "") : assert_11
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(source_ok, UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_375, UInt<1>(0h1), "") : assert_13
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(is_aligned, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_382, UInt<1>(0h1), "") : assert_15
node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_386, UInt<1>(0h1), "") : assert_16
node _T_390 = not(io.in.a.bits.mask)
node _T_391 = eq(_T_390, UInt<1>(0h0))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_391, UInt<1>(0h1), "") : assert_17
node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_T_395, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_395, UInt<1>(0h1), "") : assert_18
node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_399 :
node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_402 = and(_T_400, _T_401)
node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_406 = or(_T_403, _T_404)
node _T_407 = or(_T_406, _T_405)
node _T_408 = and(_T_402, _T_407)
node _T_409 = or(UInt<1>(0h0), _T_408)
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_409, UInt<1>(0h1), "") : assert_19
node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_415 = and(_T_413, _T_414)
node _T_416 = or(UInt<1>(0h0), _T_415)
node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_418 = cvt(_T_417)
node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000)))
node _T_420 = asSInt(_T_419)
node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0)))
node _T_422 = and(_T_416, _T_421)
node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_425 = and(_T_423, _T_424)
node _T_426 = or(UInt<1>(0h0), _T_425)
node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_433 = cvt(_T_432)
node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000)))
node _T_435 = asSInt(_T_434)
node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0)))
node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_438 = cvt(_T_437)
node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000)))
node _T_440 = asSInt(_T_439)
node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0)))
node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_443 = cvt(_T_442)
node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000)))
node _T_445 = asSInt(_T_444)
node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0)))
node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_453 = cvt(_T_452)
node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000)))
node _T_455 = asSInt(_T_454)
node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0)))
node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = or(_T_431, _T_436)
node _T_473 = or(_T_472, _T_441)
node _T_474 = or(_T_473, _T_446)
node _T_475 = or(_T_474, _T_451)
node _T_476 = or(_T_475, _T_456)
node _T_477 = or(_T_476, _T_461)
node _T_478 = or(_T_477, _T_466)
node _T_479 = or(_T_478, _T_471)
node _T_480 = and(_T_426, _T_479)
node _T_481 = or(UInt<1>(0h0), _T_422)
node _T_482 = or(_T_481, _T_480)
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_482, UInt<1>(0h1), "") : assert_20
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(source_ok, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(is_aligned, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_492, UInt<1>(0h1), "") : assert_23
node _T_496 = eq(io.in.a.bits.mask, mask)
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_496, UInt<1>(0h1), "") : assert_24
node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_500, UInt<1>(0h1), "") : assert_25
node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_504 :
node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_511 = or(_T_508, _T_509)
node _T_512 = or(_T_511, _T_510)
node _T_513 = and(_T_507, _T_512)
node _T_514 = or(UInt<1>(0h0), _T_513)
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_517 = and(_T_515, _T_516)
node _T_518 = or(UInt<1>(0h0), _T_517)
node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = and(_T_518, _T_523)
node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_527 = and(_T_525, _T_526)
node _T_528 = or(UInt<1>(0h0), _T_527)
node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = or(_T_533, _T_538)
node _T_570 = or(_T_569, _T_543)
node _T_571 = or(_T_570, _T_548)
node _T_572 = or(_T_571, _T_553)
node _T_573 = or(_T_572, _T_558)
node _T_574 = or(_T_573, _T_563)
node _T_575 = or(_T_574, _T_568)
node _T_576 = and(_T_528, _T_575)
node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_579 = cvt(_T_578)
node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000)))
node _T_581 = asSInt(_T_580)
node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0)))
node _T_583 = and(_T_577, _T_582)
node _T_584 = or(UInt<1>(0h0), _T_524)
node _T_585 = or(_T_584, _T_576)
node _T_586 = or(_T_585, _T_583)
node _T_587 = and(_T_514, _T_586)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_587, UInt<1>(0h1), "") : assert_26
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(source_ok, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(is_aligned, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_597, UInt<1>(0h1), "") : assert_29
node _T_601 = eq(io.in.a.bits.mask, mask)
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_601, UInt<1>(0h1), "") : assert_30
node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_605 :
node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_608 = and(_T_606, _T_607)
node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_612 = or(_T_609, _T_610)
node _T_613 = or(_T_612, _T_611)
node _T_614 = and(_T_608, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_618 = and(_T_616, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_618)
node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = and(_T_619, _T_624)
node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_628 = and(_T_626, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_628)
node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_646 = cvt(_T_645)
node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000)))
node _T_648 = asSInt(_T_647)
node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0)))
node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_656 = cvt(_T_655)
node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000)))
node _T_658 = asSInt(_T_657)
node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0)))
node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = or(_T_634, _T_639)
node _T_671 = or(_T_670, _T_644)
node _T_672 = or(_T_671, _T_649)
node _T_673 = or(_T_672, _T_654)
node _T_674 = or(_T_673, _T_659)
node _T_675 = or(_T_674, _T_664)
node _T_676 = or(_T_675, _T_669)
node _T_677 = and(_T_629, _T_676)
node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_680 = cvt(_T_679)
node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000)))
node _T_682 = asSInt(_T_681)
node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0)))
node _T_684 = and(_T_678, _T_683)
node _T_685 = or(UInt<1>(0h0), _T_625)
node _T_686 = or(_T_685, _T_677)
node _T_687 = or(_T_686, _T_684)
node _T_688 = and(_T_615, _T_687)
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_688, UInt<1>(0h1), "") : assert_31
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(source_ok, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(is_aligned, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(_T_698, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_698, UInt<1>(0h1), "") : assert_34
node _T_702 = not(mask)
node _T_703 = and(io.in.a.bits.mask, _T_702)
node _T_704 = eq(_T_703, UInt<1>(0h0))
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_704, UInt<1>(0h1), "") : assert_35
node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_708 :
node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_711 = and(_T_709, _T_710)
node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_715 = or(_T_712, _T_713)
node _T_716 = or(_T_715, _T_714)
node _T_717 = and(_T_711, _T_716)
node _T_718 = or(UInt<1>(0h0), _T_717)
node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_744 = cvt(_T_743)
node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000)))
node _T_746 = asSInt(_T_745)
node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0)))
node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_749 = cvt(_T_748)
node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000)))
node _T_751 = asSInt(_T_750)
node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0)))
node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_759 = cvt(_T_758)
node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000)))
node _T_761 = asSInt(_T_760)
node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0)))
node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_764 = cvt(_T_763)
node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000)))
node _T_766 = asSInt(_T_765)
node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0)))
node _T_768 = or(_T_727, _T_732)
node _T_769 = or(_T_768, _T_737)
node _T_770 = or(_T_769, _T_742)
node _T_771 = or(_T_770, _T_747)
node _T_772 = or(_T_771, _T_752)
node _T_773 = or(_T_772, _T_757)
node _T_774 = or(_T_773, _T_762)
node _T_775 = or(_T_774, _T_767)
node _T_776 = and(_T_722, _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_776)
node _T_785 = or(_T_784, _T_783)
node _T_786 = and(_T_718, _T_785)
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_786, UInt<1>(0h1), "") : assert_36
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(source_ok, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(is_aligned, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_796, UInt<1>(0h1), "") : assert_39
node _T_800 = eq(io.in.a.bits.mask, mask)
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_800, UInt<1>(0h1), "") : assert_40
node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_811 = or(_T_808, _T_809)
node _T_812 = or(_T_811, _T_810)
node _T_813 = and(_T_807, _T_812)
node _T_814 = or(UInt<1>(0h0), _T_813)
node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_817 = and(_T_815, _T_816)
node _T_818 = or(UInt<1>(0h0), _T_817)
node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_825 = cvt(_T_824)
node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000)))
node _T_827 = asSInt(_T_826)
node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0)))
node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = or(_T_823, _T_828)
node _T_865 = or(_T_864, _T_833)
node _T_866 = or(_T_865, _T_838)
node _T_867 = or(_T_866, _T_843)
node _T_868 = or(_T_867, _T_848)
node _T_869 = or(_T_868, _T_853)
node _T_870 = or(_T_869, _T_858)
node _T_871 = or(_T_870, _T_863)
node _T_872 = and(_T_818, _T_871)
node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = and(_T_873, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_872)
node _T_881 = or(_T_880, _T_879)
node _T_882 = and(_T_814, _T_881)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_882, UInt<1>(0h1), "") : assert_41
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(is_aligned, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_892, UInt<1>(0h1), "") : assert_44
node _T_896 = eq(io.in.a.bits.mask, mask)
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_896, UInt<1>(0h1), "") : assert_45
node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_900 :
node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_903 = and(_T_901, _T_902)
node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_907 = or(_T_904, _T_905)
node _T_908 = or(_T_907, _T_906)
node _T_909 = and(_T_903, _T_908)
node _T_910 = or(UInt<1>(0h0), _T_909)
node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_913 = and(_T_911, _T_912)
node _T_914 = or(UInt<1>(0h0), _T_913)
node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = and(_T_914, _T_919)
node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_923 = cvt(_T_922)
node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000)))
node _T_925 = asSInt(_T_924)
node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0)))
node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_928 = cvt(_T_927)
node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000)))
node _T_930 = asSInt(_T_929)
node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0)))
node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_933 = cvt(_T_932)
node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000)))
node _T_935 = asSInt(_T_934)
node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0)))
node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_948 = cvt(_T_947)
node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000)))
node _T_950 = asSInt(_T_949)
node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0)))
node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_953 = cvt(_T_952)
node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000)))
node _T_955 = asSInt(_T_954)
node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0)))
node _T_957 = or(_T_926, _T_931)
node _T_958 = or(_T_957, _T_936)
node _T_959 = or(_T_958, _T_941)
node _T_960 = or(_T_959, _T_946)
node _T_961 = or(_T_960, _T_951)
node _T_962 = or(_T_961, _T_956)
node _T_963 = and(_T_921, _T_962)
node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_966 = and(_T_964, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_969 = cvt(_T_968)
node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000)))
node _T_971 = asSInt(_T_970)
node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0)))
node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_974 = cvt(_T_973)
node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000)))
node _T_976 = asSInt(_T_975)
node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0)))
node _T_978 = or(_T_972, _T_977)
node _T_979 = and(_T_967, _T_978)
node _T_980 = or(UInt<1>(0h0), _T_920)
node _T_981 = or(_T_980, _T_963)
node _T_982 = or(_T_981, _T_979)
node _T_983 = and(_T_910, _T_982)
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_983, UInt<1>(0h1), "") : assert_46
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(source_ok, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(is_aligned, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_993, UInt<1>(0h1), "") : assert_49
node _T_997 = eq(io.in.a.bits.mask, mask)
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_997, UInt<1>(0h1), "") : assert_50
node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52
node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1))
node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_1 : UInt<1>[3]
connect _source_ok_WIRE_1[0], _source_ok_T_4
connect _source_ok_WIRE_1[1], _source_ok_T_5
connect _source_ok_WIRE_1[2], _source_ok_T_6
node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1009 :
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(source_ok_1, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54
node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55
node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56
node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57
node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1029 :
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(source_ok_1, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(sink_ok, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60
node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61
node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62
node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63
node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1053 = or(UInt<1>(0h1), _T_1052)
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64
node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1057 :
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(source_ok_1, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(sink_ok, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67
node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68
node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69
node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1077 = or(_T_1076, io.in.d.bits.corrupt)
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70
node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1082 = or(UInt<1>(0h1), _T_1081)
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71
node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(source_ok_1, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73
node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74
node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1099 = or(UInt<1>(0h1), _T_1098)
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75
node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1103 :
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(source_ok_1, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77
node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1112 = or(_T_1111, io.in.d.bits.corrupt)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78
node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1117 = or(UInt<1>(0h1), _T_1116)
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79
node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1121 :
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(source_ok_1, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81
node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(UInt<1>(0h1), _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84
node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1145 = cvt(_T_1144)
node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = asSInt(_T_1146)
node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = or(_T_1143, _T_1148)
node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = or(_T_1151, _T_1156)
node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2))
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1161 = cvt(_T_1160)
node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0)))
node _T_1163 = asSInt(_T_1162)
node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0)))
node _T_1165 = or(_T_1159, _T_1164)
node _T_1166 = and(_T_1149, _T_1157)
node _T_1167 = and(_T_1166, _T_1165)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _legal_source_WIRE : UInt<1>[3]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
connect _legal_source_WIRE[2], _legal_source_T_2
node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0))
node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4)
node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5)
wire _legal_source_WIRE_1 : UInt<2>
connect _legal_source_WIRE_1, _legal_source_T_7
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1171 :
node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _WIRE_4 : UInt<1>[3]
connect _WIRE_4[0], _T_1172
connect _WIRE_4[1], _T_1173
connect _WIRE_4[2], _T_1174
node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0))
node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1179 = or(_T_1176, _T_1177)
node _T_1180 = or(_T_1179, _T_1178)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1180
node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1183 = and(_T_1181, _T_1182)
node _T_1184 = or(UInt<1>(0h0), _T_1183)
node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1191 = cvt(_T_1190)
node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000)))
node _T_1193 = asSInt(_T_1192)
node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0)))
node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1196 = cvt(_T_1195)
node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000)))
node _T_1198 = asSInt(_T_1197)
node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0)))
node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1201 = cvt(_T_1200)
node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000)))
node _T_1203 = asSInt(_T_1202)
node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0)))
node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1206 = cvt(_T_1205)
node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000)))
node _T_1208 = asSInt(_T_1207)
node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0)))
node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1211 = cvt(_T_1210)
node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000)))
node _T_1213 = asSInt(_T_1212)
node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1216 = cvt(_T_1215)
node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000)))
node _T_1218 = asSInt(_T_1217)
node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0)))
node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1221 = cvt(_T_1220)
node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000)))
node _T_1223 = asSInt(_T_1222)
node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0)))
node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1226 = cvt(_T_1225)
node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000)))
node _T_1228 = asSInt(_T_1227)
node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0)))
node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1231 = cvt(_T_1230)
node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000)))
node _T_1233 = asSInt(_T_1232)
node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0)))
node _T_1235 = or(_T_1189, _T_1194)
node _T_1236 = or(_T_1235, _T_1199)
node _T_1237 = or(_T_1236, _T_1204)
node _T_1238 = or(_T_1237, _T_1209)
node _T_1239 = or(_T_1238, _T_1214)
node _T_1240 = or(_T_1239, _T_1219)
node _T_1241 = or(_T_1240, _T_1224)
node _T_1242 = or(_T_1241, _T_1229)
node _T_1243 = or(_T_1242, _T_1234)
node _T_1244 = and(_T_1184, _T_1243)
node _T_1245 = or(UInt<1>(0h0), _T_1244)
node _T_1246 = and(_WIRE_5, _T_1245)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(address_ok, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(legal_source, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1260 = asUInt(reset)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
when _T_1261 :
node _T_1262 = eq(_T_1259, UInt<1>(0h0))
when _T_1262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90
node _T_1263 = eq(io.in.b.bits.mask, mask_1)
node _T_1264 = asUInt(reset)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
when _T_1265 :
node _T_1266 = eq(_T_1263, UInt<1>(0h0))
when _T_1266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91
node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1268 = asUInt(reset)
node _T_1269 = eq(_T_1268, UInt<1>(0h0))
when _T_1269 :
node _T_1270 = eq(_T_1267, UInt<1>(0h0))
when _T_1270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92
node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1271 :
node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = or(UInt<1>(0h0), _T_1274)
node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1277 = cvt(_T_1276)
node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000)))
node _T_1279 = asSInt(_T_1278)
node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0)))
node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1282 = cvt(_T_1281)
node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000)))
node _T_1284 = asSInt(_T_1283)
node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0)))
node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1287 = cvt(_T_1286)
node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000)))
node _T_1289 = asSInt(_T_1288)
node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0)))
node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1292 = cvt(_T_1291)
node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000)))
node _T_1294 = asSInt(_T_1293)
node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0)))
node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1297 = cvt(_T_1296)
node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000)))
node _T_1299 = asSInt(_T_1298)
node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0)))
node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1302 = cvt(_T_1301)
node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000)))
node _T_1304 = asSInt(_T_1303)
node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0)))
node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1307 = cvt(_T_1306)
node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000)))
node _T_1309 = asSInt(_T_1308)
node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0)))
node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1312 = cvt(_T_1311)
node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000)))
node _T_1314 = asSInt(_T_1313)
node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0)))
node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1317 = cvt(_T_1316)
node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000)))
node _T_1319 = asSInt(_T_1318)
node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0)))
node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1322 = cvt(_T_1321)
node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000)))
node _T_1324 = asSInt(_T_1323)
node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0)))
node _T_1326 = or(_T_1280, _T_1285)
node _T_1327 = or(_T_1326, _T_1290)
node _T_1328 = or(_T_1327, _T_1295)
node _T_1329 = or(_T_1328, _T_1300)
node _T_1330 = or(_T_1329, _T_1305)
node _T_1331 = or(_T_1330, _T_1310)
node _T_1332 = or(_T_1331, _T_1315)
node _T_1333 = or(_T_1332, _T_1320)
node _T_1334 = or(_T_1333, _T_1325)
node _T_1335 = and(_T_1275, _T_1334)
node _T_1336 = or(UInt<1>(0h0), _T_1335)
node _T_1337 = and(UInt<1>(0h0), _T_1336)
node _T_1338 = asUInt(reset)
node _T_1339 = eq(_T_1338, UInt<1>(0h0))
when _T_1339 :
node _T_1340 = eq(_T_1337, UInt<1>(0h0))
when _T_1340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(address_ok, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(legal_source, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1347 = asUInt(reset)
node _T_1348 = eq(_T_1347, UInt<1>(0h0))
when _T_1348 :
node _T_1349 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97
node _T_1354 = eq(io.in.b.bits.mask, mask_1)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98
node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99
node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1365 = and(_T_1363, _T_1364)
node _T_1366 = or(UInt<1>(0h0), _T_1365)
node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1368 = cvt(_T_1367)
node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000)))
node _T_1370 = asSInt(_T_1369)
node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0)))
node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1373 = cvt(_T_1372)
node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000)))
node _T_1375 = asSInt(_T_1374)
node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0)))
node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1378 = cvt(_T_1377)
node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000)))
node _T_1380 = asSInt(_T_1379)
node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0)))
node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1383 = cvt(_T_1382)
node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000)))
node _T_1385 = asSInt(_T_1384)
node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0)))
node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1388 = cvt(_T_1387)
node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000)))
node _T_1390 = asSInt(_T_1389)
node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0)))
node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1393 = cvt(_T_1392)
node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000)))
node _T_1395 = asSInt(_T_1394)
node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0)))
node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1398 = cvt(_T_1397)
node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000)))
node _T_1400 = asSInt(_T_1399)
node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0)))
node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1403 = cvt(_T_1402)
node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000)))
node _T_1405 = asSInt(_T_1404)
node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0)))
node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1408 = cvt(_T_1407)
node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000)))
node _T_1410 = asSInt(_T_1409)
node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0)))
node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1413 = cvt(_T_1412)
node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000)))
node _T_1415 = asSInt(_T_1414)
node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0)))
node _T_1417 = or(_T_1371, _T_1376)
node _T_1418 = or(_T_1417, _T_1381)
node _T_1419 = or(_T_1418, _T_1386)
node _T_1420 = or(_T_1419, _T_1391)
node _T_1421 = or(_T_1420, _T_1396)
node _T_1422 = or(_T_1421, _T_1401)
node _T_1423 = or(_T_1422, _T_1406)
node _T_1424 = or(_T_1423, _T_1411)
node _T_1425 = or(_T_1424, _T_1416)
node _T_1426 = and(_T_1366, _T_1425)
node _T_1427 = or(UInt<1>(0h0), _T_1426)
node _T_1428 = and(UInt<1>(0h0), _T_1427)
node _T_1429 = asUInt(reset)
node _T_1430 = eq(_T_1429, UInt<1>(0h0))
when _T_1430 :
node _T_1431 = eq(_T_1428, UInt<1>(0h0))
when _T_1431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(address_ok, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1435 = asUInt(reset)
node _T_1436 = eq(_T_1435, UInt<1>(0h0))
when _T_1436 :
node _T_1437 = eq(legal_source, UInt<1>(0h0))
when _T_1437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1438 = asUInt(reset)
node _T_1439 = eq(_T_1438, UInt<1>(0h0))
when _T_1439 :
node _T_1440 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104
node _T_1445 = eq(io.in.b.bits.mask, mask_1)
node _T_1446 = asUInt(reset)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = eq(_T_1445, UInt<1>(0h0))
when _T_1448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105
node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1449 :
node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1452 = and(_T_1450, _T_1451)
node _T_1453 = or(UInt<1>(0h0), _T_1452)
node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1455 = cvt(_T_1454)
node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000)))
node _T_1457 = asSInt(_T_1456)
node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0)))
node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1460 = cvt(_T_1459)
node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000)))
node _T_1462 = asSInt(_T_1461)
node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0)))
node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1465 = cvt(_T_1464)
node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000)))
node _T_1467 = asSInt(_T_1466)
node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0)))
node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1470 = cvt(_T_1469)
node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000)))
node _T_1472 = asSInt(_T_1471)
node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0)))
node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1475 = cvt(_T_1474)
node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000)))
node _T_1477 = asSInt(_T_1476)
node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0)))
node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1480 = cvt(_T_1479)
node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000)))
node _T_1482 = asSInt(_T_1481)
node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0)))
node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1485 = cvt(_T_1484)
node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000)))
node _T_1487 = asSInt(_T_1486)
node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0)))
node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1490 = cvt(_T_1489)
node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000)))
node _T_1492 = asSInt(_T_1491)
node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0)))
node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1495 = cvt(_T_1494)
node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000)))
node _T_1497 = asSInt(_T_1496)
node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0)))
node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1500 = cvt(_T_1499)
node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000)))
node _T_1502 = asSInt(_T_1501)
node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0)))
node _T_1504 = or(_T_1458, _T_1463)
node _T_1505 = or(_T_1504, _T_1468)
node _T_1506 = or(_T_1505, _T_1473)
node _T_1507 = or(_T_1506, _T_1478)
node _T_1508 = or(_T_1507, _T_1483)
node _T_1509 = or(_T_1508, _T_1488)
node _T_1510 = or(_T_1509, _T_1493)
node _T_1511 = or(_T_1510, _T_1498)
node _T_1512 = or(_T_1511, _T_1503)
node _T_1513 = and(_T_1453, _T_1512)
node _T_1514 = or(UInt<1>(0h0), _T_1513)
node _T_1515 = and(UInt<1>(0h0), _T_1514)
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(address_ok, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1522 = asUInt(reset)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
when _T_1523 :
node _T_1524 = eq(legal_source, UInt<1>(0h0))
when _T_1524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1529 = asUInt(reset)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
when _T_1530 :
node _T_1531 = eq(_T_1528, UInt<1>(0h0))
when _T_1531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110
node _T_1532 = not(mask_1)
node _T_1533 = and(io.in.b.bits.mask, _T_1532)
node _T_1534 = eq(_T_1533, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111
node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1538 :
node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1541 = and(_T_1539, _T_1540)
node _T_1542 = or(UInt<1>(0h0), _T_1541)
node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1544 = cvt(_T_1543)
node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000)))
node _T_1546 = asSInt(_T_1545)
node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0)))
node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1549 = cvt(_T_1548)
node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000)))
node _T_1551 = asSInt(_T_1550)
node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0)))
node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1554 = cvt(_T_1553)
node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000)))
node _T_1556 = asSInt(_T_1555)
node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0)))
node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1559 = cvt(_T_1558)
node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000)))
node _T_1561 = asSInt(_T_1560)
node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0)))
node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1564 = cvt(_T_1563)
node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000)))
node _T_1566 = asSInt(_T_1565)
node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0)))
node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1569 = cvt(_T_1568)
node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000)))
node _T_1571 = asSInt(_T_1570)
node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1574 = cvt(_T_1573)
node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000)))
node _T_1576 = asSInt(_T_1575)
node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0)))
node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1579 = cvt(_T_1578)
node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000)))
node _T_1581 = asSInt(_T_1580)
node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0)))
node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1584 = cvt(_T_1583)
node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000)))
node _T_1586 = asSInt(_T_1585)
node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0)))
node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1589 = cvt(_T_1588)
node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000)))
node _T_1591 = asSInt(_T_1590)
node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0)))
node _T_1593 = or(_T_1547, _T_1552)
node _T_1594 = or(_T_1593, _T_1557)
node _T_1595 = or(_T_1594, _T_1562)
node _T_1596 = or(_T_1595, _T_1567)
node _T_1597 = or(_T_1596, _T_1572)
node _T_1598 = or(_T_1597, _T_1577)
node _T_1599 = or(_T_1598, _T_1582)
node _T_1600 = or(_T_1599, _T_1587)
node _T_1601 = or(_T_1600, _T_1592)
node _T_1602 = and(_T_1542, _T_1601)
node _T_1603 = or(UInt<1>(0h0), _T_1602)
node _T_1604 = and(UInt<1>(0h0), _T_1603)
node _T_1605 = asUInt(reset)
node _T_1606 = eq(_T_1605, UInt<1>(0h0))
when _T_1606 :
node _T_1607 = eq(_T_1604, UInt<1>(0h0))
when _T_1607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(address_ok, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(legal_source, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1614 = asUInt(reset)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
when _T_1615 :
node _T_1616 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1618 = asUInt(reset)
node _T_1619 = eq(_T_1618, UInt<1>(0h0))
when _T_1619 :
node _T_1620 = eq(_T_1617, UInt<1>(0h0))
when _T_1620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116
node _T_1621 = eq(io.in.b.bits.mask, mask_1)
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117
node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1625 :
node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1628 = and(_T_1626, _T_1627)
node _T_1629 = or(UInt<1>(0h0), _T_1628)
node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1631 = cvt(_T_1630)
node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000)))
node _T_1633 = asSInt(_T_1632)
node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0)))
node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1636 = cvt(_T_1635)
node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000)))
node _T_1638 = asSInt(_T_1637)
node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0)))
node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1641 = cvt(_T_1640)
node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000)))
node _T_1643 = asSInt(_T_1642)
node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0)))
node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1646 = cvt(_T_1645)
node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000)))
node _T_1648 = asSInt(_T_1647)
node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0)))
node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1651 = cvt(_T_1650)
node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000)))
node _T_1653 = asSInt(_T_1652)
node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0)))
node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1656 = cvt(_T_1655)
node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000)))
node _T_1658 = asSInt(_T_1657)
node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0)))
node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1661 = cvt(_T_1660)
node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000)))
node _T_1663 = asSInt(_T_1662)
node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0)))
node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1666 = cvt(_T_1665)
node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000)))
node _T_1668 = asSInt(_T_1667)
node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0)))
node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1671 = cvt(_T_1670)
node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000)))
node _T_1673 = asSInt(_T_1672)
node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0)))
node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1676 = cvt(_T_1675)
node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000)))
node _T_1678 = asSInt(_T_1677)
node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0)))
node _T_1680 = or(_T_1634, _T_1639)
node _T_1681 = or(_T_1680, _T_1644)
node _T_1682 = or(_T_1681, _T_1649)
node _T_1683 = or(_T_1682, _T_1654)
node _T_1684 = or(_T_1683, _T_1659)
node _T_1685 = or(_T_1684, _T_1664)
node _T_1686 = or(_T_1685, _T_1669)
node _T_1687 = or(_T_1686, _T_1674)
node _T_1688 = or(_T_1687, _T_1679)
node _T_1689 = and(_T_1629, _T_1688)
node _T_1690 = or(UInt<1>(0h0), _T_1689)
node _T_1691 = and(UInt<1>(0h0), _T_1690)
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118
node _T_1695 = asUInt(reset)
node _T_1696 = eq(_T_1695, UInt<1>(0h0))
when _T_1696 :
node _T_1697 = eq(address_ok, UInt<1>(0h0))
when _T_1697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1698 = asUInt(reset)
node _T_1699 = eq(_T_1698, UInt<1>(0h0))
when _T_1699 :
node _T_1700 = eq(legal_source, UInt<1>(0h0))
when _T_1700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1701 = asUInt(reset)
node _T_1702 = eq(_T_1701, UInt<1>(0h0))
when _T_1702 :
node _T_1703 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1705 = asUInt(reset)
node _T_1706 = eq(_T_1705, UInt<1>(0h0))
when _T_1706 :
node _T_1707 = eq(_T_1704, UInt<1>(0h0))
when _T_1707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122
node _T_1708 = eq(io.in.b.bits.mask, mask_1)
node _T_1709 = asUInt(reset)
node _T_1710 = eq(_T_1709, UInt<1>(0h0))
when _T_1710 :
node _T_1711 = eq(_T_1708, UInt<1>(0h0))
when _T_1711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123
node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1712 :
node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1715 = and(_T_1713, _T_1714)
node _T_1716 = or(UInt<1>(0h0), _T_1715)
node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1718 = cvt(_T_1717)
node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000)))
node _T_1720 = asSInt(_T_1719)
node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0)))
node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1723 = cvt(_T_1722)
node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000)))
node _T_1725 = asSInt(_T_1724)
node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0)))
node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1728 = cvt(_T_1727)
node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000)))
node _T_1730 = asSInt(_T_1729)
node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0)))
node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1733 = cvt(_T_1732)
node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000)))
node _T_1735 = asSInt(_T_1734)
node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0)))
node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1738 = cvt(_T_1737)
node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000)))
node _T_1740 = asSInt(_T_1739)
node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0)))
node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1743 = cvt(_T_1742)
node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000)))
node _T_1745 = asSInt(_T_1744)
node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0)))
node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1748 = cvt(_T_1747)
node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000)))
node _T_1750 = asSInt(_T_1749)
node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0)))
node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1753 = cvt(_T_1752)
node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000)))
node _T_1755 = asSInt(_T_1754)
node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0)))
node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1758 = cvt(_T_1757)
node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000)))
node _T_1760 = asSInt(_T_1759)
node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0)))
node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1763 = cvt(_T_1762)
node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000)))
node _T_1765 = asSInt(_T_1764)
node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0)))
node _T_1767 = or(_T_1721, _T_1726)
node _T_1768 = or(_T_1767, _T_1731)
node _T_1769 = or(_T_1768, _T_1736)
node _T_1770 = or(_T_1769, _T_1741)
node _T_1771 = or(_T_1770, _T_1746)
node _T_1772 = or(_T_1771, _T_1751)
node _T_1773 = or(_T_1772, _T_1756)
node _T_1774 = or(_T_1773, _T_1761)
node _T_1775 = or(_T_1774, _T_1766)
node _T_1776 = and(_T_1716, _T_1775)
node _T_1777 = or(UInt<1>(0h0), _T_1776)
node _T_1778 = and(UInt<1>(0h0), _T_1777)
node _T_1779 = asUInt(reset)
node _T_1780 = eq(_T_1779, UInt<1>(0h0))
when _T_1780 :
node _T_1781 = eq(_T_1778, UInt<1>(0h0))
when _T_1781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(address_ok, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1785 = asUInt(reset)
node _T_1786 = eq(_T_1785, UInt<1>(0h0))
when _T_1786 :
node _T_1787 = eq(legal_source, UInt<1>(0h0))
when _T_1787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1791 = eq(io.in.b.bits.mask, mask_1)
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128
node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130
node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_2 : UInt<1>[3]
connect _source_ok_WIRE_2[0], _source_ok_T_8
connect _source_ok_WIRE_2[1], _source_ok_T_9
connect _source_ok_WIRE_2[2], _source_ok_T_10
node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1806 = cvt(_T_1805)
node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0)))
node _T_1808 = asSInt(_T_1807)
node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0)))
node _T_1810 = or(_T_1804, _T_1809)
node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1812 = eq(_T_1811, UInt<1>(0h0))
node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1814 = cvt(_T_1813)
node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0)))
node _T_1816 = asSInt(_T_1815)
node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0)))
node _T_1818 = or(_T_1812, _T_1817)
node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1820 = eq(_T_1819, UInt<1>(0h0))
node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1822 = cvt(_T_1821)
node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0)))
node _T_1824 = asSInt(_T_1823)
node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0)))
node _T_1826 = or(_T_1820, _T_1825)
node _T_1827 = and(_T_1810, _T_1818)
node _T_1828 = and(_T_1827, _T_1826)
node _T_1829 = asUInt(reset)
node _T_1830 = eq(_T_1829, UInt<1>(0h0))
when _T_1830 :
node _T_1831 = eq(_T_1828, UInt<1>(0h0))
when _T_1831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131
node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1832 :
node _T_1833 = asUInt(reset)
node _T_1834 = eq(_T_1833, UInt<1>(0h0))
when _T_1834 :
node _T_1835 = eq(address_ok_1, UInt<1>(0h0))
when _T_1835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1836 = asUInt(reset)
node _T_1837 = eq(_T_1836, UInt<1>(0h0))
when _T_1837 :
node _T_1838 = eq(source_ok_2, UInt<1>(0h0))
when _T_1838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1840 = asUInt(reset)
node _T_1841 = eq(_T_1840, UInt<1>(0h0))
when _T_1841 :
node _T_1842 = eq(_T_1839, UInt<1>(0h0))
when _T_1842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134
node _T_1843 = asUInt(reset)
node _T_1844 = eq(_T_1843, UInt<1>(0h0))
when _T_1844 :
node _T_1845 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(_T_1846, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136
node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1851 = asUInt(reset)
node _T_1852 = eq(_T_1851, UInt<1>(0h0))
when _T_1852 :
node _T_1853 = eq(_T_1850, UInt<1>(0h0))
when _T_1853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137
node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1854 :
node _T_1855 = asUInt(reset)
node _T_1856 = eq(_T_1855, UInt<1>(0h0))
when _T_1856 :
node _T_1857 = eq(address_ok_1, UInt<1>(0h0))
when _T_1857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1858 = asUInt(reset)
node _T_1859 = eq(_T_1858, UInt<1>(0h0))
when _T_1859 :
node _T_1860 = eq(source_ok_2, UInt<1>(0h0))
when _T_1860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1862 = asUInt(reset)
node _T_1863 = eq(_T_1862, UInt<1>(0h0))
when _T_1863 :
node _T_1864 = eq(_T_1861, UInt<1>(0h0))
when _T_1864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1869 = asUInt(reset)
node _T_1870 = eq(_T_1869, UInt<1>(0h0))
when _T_1870 :
node _T_1871 = eq(_T_1868, UInt<1>(0h0))
when _T_1871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142
node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1872 :
node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1875 = and(_T_1873, _T_1874)
node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1879 = or(_T_1876, _T_1877)
node _T_1880 = or(_T_1879, _T_1878)
node _T_1881 = and(_T_1875, _T_1880)
node _T_1882 = or(UInt<1>(0h0), _T_1881)
node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1885 = cvt(_T_1884)
node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000)))
node _T_1887 = asSInt(_T_1886)
node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0)))
node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1890 = cvt(_T_1889)
node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000)))
node _T_1892 = asSInt(_T_1891)
node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1895 = cvt(_T_1894)
node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000)))
node _T_1897 = asSInt(_T_1896)
node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0)))
node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1900 = cvt(_T_1899)
node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000)))
node _T_1902 = asSInt(_T_1901)
node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0)))
node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1905 = cvt(_T_1904)
node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000)))
node _T_1907 = asSInt(_T_1906)
node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0)))
node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1910 = cvt(_T_1909)
node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000)))
node _T_1912 = asSInt(_T_1911)
node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0)))
node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1915 = cvt(_T_1914)
node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000)))
node _T_1917 = asSInt(_T_1916)
node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0)))
node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1920 = cvt(_T_1919)
node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000)))
node _T_1922 = asSInt(_T_1921)
node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0)))
node _T_1924 = or(_T_1888, _T_1893)
node _T_1925 = or(_T_1924, _T_1898)
node _T_1926 = or(_T_1925, _T_1903)
node _T_1927 = or(_T_1926, _T_1908)
node _T_1928 = or(_T_1927, _T_1913)
node _T_1929 = or(_T_1928, _T_1918)
node _T_1930 = or(_T_1929, _T_1923)
node _T_1931 = and(_T_1883, _T_1930)
node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1933 = or(UInt<1>(0h0), _T_1932)
node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1935 = cvt(_T_1934)
node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000)))
node _T_1937 = asSInt(_T_1936)
node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0)))
node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1940 = cvt(_T_1939)
node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000)))
node _T_1942 = asSInt(_T_1941)
node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0)))
node _T_1944 = or(_T_1938, _T_1943)
node _T_1945 = and(_T_1933, _T_1944)
node _T_1946 = or(UInt<1>(0h0), _T_1931)
node _T_1947 = or(_T_1946, _T_1945)
node _T_1948 = and(_T_1882, _T_1947)
node _T_1949 = asUInt(reset)
node _T_1950 = eq(_T_1949, UInt<1>(0h0))
when _T_1950 :
node _T_1951 = eq(_T_1948, UInt<1>(0h0))
when _T_1951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143
node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_6 : UInt<1>[3]
connect _WIRE_6[0], _T_1952
connect _WIRE_6[1], _T_1953
connect _WIRE_6[2], _T_1954
node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0))
node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1959 = or(_T_1956, _T_1957)
node _T_1960 = or(_T_1959, _T_1958)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1960
node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1963 = and(_T_1961, _T_1962)
node _T_1964 = or(UInt<1>(0h0), _T_1963)
node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1966 = cvt(_T_1965)
node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000)))
node _T_1968 = asSInt(_T_1967)
node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0)))
node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1971 = cvt(_T_1970)
node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000)))
node _T_1973 = asSInt(_T_1972)
node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0)))
node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1976 = cvt(_T_1975)
node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000)))
node _T_1978 = asSInt(_T_1977)
node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0)))
node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1981 = cvt(_T_1980)
node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000)))
node _T_1983 = asSInt(_T_1982)
node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0)))
node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1986 = cvt(_T_1985)
node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000)))
node _T_1988 = asSInt(_T_1987)
node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0)))
node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1991 = cvt(_T_1990)
node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000)))
node _T_1993 = asSInt(_T_1992)
node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0)))
node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1996 = cvt(_T_1995)
node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000)))
node _T_1998 = asSInt(_T_1997)
node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0)))
node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2001 = cvt(_T_2000)
node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000)))
node _T_2003 = asSInt(_T_2002)
node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0)))
node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2006 = cvt(_T_2005)
node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000)))
node _T_2008 = asSInt(_T_2007)
node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0)))
node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2011 = cvt(_T_2010)
node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000)))
node _T_2013 = asSInt(_T_2012)
node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0)))
node _T_2015 = or(_T_1969, _T_1974)
node _T_2016 = or(_T_2015, _T_1979)
node _T_2017 = or(_T_2016, _T_1984)
node _T_2018 = or(_T_2017, _T_1989)
node _T_2019 = or(_T_2018, _T_1994)
node _T_2020 = or(_T_2019, _T_1999)
node _T_2021 = or(_T_2020, _T_2004)
node _T_2022 = or(_T_2021, _T_2009)
node _T_2023 = or(_T_2022, _T_2014)
node _T_2024 = and(_T_1964, _T_2023)
node _T_2025 = or(UInt<1>(0h0), _T_2024)
node _T_2026 = and(_WIRE_7, _T_2025)
node _T_2027 = asUInt(reset)
node _T_2028 = eq(_T_2027, UInt<1>(0h0))
when _T_2028 :
node _T_2029 = eq(_T_2026, UInt<1>(0h0))
when _T_2029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144
node _T_2030 = asUInt(reset)
node _T_2031 = eq(_T_2030, UInt<1>(0h0))
when _T_2031 :
node _T_2032 = eq(source_ok_2, UInt<1>(0h0))
when _T_2032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2034 = asUInt(reset)
node _T_2035 = eq(_T_2034, UInt<1>(0h0))
when _T_2035 :
node _T_2036 = eq(_T_2033, UInt<1>(0h0))
when _T_2036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146
node _T_2037 = asUInt(reset)
node _T_2038 = eq(_T_2037, UInt<1>(0h0))
when _T_2038 :
node _T_2039 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2041 = asUInt(reset)
node _T_2042 = eq(_T_2041, UInt<1>(0h0))
when _T_2042 :
node _T_2043 = eq(_T_2040, UInt<1>(0h0))
when _T_2043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148
node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2045 = asUInt(reset)
node _T_2046 = eq(_T_2045, UInt<1>(0h0))
when _T_2046 :
node _T_2047 = eq(_T_2044, UInt<1>(0h0))
when _T_2047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149
node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2048 :
node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2051 = and(_T_2049, _T_2050)
node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2055 = or(_T_2052, _T_2053)
node _T_2056 = or(_T_2055, _T_2054)
node _T_2057 = and(_T_2051, _T_2056)
node _T_2058 = or(UInt<1>(0h0), _T_2057)
node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2066 = cvt(_T_2065)
node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000)))
node _T_2068 = asSInt(_T_2067)
node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0)))
node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2076 = cvt(_T_2075)
node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000)))
node _T_2078 = asSInt(_T_2077)
node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0)))
node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2081 = cvt(_T_2080)
node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000)))
node _T_2083 = asSInt(_T_2082)
node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0)))
node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2086 = cvt(_T_2085)
node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000)))
node _T_2088 = asSInt(_T_2087)
node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0)))
node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2091 = cvt(_T_2090)
node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000)))
node _T_2093 = asSInt(_T_2092)
node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0)))
node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2096 = cvt(_T_2095)
node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000)))
node _T_2098 = asSInt(_T_2097)
node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0)))
node _T_2100 = or(_T_2064, _T_2069)
node _T_2101 = or(_T_2100, _T_2074)
node _T_2102 = or(_T_2101, _T_2079)
node _T_2103 = or(_T_2102, _T_2084)
node _T_2104 = or(_T_2103, _T_2089)
node _T_2105 = or(_T_2104, _T_2094)
node _T_2106 = or(_T_2105, _T_2099)
node _T_2107 = and(_T_2059, _T_2106)
node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2109 = or(UInt<1>(0h0), _T_2108)
node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2111 = cvt(_T_2110)
node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000)))
node _T_2113 = asSInt(_T_2112)
node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0)))
node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2116 = cvt(_T_2115)
node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000)))
node _T_2118 = asSInt(_T_2117)
node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0)))
node _T_2120 = or(_T_2114, _T_2119)
node _T_2121 = and(_T_2109, _T_2120)
node _T_2122 = or(UInt<1>(0h0), _T_2107)
node _T_2123 = or(_T_2122, _T_2121)
node _T_2124 = and(_T_2058, _T_2123)
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(_T_2124, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150
node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_8 : UInt<1>[3]
connect _WIRE_8[0], _T_2128
connect _WIRE_8[1], _T_2129
connect _WIRE_8[2], _T_2130
node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0))
node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2135 = or(_T_2132, _T_2133)
node _T_2136 = or(_T_2135, _T_2134)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2136
node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2139 = and(_T_2137, _T_2138)
node _T_2140 = or(UInt<1>(0h0), _T_2139)
node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2142 = cvt(_T_2141)
node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000)))
node _T_2144 = asSInt(_T_2143)
node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0)))
node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2147 = cvt(_T_2146)
node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000)))
node _T_2149 = asSInt(_T_2148)
node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0)))
node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2152 = cvt(_T_2151)
node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000)))
node _T_2154 = asSInt(_T_2153)
node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0)))
node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2157 = cvt(_T_2156)
node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000)))
node _T_2159 = asSInt(_T_2158)
node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0)))
node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2162 = cvt(_T_2161)
node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000)))
node _T_2164 = asSInt(_T_2163)
node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0)))
node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2167 = cvt(_T_2166)
node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000)))
node _T_2169 = asSInt(_T_2168)
node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0)))
node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2172 = cvt(_T_2171)
node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000)))
node _T_2174 = asSInt(_T_2173)
node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0)))
node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2177 = cvt(_T_2176)
node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000)))
node _T_2179 = asSInt(_T_2178)
node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0)))
node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2182 = cvt(_T_2181)
node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000)))
node _T_2184 = asSInt(_T_2183)
node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0)))
node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2187 = cvt(_T_2186)
node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000)))
node _T_2189 = asSInt(_T_2188)
node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0)))
node _T_2191 = or(_T_2145, _T_2150)
node _T_2192 = or(_T_2191, _T_2155)
node _T_2193 = or(_T_2192, _T_2160)
node _T_2194 = or(_T_2193, _T_2165)
node _T_2195 = or(_T_2194, _T_2170)
node _T_2196 = or(_T_2195, _T_2175)
node _T_2197 = or(_T_2196, _T_2180)
node _T_2198 = or(_T_2197, _T_2185)
node _T_2199 = or(_T_2198, _T_2190)
node _T_2200 = and(_T_2140, _T_2199)
node _T_2201 = or(UInt<1>(0h0), _T_2200)
node _T_2202 = and(_WIRE_9, _T_2201)
node _T_2203 = asUInt(reset)
node _T_2204 = eq(_T_2203, UInt<1>(0h0))
when _T_2204 :
node _T_2205 = eq(_T_2202, UInt<1>(0h0))
when _T_2205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
node _T_2208 = eq(source_ok_2, UInt<1>(0h0))
when _T_2208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153
node _T_2213 = asUInt(reset)
node _T_2214 = eq(_T_2213, UInt<1>(0h0))
when _T_2214 :
node _T_2215 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2217 = asUInt(reset)
node _T_2218 = eq(_T_2217, UInt<1>(0h0))
when _T_2218 :
node _T_2219 = eq(_T_2216, UInt<1>(0h0))
when _T_2219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155
node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2220 :
node _T_2221 = asUInt(reset)
node _T_2222 = eq(_T_2221, UInt<1>(0h0))
when _T_2222 :
node _T_2223 = eq(address_ok_1, UInt<1>(0h0))
when _T_2223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
node _T_2226 = eq(source_ok_2, UInt<1>(0h0))
when _T_2226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2227 = asUInt(reset)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
when _T_2228 :
node _T_2229 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2231 = asUInt(reset)
node _T_2232 = eq(_T_2231, UInt<1>(0h0))
when _T_2232 :
node _T_2233 = eq(_T_2230, UInt<1>(0h0))
when _T_2233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159
node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2235 = asUInt(reset)
node _T_2236 = eq(_T_2235, UInt<1>(0h0))
when _T_2236 :
node _T_2237 = eq(_T_2234, UInt<1>(0h0))
when _T_2237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160
node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2238 :
node _T_2239 = asUInt(reset)
node _T_2240 = eq(_T_2239, UInt<1>(0h0))
when _T_2240 :
node _T_2241 = eq(address_ok_1, UInt<1>(0h0))
when _T_2241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
node _T_2244 = eq(source_ok_2, UInt<1>(0h0))
when _T_2244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2245 = asUInt(reset)
node _T_2246 = eq(_T_2245, UInt<1>(0h0))
when _T_2246 :
node _T_2247 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2249 = asUInt(reset)
node _T_2250 = eq(_T_2249, UInt<1>(0h0))
when _T_2250 :
node _T_2251 = eq(_T_2248, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164
node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2252 :
node _T_2253 = asUInt(reset)
node _T_2254 = eq(_T_2253, UInt<1>(0h0))
when _T_2254 :
node _T_2255 = eq(address_ok_1, UInt<1>(0h0))
when _T_2255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2256 = asUInt(reset)
node _T_2257 = eq(_T_2256, UInt<1>(0h0))
when _T_2257 :
node _T_2258 = eq(source_ok_2, UInt<1>(0h0))
when _T_2258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2259 = asUInt(reset)
node _T_2260 = eq(_T_2259, UInt<1>(0h0))
when _T_2260 :
node _T_2261 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2263 = asUInt(reset)
node _T_2264 = eq(_T_2263, UInt<1>(0h0))
when _T_2264 :
node _T_2265 = eq(_T_2262, UInt<1>(0h0))
when _T_2265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168
node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2267 = asUInt(reset)
node _T_2268 = eq(_T_2267, UInt<1>(0h0))
when _T_2268 :
node _T_2269 = eq(_T_2266, UInt<1>(0h0))
when _T_2269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
node _T_2272 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2273 = eq(a_first, UInt<1>(0h0))
node _T_2274 = and(io.in.a.valid, _T_2273)
when _T_2274 :
node _T_2275 = eq(io.in.a.bits.opcode, opcode)
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
node _T_2278 = eq(_T_2275, UInt<1>(0h0))
when _T_2278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171
node _T_2279 = eq(io.in.a.bits.param, param)
node _T_2280 = asUInt(reset)
node _T_2281 = eq(_T_2280, UInt<1>(0h0))
when _T_2281 :
node _T_2282 = eq(_T_2279, UInt<1>(0h0))
when _T_2282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172
node _T_2283 = eq(io.in.a.bits.size, size)
node _T_2284 = asUInt(reset)
node _T_2285 = eq(_T_2284, UInt<1>(0h0))
when _T_2285 :
node _T_2286 = eq(_T_2283, UInt<1>(0h0))
when _T_2286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173
node _T_2287 = eq(io.in.a.bits.source, source)
node _T_2288 = asUInt(reset)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
when _T_2289 :
node _T_2290 = eq(_T_2287, UInt<1>(0h0))
when _T_2290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174
node _T_2291 = eq(io.in.a.bits.address, address)
node _T_2292 = asUInt(reset)
node _T_2293 = eq(_T_2292, UInt<1>(0h0))
when _T_2293 :
node _T_2294 = eq(_T_2291, UInt<1>(0h0))
when _T_2294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175
node _T_2295 = and(io.in.a.ready, io.in.a.valid)
node _T_2296 = and(_T_2295, a_first)
when _T_2296 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2297 = eq(d_first, UInt<1>(0h0))
node _T_2298 = and(io.in.d.valid, _T_2297)
when _T_2298 :
node _T_2299 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176
node _T_2303 = eq(io.in.d.bits.param, param_1)
node _T_2304 = asUInt(reset)
node _T_2305 = eq(_T_2304, UInt<1>(0h0))
when _T_2305 :
node _T_2306 = eq(_T_2303, UInt<1>(0h0))
when _T_2306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177
node _T_2307 = eq(io.in.d.bits.size, size_1)
node _T_2308 = asUInt(reset)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
when _T_2309 :
node _T_2310 = eq(_T_2307, UInt<1>(0h0))
when _T_2310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178
node _T_2311 = eq(io.in.d.bits.source, source_1)
node _T_2312 = asUInt(reset)
node _T_2313 = eq(_T_2312, UInt<1>(0h0))
when _T_2313 :
node _T_2314 = eq(_T_2311, UInt<1>(0h0))
when _T_2314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179
node _T_2315 = eq(io.in.d.bits.sink, sink)
node _T_2316 = asUInt(reset)
node _T_2317 = eq(_T_2316, UInt<1>(0h0))
when _T_2317 :
node _T_2318 = eq(_T_2315, UInt<1>(0h0))
when _T_2318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180
node _T_2319 = eq(io.in.d.bits.denied, denied)
node _T_2320 = asUInt(reset)
node _T_2321 = eq(_T_2320, UInt<1>(0h0))
when _T_2321 :
node _T_2322 = eq(_T_2319, UInt<1>(0h0))
when _T_2322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181
node _T_2323 = and(io.in.d.ready, io.in.d.valid)
node _T_2324 = and(_T_2323, d_first)
when _T_2324 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2325 = eq(b_first, UInt<1>(0h0))
node _T_2326 = and(io.in.b.valid, _T_2325)
when _T_2326 :
node _T_2327 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2328 = asUInt(reset)
node _T_2329 = eq(_T_2328, UInt<1>(0h0))
when _T_2329 :
node _T_2330 = eq(_T_2327, UInt<1>(0h0))
when _T_2330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182
node _T_2331 = eq(io.in.b.bits.param, param_2)
node _T_2332 = asUInt(reset)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
when _T_2333 :
node _T_2334 = eq(_T_2331, UInt<1>(0h0))
when _T_2334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183
node _T_2335 = eq(io.in.b.bits.size, size_2)
node _T_2336 = asUInt(reset)
node _T_2337 = eq(_T_2336, UInt<1>(0h0))
when _T_2337 :
node _T_2338 = eq(_T_2335, UInt<1>(0h0))
when _T_2338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184
node _T_2339 = eq(io.in.b.bits.source, source_2)
node _T_2340 = asUInt(reset)
node _T_2341 = eq(_T_2340, UInt<1>(0h0))
when _T_2341 :
node _T_2342 = eq(_T_2339, UInt<1>(0h0))
when _T_2342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185
node _T_2343 = eq(io.in.b.bits.address, address_1)
node _T_2344 = asUInt(reset)
node _T_2345 = eq(_T_2344, UInt<1>(0h0))
when _T_2345 :
node _T_2346 = eq(_T_2343, UInt<1>(0h0))
when _T_2346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186
node _T_2347 = and(io.in.b.ready, io.in.b.valid)
node _T_2348 = and(_T_2347, b_first)
when _T_2348 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2349 = eq(c_first, UInt<1>(0h0))
node _T_2350 = and(io.in.c.valid, _T_2349)
when _T_2350 :
node _T_2351 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2352 = asUInt(reset)
node _T_2353 = eq(_T_2352, UInt<1>(0h0))
when _T_2353 :
node _T_2354 = eq(_T_2351, UInt<1>(0h0))
when _T_2354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187
node _T_2355 = eq(io.in.c.bits.param, param_3)
node _T_2356 = asUInt(reset)
node _T_2357 = eq(_T_2356, UInt<1>(0h0))
when _T_2357 :
node _T_2358 = eq(_T_2355, UInt<1>(0h0))
when _T_2358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188
node _T_2359 = eq(io.in.c.bits.size, size_3)
node _T_2360 = asUInt(reset)
node _T_2361 = eq(_T_2360, UInt<1>(0h0))
when _T_2361 :
node _T_2362 = eq(_T_2359, UInt<1>(0h0))
when _T_2362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189
node _T_2363 = eq(io.in.c.bits.source, source_3)
node _T_2364 = asUInt(reset)
node _T_2365 = eq(_T_2364, UInt<1>(0h0))
when _T_2365 :
node _T_2366 = eq(_T_2363, UInt<1>(0h0))
when _T_2366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190
node _T_2367 = eq(io.in.c.bits.address, address_2)
node _T_2368 = asUInt(reset)
node _T_2369 = eq(_T_2368, UInt<1>(0h0))
when _T_2369 :
node _T_2370 = eq(_T_2367, UInt<1>(0h0))
when _T_2370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191
node _T_2371 = and(io.in.c.ready, io.in.c.valid)
node _T_2372 = and(_T_2371, c_first)
when _T_2372 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<3>
connect a_set, UInt<3>(0h0)
wire a_set_wo_ready : UInt<3>
connect a_set_wo_ready, UInt<3>(0h0)
wire a_opcodes_set : UInt<12>
connect a_opcodes_set, UInt<12>(0h0)
wire a_sizes_set : UInt<24>
connect a_sizes_set, UInt<24>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2373 = and(io.in.a.valid, a_first_1)
node _T_2374 = and(_T_2373, UInt<1>(0h1))
when _T_2374 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2375 = and(io.in.a.ready, io.in.a.valid)
node _T_2376 = and(_T_2375, a_first_1)
node _T_2377 = and(_T_2376, UInt<1>(0h1))
when _T_2377 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2378 = dshr(inflight, io.in.a.bits.source)
node _T_2379 = bits(_T_2378, 0, 0)
node _T_2380 = eq(_T_2379, UInt<1>(0h0))
node _T_2381 = asUInt(reset)
node _T_2382 = eq(_T_2381, UInt<1>(0h0))
when _T_2382 :
node _T_2383 = eq(_T_2380, UInt<1>(0h0))
when _T_2383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<3>
connect d_clr, UInt<3>(0h0)
wire d_clr_wo_ready : UInt<3>
connect d_clr_wo_ready, UInt<3>(0h0)
wire d_opcodes_clr : UInt<12>
connect d_opcodes_clr, UInt<12>(0h0)
wire d_sizes_clr : UInt<24>
connect d_sizes_clr, UInt<24>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2384 = and(io.in.d.valid, d_first_1)
node _T_2385 = and(_T_2384, UInt<1>(0h1))
node _T_2386 = eq(d_release_ack, UInt<1>(0h0))
node _T_2387 = and(_T_2385, _T_2386)
when _T_2387 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2388 = and(io.in.d.ready, io.in.d.valid)
node _T_2389 = and(_T_2388, d_first_1)
node _T_2390 = and(_T_2389, UInt<1>(0h1))
node _T_2391 = eq(d_release_ack, UInt<1>(0h0))
node _T_2392 = and(_T_2390, _T_2391)
when _T_2392 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2393 = and(io.in.d.valid, d_first_1)
node _T_2394 = and(_T_2393, UInt<1>(0h1))
node _T_2395 = eq(d_release_ack, UInt<1>(0h0))
node _T_2396 = and(_T_2394, _T_2395)
when _T_2396 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2397 = dshr(inflight, io.in.d.bits.source)
node _T_2398 = bits(_T_2397, 0, 0)
node _T_2399 = or(_T_2398, same_cycle_resp)
node _T_2400 = asUInt(reset)
node _T_2401 = eq(_T_2400, UInt<1>(0h0))
when _T_2401 :
node _T_2402 = eq(_T_2399, UInt<1>(0h0))
when _T_2402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2405 = or(_T_2403, _T_2404)
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194
node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195
else :
node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2415 = or(_T_2413, _T_2414)
node _T_2416 = asUInt(reset)
node _T_2417 = eq(_T_2416, UInt<1>(0h0))
when _T_2417 :
node _T_2418 = eq(_T_2415, UInt<1>(0h0))
when _T_2418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196
node _T_2419 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2420 = asUInt(reset)
node _T_2421 = eq(_T_2420, UInt<1>(0h0))
when _T_2421 :
node _T_2422 = eq(_T_2419, UInt<1>(0h0))
when _T_2422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197
node _T_2423 = and(io.in.d.valid, d_first_1)
node _T_2424 = and(_T_2423, a_first_1)
node _T_2425 = and(_T_2424, io.in.a.valid)
node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2427 = and(_T_2425, _T_2426)
node _T_2428 = eq(d_release_ack, UInt<1>(0h0))
node _T_2429 = and(_T_2427, _T_2428)
when _T_2429 :
node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2431 = or(_T_2430, io.in.a.ready)
node _T_2432 = asUInt(reset)
node _T_2433 = eq(_T_2432, UInt<1>(0h0))
when _T_2433 :
node _T_2434 = eq(_T_2431, UInt<1>(0h0))
when _T_2434 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198
node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2436 = orr(a_set_wo_ready)
node _T_2437 = eq(_T_2436, UInt<1>(0h0))
node _T_2438 = or(_T_2435, _T_2437)
node _T_2439 = asUInt(reset)
node _T_2440 = eq(_T_2439, UInt<1>(0h0))
when _T_2440 :
node _T_2441 = eq(_T_2438, UInt<1>(0h0))
when _T_2441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_2
node _T_2442 = orr(inflight)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2445 = or(_T_2443, _T_2444)
node _T_2446 = lt(watchdog, plusarg_reader.out)
node _T_2447 = or(_T_2445, _T_2446)
node _T_2448 = asUInt(reset)
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
when _T_2449 :
node _T_2450 = eq(_T_2447, UInt<1>(0h0))
when _T_2450 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2451 = and(io.in.a.ready, io.in.a.valid)
node _T_2452 = and(io.in.d.ready, io.in.d.valid)
node _T_2453 = or(_T_2451, _T_2452)
when _T_2453 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<3>
connect c_set, UInt<3>(0h0)
wire c_set_wo_ready : UInt<3>
connect c_set_wo_ready, UInt<3>(0h0)
wire c_opcodes_set : UInt<12>
connect c_opcodes_set, UInt<12>(0h0)
wire c_sizes_set : UInt<24>
connect c_sizes_set, UInt<24>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2454 = and(io.in.c.valid, c_first_1)
node _T_2455 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2456 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2457 = and(_T_2455, _T_2456)
node _T_2458 = and(_T_2454, _T_2457)
when _T_2458 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2459 = and(io.in.c.ready, io.in.c.valid)
node _T_2460 = and(_T_2459, c_first_1)
node _T_2461 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2462 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2463 = and(_T_2461, _T_2462)
node _T_2464 = and(_T_2460, _T_2463)
when _T_2464 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2465 = dshr(inflight_1, io.in.c.bits.source)
node _T_2466 = bits(_T_2465, 0, 0)
node _T_2467 = eq(_T_2466, UInt<1>(0h0))
node _T_2468 = asUInt(reset)
node _T_2469 = eq(_T_2468, UInt<1>(0h0))
when _T_2469 :
node _T_2470 = eq(_T_2467, UInt<1>(0h0))
when _T_2470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<3>
connect d_clr_1, UInt<3>(0h0)
wire d_clr_wo_ready_1 : UInt<3>
connect d_clr_wo_ready_1, UInt<3>(0h0)
wire d_opcodes_clr_1 : UInt<12>
connect d_opcodes_clr_1, UInt<12>(0h0)
wire d_sizes_clr_1 : UInt<24>
connect d_sizes_clr_1, UInt<24>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2471 = and(io.in.d.valid, d_first_2)
node _T_2472 = and(_T_2471, UInt<1>(0h1))
node _T_2473 = and(_T_2472, d_release_ack_1)
when _T_2473 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2474 = and(io.in.d.ready, io.in.d.valid)
node _T_2475 = and(_T_2474, d_first_2)
node _T_2476 = and(_T_2475, UInt<1>(0h1))
node _T_2477 = and(_T_2476, d_release_ack_1)
when _T_2477 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2478 = and(io.in.d.valid, d_first_2)
node _T_2479 = and(_T_2478, UInt<1>(0h1))
node _T_2480 = and(_T_2479, d_release_ack_1)
when _T_2480 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2481 = dshr(inflight_1, io.in.d.bits.source)
node _T_2482 = bits(_T_2481, 0, 0)
node _T_2483 = or(_T_2482, same_cycle_resp_1)
node _T_2484 = asUInt(reset)
node _T_2485 = eq(_T_2484, UInt<1>(0h0))
when _T_2485 :
node _T_2486 = eq(_T_2483, UInt<1>(0h0))
when _T_2486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2488 = asUInt(reset)
node _T_2489 = eq(_T_2488, UInt<1>(0h0))
when _T_2489 :
node _T_2490 = eq(_T_2487, UInt<1>(0h0))
when _T_2490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203
else :
node _T_2491 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2492 = asUInt(reset)
node _T_2493 = eq(_T_2492, UInt<1>(0h0))
when _T_2493 :
node _T_2494 = eq(_T_2491, UInt<1>(0h0))
when _T_2494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204
node _T_2495 = and(io.in.d.valid, d_first_2)
node _T_2496 = and(_T_2495, c_first_1)
node _T_2497 = and(_T_2496, io.in.c.valid)
node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2499 = and(_T_2497, _T_2498)
node _T_2500 = and(_T_2499, d_release_ack_1)
node _T_2501 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2502 = and(_T_2500, _T_2501)
when _T_2502 :
node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2504 = or(_T_2503, io.in.c.ready)
node _T_2505 = asUInt(reset)
node _T_2506 = eq(_T_2505, UInt<1>(0h0))
when _T_2506 :
node _T_2507 = eq(_T_2504, UInt<1>(0h0))
when _T_2507 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205
node _T_2508 = orr(c_set_wo_ready)
when _T_2508 :
node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2510 = asUInt(reset)
node _T_2511 = eq(_T_2510, UInt<1>(0h0))
when _T_2511 :
node _T_2512 = eq(_T_2509, UInt<1>(0h0))
when _T_2512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_3
node _T_2513 = orr(inflight_1)
node _T_2514 = eq(_T_2513, UInt<1>(0h0))
node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2516 = or(_T_2514, _T_2515)
node _T_2517 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2518 = or(_T_2516, _T_2517)
node _T_2519 = asUInt(reset)
node _T_2520 = eq(_T_2519, UInt<1>(0h0))
when _T_2520 :
node _T_2521 = eq(_T_2518, UInt<1>(0h0))
when _T_2521 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2522 = and(io.in.c.ready, io.in.c.valid)
node _T_2523 = and(io.in.d.ready, io.in.d.valid)
node _T_2524 = or(_T_2522, _T_2523)
when _T_2524 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2525 = and(io.in.d.ready, io.in.d.valid)
node _T_2526 = and(_T_2525, d_first_3)
node _T_2527 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2528 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2529 = eq(_T_2528, UInt<1>(0h0))
node _T_2530 = and(_T_2527, _T_2529)
node _T_2531 = and(_T_2526, _T_2530)
when _T_2531 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2532 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2533 = bits(_T_2532, 0, 0)
node _T_2534 = eq(_T_2533, UInt<1>(0h0))
node _T_2535 = asUInt(reset)
node _T_2536 = eq(_T_2535, UInt<1>(0h0))
when _T_2536 :
node _T_2537 = eq(_T_2534, UInt<1>(0h0))
when _T_2537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2538 = and(io.in.e.ready, io.in.e.valid)
node _T_2539 = and(_T_2538, UInt<1>(0h1))
node _T_2540 = and(_T_2539, UInt<1>(0h1))
when _T_2540 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2541 = or(d_set, inflight_2)
node _T_2542 = dshr(_T_2541, io.in.e.bits.sink)
node _T_2543 = bits(_T_2542, 0, 0)
node _T_2544 = asUInt(reset)
node _T_2545 = eq(_T_2544, UInt<1>(0h0))
when _T_2545 :
node _T_2546 = eq(_T_2543, UInt<1>(0h0))
when _T_2546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_4 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_5 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_1( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7]
wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] b_first_beats1_decode = 9'h7; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31]
wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31]
wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31]
wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73]
wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73]
wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31]
wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31]
wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31]
wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [1:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [1:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [1:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [1:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [2:0] inflight; // @[Monitor.scala:614:27]
reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [23:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [2:0] a_set; // @[Monitor.scala:626:34]
wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [23:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [4:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69]
wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101]
wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69]
wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65]
wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99]
wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67]
wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99]
wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [3:0] _GEN_20 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35]
wire [3:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [2:0] d_clr; // @[Monitor.scala:664:34]
wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46]
wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [3:0] _GEN_22 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [2:0] inflight_1; // @[Monitor.scala:726:35]
reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [2:0] c_set; // @[Monitor.scala:738:34]
wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [23:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [3:0] _GEN_23 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35]
wire [3:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [2:0] d_clr_1; // @[Monitor.scala:774:34]
wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_24 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_24; // @[OneHot.scala:58:35]
assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_25 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35]
assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_68 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = or(_T_667, _T_672)
node _T_699 = or(_T_698, _T_677)
node _T_700 = or(_T_699, _T_682)
node _T_701 = or(_T_700, _T_687)
node _T_702 = or(_T_701, _T_692)
node _T_703 = or(_T_702, _T_697)
node _T_704 = and(_T_662, _T_703)
node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = and(_T_705, _T_710)
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_714 = and(_T_712, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = or(_T_720, _T_725)
node _T_727 = and(_T_715, _T_726)
node _T_728 = or(UInt<1>(0h0), _T_704)
node _T_729 = or(_T_728, _T_711)
node _T_730 = or(_T_729, _T_727)
node _T_731 = and(_T_658, _T_730)
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_731, UInt<1>(0h1), "") : assert_36
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(is_aligned, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_741, UInt<1>(0h1), "") : assert_39
node _T_745 = eq(io.in.a.bits.mask, mask)
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_745, UInt<1>(0h1), "") : assert_40
node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_749 :
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_754 = and(_T_752, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_758 = and(_T_756, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = or(_T_764, _T_769)
node _T_796 = or(_T_795, _T_774)
node _T_797 = or(_T_796, _T_779)
node _T_798 = or(_T_797, _T_784)
node _T_799 = or(_T_798, _T_789)
node _T_800 = or(_T_799, _T_794)
node _T_801 = and(_T_759, _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_811 = and(_T_809, _T_810)
node _T_812 = or(UInt<1>(0h0), _T_811)
node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = or(_T_817, _T_822)
node _T_824 = and(_T_812, _T_823)
node _T_825 = or(UInt<1>(0h0), _T_801)
node _T_826 = or(_T_825, _T_808)
node _T_827 = or(_T_826, _T_824)
node _T_828 = and(_T_755, _T_827)
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_828, UInt<1>(0h1), "") : assert_41
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(is_aligned, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_838, UInt<1>(0h1), "") : assert_44
node _T_842 = eq(io.in.a.bits.mask, mask)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_842, UInt<1>(0h1), "") : assert_45
node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_846 :
node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_851 = and(_T_849, _T_850)
node _T_852 = or(UInt<1>(0h0), _T_851)
node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = and(_T_856, _T_861)
node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = or(_T_868, _T_873)
node _T_900 = or(_T_899, _T_878)
node _T_901 = or(_T_900, _T_883)
node _T_902 = or(_T_901, _T_888)
node _T_903 = or(_T_902, _T_893)
node _T_904 = or(_T_903, _T_898)
node _T_905 = and(_T_863, _T_904)
node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_908 = and(_T_906, _T_907)
node _T_909 = or(UInt<1>(0h0), _T_908)
node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_911 = cvt(_T_910)
node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000)))
node _T_913 = asSInt(_T_912)
node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0)))
node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = or(_T_914, _T_919)
node _T_921 = and(_T_909, _T_920)
node _T_922 = or(UInt<1>(0h0), _T_862)
node _T_923 = or(_T_922, _T_905)
node _T_924 = or(_T_923, _T_921)
node _T_925 = and(_T_852, _T_924)
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_925, UInt<1>(0h1), "") : assert_46
node _T_929 = asUInt(reset)
node _T_930 = eq(_T_929, UInt<1>(0h0))
when _T_930 :
node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_931 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(is_aligned, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_935, UInt<1>(0h1), "") : assert_49
node _T_939 = eq(io.in.a.bits.mask, mask)
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_939, UInt<1>(0h1), "") : assert_50
node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_943, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_947, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_951 :
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_955, UInt<1>(0h1), "") : assert_54
node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_959, UInt<1>(0h1), "") : assert_55
node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_963, UInt<1>(0h1), "") : assert_56
node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_967, UInt<1>(0h1), "") : assert_57
node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_971 :
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(sink_ok, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_978, UInt<1>(0h1), "") : assert_60
node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_982, UInt<1>(0h1), "") : assert_61
node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_986, UInt<1>(0h1), "") : assert_62
node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_990, UInt<1>(0h1), "") : assert_63
node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_995 = or(UInt<1>(0h1), _T_994)
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_995, UInt<1>(0h1), "") : assert_64
node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_999 :
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(sink_ok, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67
node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68
node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = or(_T_1018, io.in.d.bits.corrupt)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70
node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1024 = or(UInt<1>(0h1), _T_1023)
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71
node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73
node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74
node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1041 = or(UInt<1>(0h1), _T_1040)
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75
node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1045 :
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79
node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1092 = eq(a_first, UInt<1>(0h0))
node _T_1093 = and(io.in.a.valid, _T_1092)
when _T_1093 :
node _T_1094 = eq(io.in.a.bits.opcode, opcode)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87
node _T_1098 = eq(io.in.a.bits.param, param)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88
node _T_1102 = eq(io.in.a.bits.size, size)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89
node _T_1106 = eq(io.in.a.bits.source, source)
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90
node _T_1110 = eq(io.in.a.bits.address, address)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91
node _T_1114 = and(io.in.a.ready, io.in.a.valid)
node _T_1115 = and(_T_1114, a_first)
when _T_1115 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1116 = eq(d_first, UInt<1>(0h0))
node _T_1117 = and(io.in.d.valid, _T_1116)
when _T_1117 :
node _T_1118 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92
node _T_1122 = eq(io.in.d.bits.param, param_1)
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93
node _T_1126 = eq(io.in.d.bits.size, size_1)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94
node _T_1130 = eq(io.in.d.bits.source, source_1)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95
node _T_1134 = eq(io.in.d.bits.sink, sink)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96
node _T_1138 = eq(io.in.d.bits.denied, denied)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97
node _T_1142 = and(io.in.d.ready, io.in.d.valid)
node _T_1143 = and(_T_1142, d_first)
when _T_1143 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1144 = and(io.in.a.valid, a_first_1)
node _T_1145 = and(_T_1144, UInt<1>(0h1))
when _T_1145 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1146 = and(io.in.a.ready, io.in.a.valid)
node _T_1147 = and(_T_1146, a_first_1)
node _T_1148 = and(_T_1147, UInt<1>(0h1))
when _T_1148 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1149 = dshr(inflight, io.in.a.bits.source)
node _T_1150 = bits(_T_1149, 0, 0)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1155 = and(io.in.d.valid, d_first_1)
node _T_1156 = and(_T_1155, UInt<1>(0h1))
node _T_1157 = eq(d_release_ack, UInt<1>(0h0))
node _T_1158 = and(_T_1156, _T_1157)
when _T_1158 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1159 = and(io.in.d.ready, io.in.d.valid)
node _T_1160 = and(_T_1159, d_first_1)
node _T_1161 = and(_T_1160, UInt<1>(0h1))
node _T_1162 = eq(d_release_ack, UInt<1>(0h0))
node _T_1163 = and(_T_1161, _T_1162)
when _T_1163 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1164 = and(io.in.d.valid, d_first_1)
node _T_1165 = and(_T_1164, UInt<1>(0h1))
node _T_1166 = eq(d_release_ack, UInt<1>(0h0))
node _T_1167 = and(_T_1165, _T_1166)
when _T_1167 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1168 = dshr(inflight, io.in.d.bits.source)
node _T_1169 = bits(_T_1168, 0, 0)
node _T_1170 = or(_T_1169, same_cycle_resp)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100
node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101
else :
node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1186 = or(_T_1184, _T_1185)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102
node _T_1190 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103
node _T_1194 = and(io.in.d.valid, d_first_1)
node _T_1195 = and(_T_1194, a_first_1)
node _T_1196 = and(_T_1195, io.in.a.valid)
node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1198 = and(_T_1196, _T_1197)
node _T_1199 = eq(d_release_ack, UInt<1>(0h0))
node _T_1200 = and(_T_1198, _T_1199)
when _T_1200 :
node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1202 = or(_T_1201, io.in.a.ready)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104
node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1207 = orr(a_set_wo_ready)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
node _T_1209 = or(_T_1206, _T_1208)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_144
node _T_1213 = orr(inflight)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1216 = or(_T_1214, _T_1215)
node _T_1217 = lt(watchdog, plusarg_reader.out)
node _T_1218 = or(_T_1216, _T_1217)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1222 = and(io.in.a.ready, io.in.a.valid)
node _T_1223 = and(io.in.d.ready, io.in.d.valid)
node _T_1224 = or(_T_1222, _T_1223)
when _T_1224 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1225 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = and(_T_1225, _T_1228)
when _T_1229 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1231 = and(_T_1230, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1234 = and(_T_1232, _T_1233)
node _T_1235 = and(_T_1231, _T_1234)
when _T_1235 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1237 = bits(_T_1236, 0, 0)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1242 = and(io.in.d.valid, d_first_2)
node _T_1243 = and(_T_1242, UInt<1>(0h1))
node _T_1244 = and(_T_1243, d_release_ack_1)
when _T_1244 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1245 = and(io.in.d.ready, io.in.d.valid)
node _T_1246 = and(_T_1245, d_first_2)
node _T_1247 = and(_T_1246, UInt<1>(0h1))
node _T_1248 = and(_T_1247, d_release_ack_1)
when _T_1248 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1249 = and(io.in.d.valid, d_first_2)
node _T_1250 = and(_T_1249, UInt<1>(0h1))
node _T_1251 = and(_T_1250, d_release_ack_1)
when _T_1251 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1252 = dshr(inflight_1, io.in.d.bits.source)
node _T_1253 = bits(_T_1252, 0, 0)
node _T_1254 = or(_T_1253, same_cycle_resp_1)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(_T_1258, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109
else :
node _T_1262 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110
node _T_1266 = and(io.in.d.valid, d_first_2)
node _T_1267 = and(_T_1266, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1268 = and(_T_1267, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1270 = and(_T_1268, _T_1269)
node _T_1271 = and(_T_1270, d_release_ack_1)
node _T_1272 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1275 = or(_T_1274, _WIRE_23.ready)
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(_T_1275, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111
node _T_1279 = orr(c_set_wo_ready)
when _T_1279 :
node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_145
node _T_1284 = orr(inflight_1)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1287 = or(_T_1285, _T_1286)
node _T_1288 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1294 = and(io.in.d.ready, io.in.d.valid)
node _T_1295 = or(_T_1293, _T_1294)
when _T_1295 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_68( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1148 = _T_1222 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1148 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1148 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1148 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1148 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_1148 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1163 = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1248 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_168 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_168( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCache :
input clock : Clock
input reset : Reset
output auto : { flip ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
inst ctrls of InclusiveCacheControl
connect ctrls.clock, clock
connect ctrls.reset, reset
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_43
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
connect ctrls.auto.ctrl_in, auto.ctrls_ctrl_in
inst inclusive_cache_bank_sched of InclusiveCacheBankScheduler
connect inclusive_cache_bank_sched.clock, clock
connect inclusive_cache_bank_sched.reset, reset
connect inclusive_cache_bank_sched.io.in, nodeIn
connect nodeOut.e.bits, inclusive_cache_bank_sched.io.out.e.bits
connect nodeOut.e.valid, inclusive_cache_bank_sched.io.out.e.valid
connect inclusive_cache_bank_sched.io.out.e.ready, nodeOut.e.ready
connect inclusive_cache_bank_sched.io.out.d, nodeOut.d
connect nodeOut.c.bits, inclusive_cache_bank_sched.io.out.c.bits
connect nodeOut.c.valid, inclusive_cache_bank_sched.io.out.c.valid
connect inclusive_cache_bank_sched.io.out.c.ready, nodeOut.c.ready
connect inclusive_cache_bank_sched.io.out.b, nodeOut.b
connect nodeOut.a.bits, inclusive_cache_bank_sched.io.out.a.bits
connect nodeOut.a.valid, inclusive_cache_bank_sched.io.out.a.valid
connect inclusive_cache_bank_sched.io.out.a.ready, nodeOut.a.ready
invalidate inclusive_cache_bank_sched.io.ways[0]
invalidate inclusive_cache_bank_sched.io.ways[1]
invalidate inclusive_cache_bank_sched.io.ways[2]
invalidate inclusive_cache_bank_sched.io.ways[3]
invalidate inclusive_cache_bank_sched.io.ways[4]
invalidate inclusive_cache_bank_sched.io.ways[5]
invalidate inclusive_cache_bank_sched.io.ways[6]
invalidate inclusive_cache_bank_sched.io.ways[7]
invalidate inclusive_cache_bank_sched.io.ways[8]
invalidate inclusive_cache_bank_sched.io.ways[9]
invalidate inclusive_cache_bank_sched.io.ways[10]
invalidate inclusive_cache_bank_sched.io.ways[11]
invalidate inclusive_cache_bank_sched.io.ways[12]
invalidate inclusive_cache_bank_sched.io.ways[13]
invalidate inclusive_cache_bank_sched.io.ways[14]
invalidate inclusive_cache_bank_sched.io.divs[0]
invalidate inclusive_cache_bank_sched.io.divs[1]
invalidate inclusive_cache_bank_sched.io.divs[2]
invalidate inclusive_cache_bank_sched.io.divs[3]
invalidate inclusive_cache_bank_sched.io.divs[4]
invalidate inclusive_cache_bank_sched.io.divs[5]
invalidate inclusive_cache_bank_sched.io.divs[6]
invalidate inclusive_cache_bank_sched.io.divs[7]
invalidate inclusive_cache_bank_sched.io.divs[8]
invalidate inclusive_cache_bank_sched.io.divs[9]
invalidate inclusive_cache_bank_sched.io.divs[10]
invalidate inclusive_cache_bank_sched.io.divs[11]
invalidate inclusive_cache_bank_sched.io.divs[12]
invalidate inclusive_cache_bank_sched.io.divs[13]
invalidate inclusive_cache_bank_sched.io.divs[14]
connect inclusive_cache_bank_sched.io.req.valid, UInt<1>(0h0)
connect inclusive_cache_bank_sched.io.req.bits.address, UInt<1>(0h0)
connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1)
node _nodeOut_a_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_address_mux_matches_T_1 = cvt(_nodeOut_a_bits_address_mux_matches_T)
node _nodeOut_a_bits_address_mux_matches_T_2 = and(_nodeOut_a_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_address_mux_matches_T_3 = asSInt(_nodeOut_a_bits_address_mux_matches_T_2)
node nodeOut_a_bits_address_mux_0_1 = eq(_nodeOut_a_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_address_T = or(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0))
connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T
node _nodeIn_b_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0))
node _nodeIn_b_bits_address_mux_matches_T_1 = cvt(_nodeIn_b_bits_address_mux_matches_T)
node _nodeIn_b_bits_address_mux_matches_T_2 = and(_nodeIn_b_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0)))
node _nodeIn_b_bits_address_mux_matches_T_3 = asSInt(_nodeIn_b_bits_address_mux_matches_T_2)
node nodeIn_b_bits_address_mux_0_1 = eq(_nodeIn_b_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0)))
node _nodeIn_b_bits_address_T = or(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0))
connect nodeIn.b.bits.address, _nodeIn_b_bits_address_T
node _nodeOut_c_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_address_mux_matches_T_1 = cvt(_nodeOut_c_bits_address_mux_matches_T)
node _nodeOut_c_bits_address_mux_matches_T_2 = and(_nodeOut_c_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_address_mux_matches_T_3 = asSInt(_nodeOut_c_bits_address_mux_matches_T_2)
node nodeOut_c_bits_address_mux_0_1 = eq(_nodeOut_c_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_address_T = or(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0))
connect nodeOut.c.bits.address, _nodeOut_c_bits_address_T
connect ctrls.io.flush_req.ready, UInt<1>(0h0)
connect ctrls.io.flush_resp, UInt<1>(0h0)
connect ctrls.io.flush_match, UInt<1>(0h0)
node _contained_T = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000000))
node _contained_T_1 = cvt(_contained_T)
node _contained_T_2 = and(_contained_T_1, asSInt(UInt<29>(0h10000000)))
node _contained_T_3 = asSInt(_contained_T_2)
node _contained_T_4 = eq(_contained_T_3, asSInt(UInt<1>(0h0)))
node _contained_T_5 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000000))
node _contained_T_6 = cvt(_contained_T_5)
node _contained_T_7 = and(_contained_T_6, asSInt(UInt<17>(0h10000)))
node _contained_T_8 = asSInt(_contained_T_7)
node _contained_T_9 = eq(_contained_T_8, asSInt(UInt<1>(0h0)))
node contained = or(_contained_T_4, _contained_T_9)
when contained :
connect ctrls.io.flush_match, UInt<1>(0h1)
node _inclusive_cache_bank_sched_io_req_valid_T = and(contained, ctrls.io.flush_req.valid)
connect inclusive_cache_bank_sched.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T
connect inclusive_cache_bank_sched.io.req.bits.address, ctrls.io.flush_req.bits
node _T = and(contained, inclusive_cache_bank_sched.io.req.ready)
when _T :
connect ctrls.io.flush_req.ready, UInt<1>(0h1)
when inclusive_cache_bank_sched.io.resp.valid :
connect ctrls.io.flush_resp, UInt<1>(0h1)
connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1) | module InclusiveCache( // @[InclusiveCache.scala:108:9]
input clock, // @[InclusiveCache.scala:108:9]
input reset, // @[InclusiveCache.scala:108:9]
output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire _inclusive_cache_bank_sched_io_in_a_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_b_valid; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_io_in_b_bits_param; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_c_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_d_valid; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_opcode; // @[InclusiveCache.scala:137:29]
wire [1:0] _inclusive_cache_bank_sched_io_in_d_bits_param; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_size; // @[InclusiveCache.scala:137:29]
wire [8:0] _inclusive_cache_bank_sched_io_in_d_bits_source; // @[InclusiveCache.scala:137:29]
wire [2:0] _inclusive_cache_bank_sched_io_in_d_bits_sink; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_d_bits_denied; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_in_d_bits_corrupt; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29]
wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43]
wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43]
wire contained = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:28] ^ 4'h8} == 36'h0 | {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:16] ^ 12'h800} == 48'h0; // @[Parameters.scala:137:{31,41,46,59}]
InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43]
.clock (clock),
.reset (reset),
.auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready),
.auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid),
.auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode),
.auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param),
.auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size),
.auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source),
.auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address),
.auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask),
.auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data),
.auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt),
.auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready),
.auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid),
.auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode),
.auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size),
.auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source),
.auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data),
.io_flush_match (contained), // @[InclusiveCache.scala:169:67]
.io_flush_req_ready (contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:25]
.io_flush_req_valid (_ctrls_io_flush_req_valid),
.io_flush_req_bits (_ctrls_io_flush_req_bits),
.io_flush_resp (_inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29]
); // @[InclusiveCache.scala:103:43]
TLMonitor_43 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_io_in_a_ready), // @[InclusiveCache.scala:137:29]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_b_ready (auto_in_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_io_in_b_valid), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_param (_inclusive_cache_bank_sched_io_in_b_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address), // @[InclusiveCache.scala:137:29]
.io_in_c_ready (_inclusive_cache_bank_sched_io_in_c_ready), // @[InclusiveCache.scala:137:29]
.io_in_c_valid (auto_in_c_valid),
.io_in_c_bits_opcode (auto_in_c_bits_opcode),
.io_in_c_bits_param (auto_in_c_bits_param),
.io_in_c_bits_size (auto_in_c_bits_size),
.io_in_c_bits_source (auto_in_c_bits_source),
.io_in_c_bits_address (auto_in_c_bits_address),
.io_in_c_bits_corrupt (auto_in_c_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_io_in_d_valid), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_io_in_d_bits_opcode), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_param (_inclusive_cache_bank_sched_io_in_d_bits_param), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_size (_inclusive_cache_bank_sched_io_in_d_bits_size), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_source (_inclusive_cache_bank_sched_io_in_d_bits_source), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_sink (_inclusive_cache_bank_sched_io_in_d_bits_sink), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_denied (_inclusive_cache_bank_sched_io_in_d_bits_denied), // @[InclusiveCache.scala:137:29]
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_io_in_d_bits_corrupt), // @[InclusiveCache.scala:137:29]
.io_in_e_valid (auto_in_e_valid),
.io_in_e_bits_sink (auto_in_e_bits_sink)
); // @[Nodes.scala:27:25]
InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29]
.clock (clock),
.reset (reset),
.io_in_a_ready (_inclusive_cache_bank_sched_io_in_a_ready),
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_data (auto_in_a_bits_data),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_b_ready (auto_in_b_ready),
.io_in_b_valid (_inclusive_cache_bank_sched_io_in_b_valid),
.io_in_b_bits_param (_inclusive_cache_bank_sched_io_in_b_bits_param),
.io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address),
.io_in_c_ready (_inclusive_cache_bank_sched_io_in_c_ready),
.io_in_c_valid (auto_in_c_valid),
.io_in_c_bits_opcode (auto_in_c_bits_opcode),
.io_in_c_bits_param (auto_in_c_bits_param),
.io_in_c_bits_size (auto_in_c_bits_size),
.io_in_c_bits_source (auto_in_c_bits_source),
.io_in_c_bits_address (auto_in_c_bits_address),
.io_in_c_bits_data (auto_in_c_bits_data),
.io_in_c_bits_corrupt (auto_in_c_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_inclusive_cache_bank_sched_io_in_d_valid),
.io_in_d_bits_opcode (_inclusive_cache_bank_sched_io_in_d_bits_opcode),
.io_in_d_bits_param (_inclusive_cache_bank_sched_io_in_d_bits_param),
.io_in_d_bits_size (_inclusive_cache_bank_sched_io_in_d_bits_size),
.io_in_d_bits_source (_inclusive_cache_bank_sched_io_in_d_bits_source),
.io_in_d_bits_sink (_inclusive_cache_bank_sched_io_in_d_bits_sink),
.io_in_d_bits_denied (_inclusive_cache_bank_sched_io_in_d_bits_denied),
.io_in_d_bits_data (auto_in_d_bits_data),
.io_in_d_bits_corrupt (_inclusive_cache_bank_sched_io_in_d_bits_corrupt),
.io_in_e_valid (auto_in_e_valid),
.io_in_e_bits_sink (auto_in_e_bits_sink),
.io_out_a_ready (auto_out_a_ready),
.io_out_a_valid (auto_out_a_valid),
.io_out_a_bits_opcode (auto_out_a_bits_opcode),
.io_out_a_bits_param (auto_out_a_bits_param),
.io_out_a_bits_size (auto_out_a_bits_size),
.io_out_a_bits_source (auto_out_a_bits_source),
.io_out_a_bits_address (auto_out_a_bits_address),
.io_out_a_bits_mask (auto_out_a_bits_mask),
.io_out_a_bits_data (auto_out_a_bits_data),
.io_out_a_bits_corrupt (auto_out_a_bits_corrupt),
.io_out_c_ready (auto_out_c_ready),
.io_out_c_valid (auto_out_c_valid),
.io_out_c_bits_opcode (auto_out_c_bits_opcode),
.io_out_c_bits_param (auto_out_c_bits_param),
.io_out_c_bits_size (auto_out_c_bits_size),
.io_out_c_bits_source (auto_out_c_bits_source),
.io_out_c_bits_address (auto_out_c_bits_address),
.io_out_c_bits_data (auto_out_c_bits_data),
.io_out_c_bits_corrupt (auto_out_c_bits_corrupt),
.io_out_d_ready (auto_out_d_ready),
.io_out_d_valid (auto_out_d_valid),
.io_out_d_bits_opcode (auto_out_d_bits_opcode),
.io_out_d_bits_param (auto_out_d_bits_param),
.io_out_d_bits_size (auto_out_d_bits_size),
.io_out_d_bits_source (auto_out_d_bits_source),
.io_out_d_bits_sink (auto_out_d_bits_sink),
.io_out_d_bits_denied (auto_out_d_bits_denied),
.io_out_d_bits_data (auto_out_d_bits_data),
.io_out_d_bits_corrupt (auto_out_d_bits_corrupt),
.io_out_e_valid (auto_out_e_valid),
.io_out_e_bits_sink (auto_out_e_bits_sink),
.io_req_ready (_inclusive_cache_bank_sched_io_req_ready),
.io_req_valid (contained & _ctrls_io_flush_req_valid), // @[InclusiveCache.scala:103:43, :169:67, :172:41]
.io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31]
.io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid)
); // @[InclusiveCache.scala:137:29]
assign auto_in_a_ready = _inclusive_cache_bank_sched_io_in_a_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_b_valid = _inclusive_cache_bank_sched_io_in_b_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_b_bits_param = _inclusive_cache_bank_sched_io_in_b_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_b_bits_address = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_c_ready = _inclusive_cache_bank_sched_io_in_c_ready; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_valid = _inclusive_cache_bank_sched_io_in_d_valid; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_bits_opcode = _inclusive_cache_bank_sched_io_in_d_bits_opcode; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_bits_param = _inclusive_cache_bank_sched_io_in_d_bits_param; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_bits_size = _inclusive_cache_bank_sched_io_in_d_bits_size; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_bits_source = _inclusive_cache_bank_sched_io_in_d_bits_source; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_bits_sink = _inclusive_cache_bank_sched_io_in_d_bits_sink; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_bits_denied = _inclusive_cache_bank_sched_io_in_d_bits_denied; // @[InclusiveCache.scala:108:9, :137:29]
assign auto_in_d_bits_corrupt = _inclusive_cache_bank_sched_io_in_d_bits_corrupt; // @[InclusiveCache.scala:108:9, :137:29]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_64 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_64( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Atomics_3 :
input clock : Clock
input reset : Reset
output io : { flip write : UInt<1>, flip a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, flip data_in : UInt<128>, data_out : UInt<128>}
node adder = bits(io.a.param, 2, 2)
node unsigned = bits(io.a.param, 1, 1)
node take_max = bits(io.a.param, 0, 0)
node _signBit_T = not(io.a.mask)
node _signBit_T_1 = shr(_signBit_T, 1)
node _signBit_T_2 = cat(UInt<1>(0h1), _signBit_T_1)
node signBit = and(io.a.mask, _signBit_T_2)
node _inv_d_T = not(io.data_in)
node inv_d = mux(adder, io.data_in, _inv_d_T)
node _sum_T = bits(io.a.mask, 0, 0)
node _sum_T_1 = bits(io.a.mask, 1, 1)
node _sum_T_2 = bits(io.a.mask, 2, 2)
node _sum_T_3 = bits(io.a.mask, 3, 3)
node _sum_T_4 = bits(io.a.mask, 4, 4)
node _sum_T_5 = bits(io.a.mask, 5, 5)
node _sum_T_6 = bits(io.a.mask, 6, 6)
node _sum_T_7 = bits(io.a.mask, 7, 7)
node _sum_T_8 = bits(io.a.mask, 8, 8)
node _sum_T_9 = bits(io.a.mask, 9, 9)
node _sum_T_10 = bits(io.a.mask, 10, 10)
node _sum_T_11 = bits(io.a.mask, 11, 11)
node _sum_T_12 = bits(io.a.mask, 12, 12)
node _sum_T_13 = bits(io.a.mask, 13, 13)
node _sum_T_14 = bits(io.a.mask, 14, 14)
node _sum_T_15 = bits(io.a.mask, 15, 15)
node _sum_T_16 = mux(_sum_T, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_17 = mux(_sum_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_18 = mux(_sum_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_19 = mux(_sum_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_20 = mux(_sum_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_21 = mux(_sum_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_22 = mux(_sum_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_23 = mux(_sum_T_7, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_24 = mux(_sum_T_8, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_25 = mux(_sum_T_9, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_26 = mux(_sum_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_27 = mux(_sum_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_28 = mux(_sum_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_29 = mux(_sum_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_30 = mux(_sum_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_31 = mux(_sum_T_15, UInt<8>(0hff), UInt<8>(0h0))
node sum_lo_lo_lo = cat(_sum_T_17, _sum_T_16)
node sum_lo_lo_hi = cat(_sum_T_19, _sum_T_18)
node sum_lo_lo = cat(sum_lo_lo_hi, sum_lo_lo_lo)
node sum_lo_hi_lo = cat(_sum_T_21, _sum_T_20)
node sum_lo_hi_hi = cat(_sum_T_23, _sum_T_22)
node sum_lo_hi = cat(sum_lo_hi_hi, sum_lo_hi_lo)
node sum_lo = cat(sum_lo_hi, sum_lo_lo)
node sum_hi_lo_lo = cat(_sum_T_25, _sum_T_24)
node sum_hi_lo_hi = cat(_sum_T_27, _sum_T_26)
node sum_hi_lo = cat(sum_hi_lo_hi, sum_hi_lo_lo)
node sum_hi_hi_lo = cat(_sum_T_29, _sum_T_28)
node sum_hi_hi_hi = cat(_sum_T_31, _sum_T_30)
node sum_hi_hi = cat(sum_hi_hi_hi, sum_hi_hi_lo)
node sum_hi = cat(sum_hi_hi, sum_hi_lo)
node _sum_T_32 = cat(sum_hi, sum_lo)
node _sum_T_33 = and(_sum_T_32, io.a.data)
node _sum_T_34 = add(_sum_T_33, inv_d)
node sum = tail(_sum_T_34, 1)
node _sign_a_T = bits(io.a.data, 0, 0)
node _sign_a_T_1 = bits(io.a.data, 1, 1)
node _sign_a_T_2 = bits(io.a.data, 2, 2)
node _sign_a_T_3 = bits(io.a.data, 3, 3)
node _sign_a_T_4 = bits(io.a.data, 4, 4)
node _sign_a_T_5 = bits(io.a.data, 5, 5)
node _sign_a_T_6 = bits(io.a.data, 6, 6)
node _sign_a_T_7 = bits(io.a.data, 7, 7)
node _sign_a_T_8 = bits(io.a.data, 8, 8)
node _sign_a_T_9 = bits(io.a.data, 9, 9)
node _sign_a_T_10 = bits(io.a.data, 10, 10)
node _sign_a_T_11 = bits(io.a.data, 11, 11)
node _sign_a_T_12 = bits(io.a.data, 12, 12)
node _sign_a_T_13 = bits(io.a.data, 13, 13)
node _sign_a_T_14 = bits(io.a.data, 14, 14)
node _sign_a_T_15 = bits(io.a.data, 15, 15)
node _sign_a_T_16 = bits(io.a.data, 16, 16)
node _sign_a_T_17 = bits(io.a.data, 17, 17)
node _sign_a_T_18 = bits(io.a.data, 18, 18)
node _sign_a_T_19 = bits(io.a.data, 19, 19)
node _sign_a_T_20 = bits(io.a.data, 20, 20)
node _sign_a_T_21 = bits(io.a.data, 21, 21)
node _sign_a_T_22 = bits(io.a.data, 22, 22)
node _sign_a_T_23 = bits(io.a.data, 23, 23)
node _sign_a_T_24 = bits(io.a.data, 24, 24)
node _sign_a_T_25 = bits(io.a.data, 25, 25)
node _sign_a_T_26 = bits(io.a.data, 26, 26)
node _sign_a_T_27 = bits(io.a.data, 27, 27)
node _sign_a_T_28 = bits(io.a.data, 28, 28)
node _sign_a_T_29 = bits(io.a.data, 29, 29)
node _sign_a_T_30 = bits(io.a.data, 30, 30)
node _sign_a_T_31 = bits(io.a.data, 31, 31)
node _sign_a_T_32 = bits(io.a.data, 32, 32)
node _sign_a_T_33 = bits(io.a.data, 33, 33)
node _sign_a_T_34 = bits(io.a.data, 34, 34)
node _sign_a_T_35 = bits(io.a.data, 35, 35)
node _sign_a_T_36 = bits(io.a.data, 36, 36)
node _sign_a_T_37 = bits(io.a.data, 37, 37)
node _sign_a_T_38 = bits(io.a.data, 38, 38)
node _sign_a_T_39 = bits(io.a.data, 39, 39)
node _sign_a_T_40 = bits(io.a.data, 40, 40)
node _sign_a_T_41 = bits(io.a.data, 41, 41)
node _sign_a_T_42 = bits(io.a.data, 42, 42)
node _sign_a_T_43 = bits(io.a.data, 43, 43)
node _sign_a_T_44 = bits(io.a.data, 44, 44)
node _sign_a_T_45 = bits(io.a.data, 45, 45)
node _sign_a_T_46 = bits(io.a.data, 46, 46)
node _sign_a_T_47 = bits(io.a.data, 47, 47)
node _sign_a_T_48 = bits(io.a.data, 48, 48)
node _sign_a_T_49 = bits(io.a.data, 49, 49)
node _sign_a_T_50 = bits(io.a.data, 50, 50)
node _sign_a_T_51 = bits(io.a.data, 51, 51)
node _sign_a_T_52 = bits(io.a.data, 52, 52)
node _sign_a_T_53 = bits(io.a.data, 53, 53)
node _sign_a_T_54 = bits(io.a.data, 54, 54)
node _sign_a_T_55 = bits(io.a.data, 55, 55)
node _sign_a_T_56 = bits(io.a.data, 56, 56)
node _sign_a_T_57 = bits(io.a.data, 57, 57)
node _sign_a_T_58 = bits(io.a.data, 58, 58)
node _sign_a_T_59 = bits(io.a.data, 59, 59)
node _sign_a_T_60 = bits(io.a.data, 60, 60)
node _sign_a_T_61 = bits(io.a.data, 61, 61)
node _sign_a_T_62 = bits(io.a.data, 62, 62)
node _sign_a_T_63 = bits(io.a.data, 63, 63)
node _sign_a_T_64 = bits(io.a.data, 64, 64)
node _sign_a_T_65 = bits(io.a.data, 65, 65)
node _sign_a_T_66 = bits(io.a.data, 66, 66)
node _sign_a_T_67 = bits(io.a.data, 67, 67)
node _sign_a_T_68 = bits(io.a.data, 68, 68)
node _sign_a_T_69 = bits(io.a.data, 69, 69)
node _sign_a_T_70 = bits(io.a.data, 70, 70)
node _sign_a_T_71 = bits(io.a.data, 71, 71)
node _sign_a_T_72 = bits(io.a.data, 72, 72)
node _sign_a_T_73 = bits(io.a.data, 73, 73)
node _sign_a_T_74 = bits(io.a.data, 74, 74)
node _sign_a_T_75 = bits(io.a.data, 75, 75)
node _sign_a_T_76 = bits(io.a.data, 76, 76)
node _sign_a_T_77 = bits(io.a.data, 77, 77)
node _sign_a_T_78 = bits(io.a.data, 78, 78)
node _sign_a_T_79 = bits(io.a.data, 79, 79)
node _sign_a_T_80 = bits(io.a.data, 80, 80)
node _sign_a_T_81 = bits(io.a.data, 81, 81)
node _sign_a_T_82 = bits(io.a.data, 82, 82)
node _sign_a_T_83 = bits(io.a.data, 83, 83)
node _sign_a_T_84 = bits(io.a.data, 84, 84)
node _sign_a_T_85 = bits(io.a.data, 85, 85)
node _sign_a_T_86 = bits(io.a.data, 86, 86)
node _sign_a_T_87 = bits(io.a.data, 87, 87)
node _sign_a_T_88 = bits(io.a.data, 88, 88)
node _sign_a_T_89 = bits(io.a.data, 89, 89)
node _sign_a_T_90 = bits(io.a.data, 90, 90)
node _sign_a_T_91 = bits(io.a.data, 91, 91)
node _sign_a_T_92 = bits(io.a.data, 92, 92)
node _sign_a_T_93 = bits(io.a.data, 93, 93)
node _sign_a_T_94 = bits(io.a.data, 94, 94)
node _sign_a_T_95 = bits(io.a.data, 95, 95)
node _sign_a_T_96 = bits(io.a.data, 96, 96)
node _sign_a_T_97 = bits(io.a.data, 97, 97)
node _sign_a_T_98 = bits(io.a.data, 98, 98)
node _sign_a_T_99 = bits(io.a.data, 99, 99)
node _sign_a_T_100 = bits(io.a.data, 100, 100)
node _sign_a_T_101 = bits(io.a.data, 101, 101)
node _sign_a_T_102 = bits(io.a.data, 102, 102)
node _sign_a_T_103 = bits(io.a.data, 103, 103)
node _sign_a_T_104 = bits(io.a.data, 104, 104)
node _sign_a_T_105 = bits(io.a.data, 105, 105)
node _sign_a_T_106 = bits(io.a.data, 106, 106)
node _sign_a_T_107 = bits(io.a.data, 107, 107)
node _sign_a_T_108 = bits(io.a.data, 108, 108)
node _sign_a_T_109 = bits(io.a.data, 109, 109)
node _sign_a_T_110 = bits(io.a.data, 110, 110)
node _sign_a_T_111 = bits(io.a.data, 111, 111)
node _sign_a_T_112 = bits(io.a.data, 112, 112)
node _sign_a_T_113 = bits(io.a.data, 113, 113)
node _sign_a_T_114 = bits(io.a.data, 114, 114)
node _sign_a_T_115 = bits(io.a.data, 115, 115)
node _sign_a_T_116 = bits(io.a.data, 116, 116)
node _sign_a_T_117 = bits(io.a.data, 117, 117)
node _sign_a_T_118 = bits(io.a.data, 118, 118)
node _sign_a_T_119 = bits(io.a.data, 119, 119)
node _sign_a_T_120 = bits(io.a.data, 120, 120)
node _sign_a_T_121 = bits(io.a.data, 121, 121)
node _sign_a_T_122 = bits(io.a.data, 122, 122)
node _sign_a_T_123 = bits(io.a.data, 123, 123)
node _sign_a_T_124 = bits(io.a.data, 124, 124)
node _sign_a_T_125 = bits(io.a.data, 125, 125)
node _sign_a_T_126 = bits(io.a.data, 126, 126)
node _sign_a_T_127 = bits(io.a.data, 127, 127)
node sign_a_lo_lo_lo = cat(_sign_a_T_15, _sign_a_T_7)
node sign_a_lo_lo_hi = cat(_sign_a_T_31, _sign_a_T_23)
node sign_a_lo_lo = cat(sign_a_lo_lo_hi, sign_a_lo_lo_lo)
node sign_a_lo_hi_lo = cat(_sign_a_T_47, _sign_a_T_39)
node sign_a_lo_hi_hi = cat(_sign_a_T_63, _sign_a_T_55)
node sign_a_lo_hi = cat(sign_a_lo_hi_hi, sign_a_lo_hi_lo)
node sign_a_lo = cat(sign_a_lo_hi, sign_a_lo_lo)
node sign_a_hi_lo_lo = cat(_sign_a_T_79, _sign_a_T_71)
node sign_a_hi_lo_hi = cat(_sign_a_T_95, _sign_a_T_87)
node sign_a_hi_lo = cat(sign_a_hi_lo_hi, sign_a_hi_lo_lo)
node sign_a_hi_hi_lo = cat(_sign_a_T_111, _sign_a_T_103)
node sign_a_hi_hi_hi = cat(_sign_a_T_127, _sign_a_T_119)
node sign_a_hi_hi = cat(sign_a_hi_hi_hi, sign_a_hi_hi_lo)
node sign_a_hi = cat(sign_a_hi_hi, sign_a_hi_lo)
node _sign_a_T_128 = cat(sign_a_hi, sign_a_lo)
node _sign_a_T_129 = and(_sign_a_T_128, signBit)
node sign_a = orr(_sign_a_T_129)
node _sign_d_T = bits(io.data_in, 0, 0)
node _sign_d_T_1 = bits(io.data_in, 1, 1)
node _sign_d_T_2 = bits(io.data_in, 2, 2)
node _sign_d_T_3 = bits(io.data_in, 3, 3)
node _sign_d_T_4 = bits(io.data_in, 4, 4)
node _sign_d_T_5 = bits(io.data_in, 5, 5)
node _sign_d_T_6 = bits(io.data_in, 6, 6)
node _sign_d_T_7 = bits(io.data_in, 7, 7)
node _sign_d_T_8 = bits(io.data_in, 8, 8)
node _sign_d_T_9 = bits(io.data_in, 9, 9)
node _sign_d_T_10 = bits(io.data_in, 10, 10)
node _sign_d_T_11 = bits(io.data_in, 11, 11)
node _sign_d_T_12 = bits(io.data_in, 12, 12)
node _sign_d_T_13 = bits(io.data_in, 13, 13)
node _sign_d_T_14 = bits(io.data_in, 14, 14)
node _sign_d_T_15 = bits(io.data_in, 15, 15)
node _sign_d_T_16 = bits(io.data_in, 16, 16)
node _sign_d_T_17 = bits(io.data_in, 17, 17)
node _sign_d_T_18 = bits(io.data_in, 18, 18)
node _sign_d_T_19 = bits(io.data_in, 19, 19)
node _sign_d_T_20 = bits(io.data_in, 20, 20)
node _sign_d_T_21 = bits(io.data_in, 21, 21)
node _sign_d_T_22 = bits(io.data_in, 22, 22)
node _sign_d_T_23 = bits(io.data_in, 23, 23)
node _sign_d_T_24 = bits(io.data_in, 24, 24)
node _sign_d_T_25 = bits(io.data_in, 25, 25)
node _sign_d_T_26 = bits(io.data_in, 26, 26)
node _sign_d_T_27 = bits(io.data_in, 27, 27)
node _sign_d_T_28 = bits(io.data_in, 28, 28)
node _sign_d_T_29 = bits(io.data_in, 29, 29)
node _sign_d_T_30 = bits(io.data_in, 30, 30)
node _sign_d_T_31 = bits(io.data_in, 31, 31)
node _sign_d_T_32 = bits(io.data_in, 32, 32)
node _sign_d_T_33 = bits(io.data_in, 33, 33)
node _sign_d_T_34 = bits(io.data_in, 34, 34)
node _sign_d_T_35 = bits(io.data_in, 35, 35)
node _sign_d_T_36 = bits(io.data_in, 36, 36)
node _sign_d_T_37 = bits(io.data_in, 37, 37)
node _sign_d_T_38 = bits(io.data_in, 38, 38)
node _sign_d_T_39 = bits(io.data_in, 39, 39)
node _sign_d_T_40 = bits(io.data_in, 40, 40)
node _sign_d_T_41 = bits(io.data_in, 41, 41)
node _sign_d_T_42 = bits(io.data_in, 42, 42)
node _sign_d_T_43 = bits(io.data_in, 43, 43)
node _sign_d_T_44 = bits(io.data_in, 44, 44)
node _sign_d_T_45 = bits(io.data_in, 45, 45)
node _sign_d_T_46 = bits(io.data_in, 46, 46)
node _sign_d_T_47 = bits(io.data_in, 47, 47)
node _sign_d_T_48 = bits(io.data_in, 48, 48)
node _sign_d_T_49 = bits(io.data_in, 49, 49)
node _sign_d_T_50 = bits(io.data_in, 50, 50)
node _sign_d_T_51 = bits(io.data_in, 51, 51)
node _sign_d_T_52 = bits(io.data_in, 52, 52)
node _sign_d_T_53 = bits(io.data_in, 53, 53)
node _sign_d_T_54 = bits(io.data_in, 54, 54)
node _sign_d_T_55 = bits(io.data_in, 55, 55)
node _sign_d_T_56 = bits(io.data_in, 56, 56)
node _sign_d_T_57 = bits(io.data_in, 57, 57)
node _sign_d_T_58 = bits(io.data_in, 58, 58)
node _sign_d_T_59 = bits(io.data_in, 59, 59)
node _sign_d_T_60 = bits(io.data_in, 60, 60)
node _sign_d_T_61 = bits(io.data_in, 61, 61)
node _sign_d_T_62 = bits(io.data_in, 62, 62)
node _sign_d_T_63 = bits(io.data_in, 63, 63)
node _sign_d_T_64 = bits(io.data_in, 64, 64)
node _sign_d_T_65 = bits(io.data_in, 65, 65)
node _sign_d_T_66 = bits(io.data_in, 66, 66)
node _sign_d_T_67 = bits(io.data_in, 67, 67)
node _sign_d_T_68 = bits(io.data_in, 68, 68)
node _sign_d_T_69 = bits(io.data_in, 69, 69)
node _sign_d_T_70 = bits(io.data_in, 70, 70)
node _sign_d_T_71 = bits(io.data_in, 71, 71)
node _sign_d_T_72 = bits(io.data_in, 72, 72)
node _sign_d_T_73 = bits(io.data_in, 73, 73)
node _sign_d_T_74 = bits(io.data_in, 74, 74)
node _sign_d_T_75 = bits(io.data_in, 75, 75)
node _sign_d_T_76 = bits(io.data_in, 76, 76)
node _sign_d_T_77 = bits(io.data_in, 77, 77)
node _sign_d_T_78 = bits(io.data_in, 78, 78)
node _sign_d_T_79 = bits(io.data_in, 79, 79)
node _sign_d_T_80 = bits(io.data_in, 80, 80)
node _sign_d_T_81 = bits(io.data_in, 81, 81)
node _sign_d_T_82 = bits(io.data_in, 82, 82)
node _sign_d_T_83 = bits(io.data_in, 83, 83)
node _sign_d_T_84 = bits(io.data_in, 84, 84)
node _sign_d_T_85 = bits(io.data_in, 85, 85)
node _sign_d_T_86 = bits(io.data_in, 86, 86)
node _sign_d_T_87 = bits(io.data_in, 87, 87)
node _sign_d_T_88 = bits(io.data_in, 88, 88)
node _sign_d_T_89 = bits(io.data_in, 89, 89)
node _sign_d_T_90 = bits(io.data_in, 90, 90)
node _sign_d_T_91 = bits(io.data_in, 91, 91)
node _sign_d_T_92 = bits(io.data_in, 92, 92)
node _sign_d_T_93 = bits(io.data_in, 93, 93)
node _sign_d_T_94 = bits(io.data_in, 94, 94)
node _sign_d_T_95 = bits(io.data_in, 95, 95)
node _sign_d_T_96 = bits(io.data_in, 96, 96)
node _sign_d_T_97 = bits(io.data_in, 97, 97)
node _sign_d_T_98 = bits(io.data_in, 98, 98)
node _sign_d_T_99 = bits(io.data_in, 99, 99)
node _sign_d_T_100 = bits(io.data_in, 100, 100)
node _sign_d_T_101 = bits(io.data_in, 101, 101)
node _sign_d_T_102 = bits(io.data_in, 102, 102)
node _sign_d_T_103 = bits(io.data_in, 103, 103)
node _sign_d_T_104 = bits(io.data_in, 104, 104)
node _sign_d_T_105 = bits(io.data_in, 105, 105)
node _sign_d_T_106 = bits(io.data_in, 106, 106)
node _sign_d_T_107 = bits(io.data_in, 107, 107)
node _sign_d_T_108 = bits(io.data_in, 108, 108)
node _sign_d_T_109 = bits(io.data_in, 109, 109)
node _sign_d_T_110 = bits(io.data_in, 110, 110)
node _sign_d_T_111 = bits(io.data_in, 111, 111)
node _sign_d_T_112 = bits(io.data_in, 112, 112)
node _sign_d_T_113 = bits(io.data_in, 113, 113)
node _sign_d_T_114 = bits(io.data_in, 114, 114)
node _sign_d_T_115 = bits(io.data_in, 115, 115)
node _sign_d_T_116 = bits(io.data_in, 116, 116)
node _sign_d_T_117 = bits(io.data_in, 117, 117)
node _sign_d_T_118 = bits(io.data_in, 118, 118)
node _sign_d_T_119 = bits(io.data_in, 119, 119)
node _sign_d_T_120 = bits(io.data_in, 120, 120)
node _sign_d_T_121 = bits(io.data_in, 121, 121)
node _sign_d_T_122 = bits(io.data_in, 122, 122)
node _sign_d_T_123 = bits(io.data_in, 123, 123)
node _sign_d_T_124 = bits(io.data_in, 124, 124)
node _sign_d_T_125 = bits(io.data_in, 125, 125)
node _sign_d_T_126 = bits(io.data_in, 126, 126)
node _sign_d_T_127 = bits(io.data_in, 127, 127)
node sign_d_lo_lo_lo = cat(_sign_d_T_15, _sign_d_T_7)
node sign_d_lo_lo_hi = cat(_sign_d_T_31, _sign_d_T_23)
node sign_d_lo_lo = cat(sign_d_lo_lo_hi, sign_d_lo_lo_lo)
node sign_d_lo_hi_lo = cat(_sign_d_T_47, _sign_d_T_39)
node sign_d_lo_hi_hi = cat(_sign_d_T_63, _sign_d_T_55)
node sign_d_lo_hi = cat(sign_d_lo_hi_hi, sign_d_lo_hi_lo)
node sign_d_lo = cat(sign_d_lo_hi, sign_d_lo_lo)
node sign_d_hi_lo_lo = cat(_sign_d_T_79, _sign_d_T_71)
node sign_d_hi_lo_hi = cat(_sign_d_T_95, _sign_d_T_87)
node sign_d_hi_lo = cat(sign_d_hi_lo_hi, sign_d_hi_lo_lo)
node sign_d_hi_hi_lo = cat(_sign_d_T_111, _sign_d_T_103)
node sign_d_hi_hi_hi = cat(_sign_d_T_127, _sign_d_T_119)
node sign_d_hi_hi = cat(sign_d_hi_hi_hi, sign_d_hi_hi_lo)
node sign_d_hi = cat(sign_d_hi_hi, sign_d_hi_lo)
node _sign_d_T_128 = cat(sign_d_hi, sign_d_lo)
node _sign_d_T_129 = and(_sign_d_T_128, signBit)
node sign_d = orr(_sign_d_T_129)
node _sign_s_T = bits(sum, 0, 0)
node _sign_s_T_1 = bits(sum, 1, 1)
node _sign_s_T_2 = bits(sum, 2, 2)
node _sign_s_T_3 = bits(sum, 3, 3)
node _sign_s_T_4 = bits(sum, 4, 4)
node _sign_s_T_5 = bits(sum, 5, 5)
node _sign_s_T_6 = bits(sum, 6, 6)
node _sign_s_T_7 = bits(sum, 7, 7)
node _sign_s_T_8 = bits(sum, 8, 8)
node _sign_s_T_9 = bits(sum, 9, 9)
node _sign_s_T_10 = bits(sum, 10, 10)
node _sign_s_T_11 = bits(sum, 11, 11)
node _sign_s_T_12 = bits(sum, 12, 12)
node _sign_s_T_13 = bits(sum, 13, 13)
node _sign_s_T_14 = bits(sum, 14, 14)
node _sign_s_T_15 = bits(sum, 15, 15)
node _sign_s_T_16 = bits(sum, 16, 16)
node _sign_s_T_17 = bits(sum, 17, 17)
node _sign_s_T_18 = bits(sum, 18, 18)
node _sign_s_T_19 = bits(sum, 19, 19)
node _sign_s_T_20 = bits(sum, 20, 20)
node _sign_s_T_21 = bits(sum, 21, 21)
node _sign_s_T_22 = bits(sum, 22, 22)
node _sign_s_T_23 = bits(sum, 23, 23)
node _sign_s_T_24 = bits(sum, 24, 24)
node _sign_s_T_25 = bits(sum, 25, 25)
node _sign_s_T_26 = bits(sum, 26, 26)
node _sign_s_T_27 = bits(sum, 27, 27)
node _sign_s_T_28 = bits(sum, 28, 28)
node _sign_s_T_29 = bits(sum, 29, 29)
node _sign_s_T_30 = bits(sum, 30, 30)
node _sign_s_T_31 = bits(sum, 31, 31)
node _sign_s_T_32 = bits(sum, 32, 32)
node _sign_s_T_33 = bits(sum, 33, 33)
node _sign_s_T_34 = bits(sum, 34, 34)
node _sign_s_T_35 = bits(sum, 35, 35)
node _sign_s_T_36 = bits(sum, 36, 36)
node _sign_s_T_37 = bits(sum, 37, 37)
node _sign_s_T_38 = bits(sum, 38, 38)
node _sign_s_T_39 = bits(sum, 39, 39)
node _sign_s_T_40 = bits(sum, 40, 40)
node _sign_s_T_41 = bits(sum, 41, 41)
node _sign_s_T_42 = bits(sum, 42, 42)
node _sign_s_T_43 = bits(sum, 43, 43)
node _sign_s_T_44 = bits(sum, 44, 44)
node _sign_s_T_45 = bits(sum, 45, 45)
node _sign_s_T_46 = bits(sum, 46, 46)
node _sign_s_T_47 = bits(sum, 47, 47)
node _sign_s_T_48 = bits(sum, 48, 48)
node _sign_s_T_49 = bits(sum, 49, 49)
node _sign_s_T_50 = bits(sum, 50, 50)
node _sign_s_T_51 = bits(sum, 51, 51)
node _sign_s_T_52 = bits(sum, 52, 52)
node _sign_s_T_53 = bits(sum, 53, 53)
node _sign_s_T_54 = bits(sum, 54, 54)
node _sign_s_T_55 = bits(sum, 55, 55)
node _sign_s_T_56 = bits(sum, 56, 56)
node _sign_s_T_57 = bits(sum, 57, 57)
node _sign_s_T_58 = bits(sum, 58, 58)
node _sign_s_T_59 = bits(sum, 59, 59)
node _sign_s_T_60 = bits(sum, 60, 60)
node _sign_s_T_61 = bits(sum, 61, 61)
node _sign_s_T_62 = bits(sum, 62, 62)
node _sign_s_T_63 = bits(sum, 63, 63)
node _sign_s_T_64 = bits(sum, 64, 64)
node _sign_s_T_65 = bits(sum, 65, 65)
node _sign_s_T_66 = bits(sum, 66, 66)
node _sign_s_T_67 = bits(sum, 67, 67)
node _sign_s_T_68 = bits(sum, 68, 68)
node _sign_s_T_69 = bits(sum, 69, 69)
node _sign_s_T_70 = bits(sum, 70, 70)
node _sign_s_T_71 = bits(sum, 71, 71)
node _sign_s_T_72 = bits(sum, 72, 72)
node _sign_s_T_73 = bits(sum, 73, 73)
node _sign_s_T_74 = bits(sum, 74, 74)
node _sign_s_T_75 = bits(sum, 75, 75)
node _sign_s_T_76 = bits(sum, 76, 76)
node _sign_s_T_77 = bits(sum, 77, 77)
node _sign_s_T_78 = bits(sum, 78, 78)
node _sign_s_T_79 = bits(sum, 79, 79)
node _sign_s_T_80 = bits(sum, 80, 80)
node _sign_s_T_81 = bits(sum, 81, 81)
node _sign_s_T_82 = bits(sum, 82, 82)
node _sign_s_T_83 = bits(sum, 83, 83)
node _sign_s_T_84 = bits(sum, 84, 84)
node _sign_s_T_85 = bits(sum, 85, 85)
node _sign_s_T_86 = bits(sum, 86, 86)
node _sign_s_T_87 = bits(sum, 87, 87)
node _sign_s_T_88 = bits(sum, 88, 88)
node _sign_s_T_89 = bits(sum, 89, 89)
node _sign_s_T_90 = bits(sum, 90, 90)
node _sign_s_T_91 = bits(sum, 91, 91)
node _sign_s_T_92 = bits(sum, 92, 92)
node _sign_s_T_93 = bits(sum, 93, 93)
node _sign_s_T_94 = bits(sum, 94, 94)
node _sign_s_T_95 = bits(sum, 95, 95)
node _sign_s_T_96 = bits(sum, 96, 96)
node _sign_s_T_97 = bits(sum, 97, 97)
node _sign_s_T_98 = bits(sum, 98, 98)
node _sign_s_T_99 = bits(sum, 99, 99)
node _sign_s_T_100 = bits(sum, 100, 100)
node _sign_s_T_101 = bits(sum, 101, 101)
node _sign_s_T_102 = bits(sum, 102, 102)
node _sign_s_T_103 = bits(sum, 103, 103)
node _sign_s_T_104 = bits(sum, 104, 104)
node _sign_s_T_105 = bits(sum, 105, 105)
node _sign_s_T_106 = bits(sum, 106, 106)
node _sign_s_T_107 = bits(sum, 107, 107)
node _sign_s_T_108 = bits(sum, 108, 108)
node _sign_s_T_109 = bits(sum, 109, 109)
node _sign_s_T_110 = bits(sum, 110, 110)
node _sign_s_T_111 = bits(sum, 111, 111)
node _sign_s_T_112 = bits(sum, 112, 112)
node _sign_s_T_113 = bits(sum, 113, 113)
node _sign_s_T_114 = bits(sum, 114, 114)
node _sign_s_T_115 = bits(sum, 115, 115)
node _sign_s_T_116 = bits(sum, 116, 116)
node _sign_s_T_117 = bits(sum, 117, 117)
node _sign_s_T_118 = bits(sum, 118, 118)
node _sign_s_T_119 = bits(sum, 119, 119)
node _sign_s_T_120 = bits(sum, 120, 120)
node _sign_s_T_121 = bits(sum, 121, 121)
node _sign_s_T_122 = bits(sum, 122, 122)
node _sign_s_T_123 = bits(sum, 123, 123)
node _sign_s_T_124 = bits(sum, 124, 124)
node _sign_s_T_125 = bits(sum, 125, 125)
node _sign_s_T_126 = bits(sum, 126, 126)
node _sign_s_T_127 = bits(sum, 127, 127)
node sign_s_lo_lo_lo = cat(_sign_s_T_15, _sign_s_T_7)
node sign_s_lo_lo_hi = cat(_sign_s_T_31, _sign_s_T_23)
node sign_s_lo_lo = cat(sign_s_lo_lo_hi, sign_s_lo_lo_lo)
node sign_s_lo_hi_lo = cat(_sign_s_T_47, _sign_s_T_39)
node sign_s_lo_hi_hi = cat(_sign_s_T_63, _sign_s_T_55)
node sign_s_lo_hi = cat(sign_s_lo_hi_hi, sign_s_lo_hi_lo)
node sign_s_lo = cat(sign_s_lo_hi, sign_s_lo_lo)
node sign_s_hi_lo_lo = cat(_sign_s_T_79, _sign_s_T_71)
node sign_s_hi_lo_hi = cat(_sign_s_T_95, _sign_s_T_87)
node sign_s_hi_lo = cat(sign_s_hi_lo_hi, sign_s_hi_lo_lo)
node sign_s_hi_hi_lo = cat(_sign_s_T_111, _sign_s_T_103)
node sign_s_hi_hi_hi = cat(_sign_s_T_127, _sign_s_T_119)
node sign_s_hi_hi = cat(sign_s_hi_hi_hi, sign_s_hi_hi_lo)
node sign_s_hi = cat(sign_s_hi_hi, sign_s_hi_lo)
node _sign_s_T_128 = cat(sign_s_hi, sign_s_lo)
node _sign_s_T_129 = and(_sign_s_T_128, signBit)
node sign_s = orr(_sign_s_T_129)
node a_bigger_uneq = eq(unsigned, sign_a)
node _a_bigger_T = eq(sign_a, sign_d)
node _a_bigger_T_1 = eq(sign_s, UInt<1>(0h0))
node a_bigger = mux(_a_bigger_T, _a_bigger_T_1, a_bigger_uneq)
node pick_a = eq(take_max, a_bigger)
wire _lut_WIRE : UInt<4>[4]
connect _lut_WIRE[0], UInt<3>(0h6)
connect _lut_WIRE[1], UInt<4>(0he)
connect _lut_WIRE[2], UInt<4>(0h8)
connect _lut_WIRE[3], UInt<4>(0hc)
node _lut_T = bits(io.a.param, 1, 0)
node _logical_T = bits(io.a.data, 0, 0)
node _logical_T_1 = bits(io.a.data, 1, 1)
node _logical_T_2 = bits(io.a.data, 2, 2)
node _logical_T_3 = bits(io.a.data, 3, 3)
node _logical_T_4 = bits(io.a.data, 4, 4)
node _logical_T_5 = bits(io.a.data, 5, 5)
node _logical_T_6 = bits(io.a.data, 6, 6)
node _logical_T_7 = bits(io.a.data, 7, 7)
node _logical_T_8 = bits(io.a.data, 8, 8)
node _logical_T_9 = bits(io.a.data, 9, 9)
node _logical_T_10 = bits(io.a.data, 10, 10)
node _logical_T_11 = bits(io.a.data, 11, 11)
node _logical_T_12 = bits(io.a.data, 12, 12)
node _logical_T_13 = bits(io.a.data, 13, 13)
node _logical_T_14 = bits(io.a.data, 14, 14)
node _logical_T_15 = bits(io.a.data, 15, 15)
node _logical_T_16 = bits(io.a.data, 16, 16)
node _logical_T_17 = bits(io.a.data, 17, 17)
node _logical_T_18 = bits(io.a.data, 18, 18)
node _logical_T_19 = bits(io.a.data, 19, 19)
node _logical_T_20 = bits(io.a.data, 20, 20)
node _logical_T_21 = bits(io.a.data, 21, 21)
node _logical_T_22 = bits(io.a.data, 22, 22)
node _logical_T_23 = bits(io.a.data, 23, 23)
node _logical_T_24 = bits(io.a.data, 24, 24)
node _logical_T_25 = bits(io.a.data, 25, 25)
node _logical_T_26 = bits(io.a.data, 26, 26)
node _logical_T_27 = bits(io.a.data, 27, 27)
node _logical_T_28 = bits(io.a.data, 28, 28)
node _logical_T_29 = bits(io.a.data, 29, 29)
node _logical_T_30 = bits(io.a.data, 30, 30)
node _logical_T_31 = bits(io.a.data, 31, 31)
node _logical_T_32 = bits(io.a.data, 32, 32)
node _logical_T_33 = bits(io.a.data, 33, 33)
node _logical_T_34 = bits(io.a.data, 34, 34)
node _logical_T_35 = bits(io.a.data, 35, 35)
node _logical_T_36 = bits(io.a.data, 36, 36)
node _logical_T_37 = bits(io.a.data, 37, 37)
node _logical_T_38 = bits(io.a.data, 38, 38)
node _logical_T_39 = bits(io.a.data, 39, 39)
node _logical_T_40 = bits(io.a.data, 40, 40)
node _logical_T_41 = bits(io.a.data, 41, 41)
node _logical_T_42 = bits(io.a.data, 42, 42)
node _logical_T_43 = bits(io.a.data, 43, 43)
node _logical_T_44 = bits(io.a.data, 44, 44)
node _logical_T_45 = bits(io.a.data, 45, 45)
node _logical_T_46 = bits(io.a.data, 46, 46)
node _logical_T_47 = bits(io.a.data, 47, 47)
node _logical_T_48 = bits(io.a.data, 48, 48)
node _logical_T_49 = bits(io.a.data, 49, 49)
node _logical_T_50 = bits(io.a.data, 50, 50)
node _logical_T_51 = bits(io.a.data, 51, 51)
node _logical_T_52 = bits(io.a.data, 52, 52)
node _logical_T_53 = bits(io.a.data, 53, 53)
node _logical_T_54 = bits(io.a.data, 54, 54)
node _logical_T_55 = bits(io.a.data, 55, 55)
node _logical_T_56 = bits(io.a.data, 56, 56)
node _logical_T_57 = bits(io.a.data, 57, 57)
node _logical_T_58 = bits(io.a.data, 58, 58)
node _logical_T_59 = bits(io.a.data, 59, 59)
node _logical_T_60 = bits(io.a.data, 60, 60)
node _logical_T_61 = bits(io.a.data, 61, 61)
node _logical_T_62 = bits(io.a.data, 62, 62)
node _logical_T_63 = bits(io.a.data, 63, 63)
node _logical_T_64 = bits(io.a.data, 64, 64)
node _logical_T_65 = bits(io.a.data, 65, 65)
node _logical_T_66 = bits(io.a.data, 66, 66)
node _logical_T_67 = bits(io.a.data, 67, 67)
node _logical_T_68 = bits(io.a.data, 68, 68)
node _logical_T_69 = bits(io.a.data, 69, 69)
node _logical_T_70 = bits(io.a.data, 70, 70)
node _logical_T_71 = bits(io.a.data, 71, 71)
node _logical_T_72 = bits(io.a.data, 72, 72)
node _logical_T_73 = bits(io.a.data, 73, 73)
node _logical_T_74 = bits(io.a.data, 74, 74)
node _logical_T_75 = bits(io.a.data, 75, 75)
node _logical_T_76 = bits(io.a.data, 76, 76)
node _logical_T_77 = bits(io.a.data, 77, 77)
node _logical_T_78 = bits(io.a.data, 78, 78)
node _logical_T_79 = bits(io.a.data, 79, 79)
node _logical_T_80 = bits(io.a.data, 80, 80)
node _logical_T_81 = bits(io.a.data, 81, 81)
node _logical_T_82 = bits(io.a.data, 82, 82)
node _logical_T_83 = bits(io.a.data, 83, 83)
node _logical_T_84 = bits(io.a.data, 84, 84)
node _logical_T_85 = bits(io.a.data, 85, 85)
node _logical_T_86 = bits(io.a.data, 86, 86)
node _logical_T_87 = bits(io.a.data, 87, 87)
node _logical_T_88 = bits(io.a.data, 88, 88)
node _logical_T_89 = bits(io.a.data, 89, 89)
node _logical_T_90 = bits(io.a.data, 90, 90)
node _logical_T_91 = bits(io.a.data, 91, 91)
node _logical_T_92 = bits(io.a.data, 92, 92)
node _logical_T_93 = bits(io.a.data, 93, 93)
node _logical_T_94 = bits(io.a.data, 94, 94)
node _logical_T_95 = bits(io.a.data, 95, 95)
node _logical_T_96 = bits(io.a.data, 96, 96)
node _logical_T_97 = bits(io.a.data, 97, 97)
node _logical_T_98 = bits(io.a.data, 98, 98)
node _logical_T_99 = bits(io.a.data, 99, 99)
node _logical_T_100 = bits(io.a.data, 100, 100)
node _logical_T_101 = bits(io.a.data, 101, 101)
node _logical_T_102 = bits(io.a.data, 102, 102)
node _logical_T_103 = bits(io.a.data, 103, 103)
node _logical_T_104 = bits(io.a.data, 104, 104)
node _logical_T_105 = bits(io.a.data, 105, 105)
node _logical_T_106 = bits(io.a.data, 106, 106)
node _logical_T_107 = bits(io.a.data, 107, 107)
node _logical_T_108 = bits(io.a.data, 108, 108)
node _logical_T_109 = bits(io.a.data, 109, 109)
node _logical_T_110 = bits(io.a.data, 110, 110)
node _logical_T_111 = bits(io.a.data, 111, 111)
node _logical_T_112 = bits(io.a.data, 112, 112)
node _logical_T_113 = bits(io.a.data, 113, 113)
node _logical_T_114 = bits(io.a.data, 114, 114)
node _logical_T_115 = bits(io.a.data, 115, 115)
node _logical_T_116 = bits(io.a.data, 116, 116)
node _logical_T_117 = bits(io.a.data, 117, 117)
node _logical_T_118 = bits(io.a.data, 118, 118)
node _logical_T_119 = bits(io.a.data, 119, 119)
node _logical_T_120 = bits(io.a.data, 120, 120)
node _logical_T_121 = bits(io.a.data, 121, 121)
node _logical_T_122 = bits(io.a.data, 122, 122)
node _logical_T_123 = bits(io.a.data, 123, 123)
node _logical_T_124 = bits(io.a.data, 124, 124)
node _logical_T_125 = bits(io.a.data, 125, 125)
node _logical_T_126 = bits(io.a.data, 126, 126)
node _logical_T_127 = bits(io.a.data, 127, 127)
node _logical_T_128 = bits(io.data_in, 0, 0)
node _logical_T_129 = bits(io.data_in, 1, 1)
node _logical_T_130 = bits(io.data_in, 2, 2)
node _logical_T_131 = bits(io.data_in, 3, 3)
node _logical_T_132 = bits(io.data_in, 4, 4)
node _logical_T_133 = bits(io.data_in, 5, 5)
node _logical_T_134 = bits(io.data_in, 6, 6)
node _logical_T_135 = bits(io.data_in, 7, 7)
node _logical_T_136 = bits(io.data_in, 8, 8)
node _logical_T_137 = bits(io.data_in, 9, 9)
node _logical_T_138 = bits(io.data_in, 10, 10)
node _logical_T_139 = bits(io.data_in, 11, 11)
node _logical_T_140 = bits(io.data_in, 12, 12)
node _logical_T_141 = bits(io.data_in, 13, 13)
node _logical_T_142 = bits(io.data_in, 14, 14)
node _logical_T_143 = bits(io.data_in, 15, 15)
node _logical_T_144 = bits(io.data_in, 16, 16)
node _logical_T_145 = bits(io.data_in, 17, 17)
node _logical_T_146 = bits(io.data_in, 18, 18)
node _logical_T_147 = bits(io.data_in, 19, 19)
node _logical_T_148 = bits(io.data_in, 20, 20)
node _logical_T_149 = bits(io.data_in, 21, 21)
node _logical_T_150 = bits(io.data_in, 22, 22)
node _logical_T_151 = bits(io.data_in, 23, 23)
node _logical_T_152 = bits(io.data_in, 24, 24)
node _logical_T_153 = bits(io.data_in, 25, 25)
node _logical_T_154 = bits(io.data_in, 26, 26)
node _logical_T_155 = bits(io.data_in, 27, 27)
node _logical_T_156 = bits(io.data_in, 28, 28)
node _logical_T_157 = bits(io.data_in, 29, 29)
node _logical_T_158 = bits(io.data_in, 30, 30)
node _logical_T_159 = bits(io.data_in, 31, 31)
node _logical_T_160 = bits(io.data_in, 32, 32)
node _logical_T_161 = bits(io.data_in, 33, 33)
node _logical_T_162 = bits(io.data_in, 34, 34)
node _logical_T_163 = bits(io.data_in, 35, 35)
node _logical_T_164 = bits(io.data_in, 36, 36)
node _logical_T_165 = bits(io.data_in, 37, 37)
node _logical_T_166 = bits(io.data_in, 38, 38)
node _logical_T_167 = bits(io.data_in, 39, 39)
node _logical_T_168 = bits(io.data_in, 40, 40)
node _logical_T_169 = bits(io.data_in, 41, 41)
node _logical_T_170 = bits(io.data_in, 42, 42)
node _logical_T_171 = bits(io.data_in, 43, 43)
node _logical_T_172 = bits(io.data_in, 44, 44)
node _logical_T_173 = bits(io.data_in, 45, 45)
node _logical_T_174 = bits(io.data_in, 46, 46)
node _logical_T_175 = bits(io.data_in, 47, 47)
node _logical_T_176 = bits(io.data_in, 48, 48)
node _logical_T_177 = bits(io.data_in, 49, 49)
node _logical_T_178 = bits(io.data_in, 50, 50)
node _logical_T_179 = bits(io.data_in, 51, 51)
node _logical_T_180 = bits(io.data_in, 52, 52)
node _logical_T_181 = bits(io.data_in, 53, 53)
node _logical_T_182 = bits(io.data_in, 54, 54)
node _logical_T_183 = bits(io.data_in, 55, 55)
node _logical_T_184 = bits(io.data_in, 56, 56)
node _logical_T_185 = bits(io.data_in, 57, 57)
node _logical_T_186 = bits(io.data_in, 58, 58)
node _logical_T_187 = bits(io.data_in, 59, 59)
node _logical_T_188 = bits(io.data_in, 60, 60)
node _logical_T_189 = bits(io.data_in, 61, 61)
node _logical_T_190 = bits(io.data_in, 62, 62)
node _logical_T_191 = bits(io.data_in, 63, 63)
node _logical_T_192 = bits(io.data_in, 64, 64)
node _logical_T_193 = bits(io.data_in, 65, 65)
node _logical_T_194 = bits(io.data_in, 66, 66)
node _logical_T_195 = bits(io.data_in, 67, 67)
node _logical_T_196 = bits(io.data_in, 68, 68)
node _logical_T_197 = bits(io.data_in, 69, 69)
node _logical_T_198 = bits(io.data_in, 70, 70)
node _logical_T_199 = bits(io.data_in, 71, 71)
node _logical_T_200 = bits(io.data_in, 72, 72)
node _logical_T_201 = bits(io.data_in, 73, 73)
node _logical_T_202 = bits(io.data_in, 74, 74)
node _logical_T_203 = bits(io.data_in, 75, 75)
node _logical_T_204 = bits(io.data_in, 76, 76)
node _logical_T_205 = bits(io.data_in, 77, 77)
node _logical_T_206 = bits(io.data_in, 78, 78)
node _logical_T_207 = bits(io.data_in, 79, 79)
node _logical_T_208 = bits(io.data_in, 80, 80)
node _logical_T_209 = bits(io.data_in, 81, 81)
node _logical_T_210 = bits(io.data_in, 82, 82)
node _logical_T_211 = bits(io.data_in, 83, 83)
node _logical_T_212 = bits(io.data_in, 84, 84)
node _logical_T_213 = bits(io.data_in, 85, 85)
node _logical_T_214 = bits(io.data_in, 86, 86)
node _logical_T_215 = bits(io.data_in, 87, 87)
node _logical_T_216 = bits(io.data_in, 88, 88)
node _logical_T_217 = bits(io.data_in, 89, 89)
node _logical_T_218 = bits(io.data_in, 90, 90)
node _logical_T_219 = bits(io.data_in, 91, 91)
node _logical_T_220 = bits(io.data_in, 92, 92)
node _logical_T_221 = bits(io.data_in, 93, 93)
node _logical_T_222 = bits(io.data_in, 94, 94)
node _logical_T_223 = bits(io.data_in, 95, 95)
node _logical_T_224 = bits(io.data_in, 96, 96)
node _logical_T_225 = bits(io.data_in, 97, 97)
node _logical_T_226 = bits(io.data_in, 98, 98)
node _logical_T_227 = bits(io.data_in, 99, 99)
node _logical_T_228 = bits(io.data_in, 100, 100)
node _logical_T_229 = bits(io.data_in, 101, 101)
node _logical_T_230 = bits(io.data_in, 102, 102)
node _logical_T_231 = bits(io.data_in, 103, 103)
node _logical_T_232 = bits(io.data_in, 104, 104)
node _logical_T_233 = bits(io.data_in, 105, 105)
node _logical_T_234 = bits(io.data_in, 106, 106)
node _logical_T_235 = bits(io.data_in, 107, 107)
node _logical_T_236 = bits(io.data_in, 108, 108)
node _logical_T_237 = bits(io.data_in, 109, 109)
node _logical_T_238 = bits(io.data_in, 110, 110)
node _logical_T_239 = bits(io.data_in, 111, 111)
node _logical_T_240 = bits(io.data_in, 112, 112)
node _logical_T_241 = bits(io.data_in, 113, 113)
node _logical_T_242 = bits(io.data_in, 114, 114)
node _logical_T_243 = bits(io.data_in, 115, 115)
node _logical_T_244 = bits(io.data_in, 116, 116)
node _logical_T_245 = bits(io.data_in, 117, 117)
node _logical_T_246 = bits(io.data_in, 118, 118)
node _logical_T_247 = bits(io.data_in, 119, 119)
node _logical_T_248 = bits(io.data_in, 120, 120)
node _logical_T_249 = bits(io.data_in, 121, 121)
node _logical_T_250 = bits(io.data_in, 122, 122)
node _logical_T_251 = bits(io.data_in, 123, 123)
node _logical_T_252 = bits(io.data_in, 124, 124)
node _logical_T_253 = bits(io.data_in, 125, 125)
node _logical_T_254 = bits(io.data_in, 126, 126)
node _logical_T_255 = bits(io.data_in, 127, 127)
node _logical_T_256 = cat(_logical_T, _logical_T_128)
node _logical_T_257 = dshr(_lut_WIRE[_lut_T], _logical_T_256)
node _logical_T_258 = bits(_logical_T_257, 0, 0)
node _logical_T_259 = cat(_logical_T_1, _logical_T_129)
node _logical_T_260 = dshr(_lut_WIRE[_lut_T], _logical_T_259)
node _logical_T_261 = bits(_logical_T_260, 0, 0)
node _logical_T_262 = cat(_logical_T_2, _logical_T_130)
node _logical_T_263 = dshr(_lut_WIRE[_lut_T], _logical_T_262)
node _logical_T_264 = bits(_logical_T_263, 0, 0)
node _logical_T_265 = cat(_logical_T_3, _logical_T_131)
node _logical_T_266 = dshr(_lut_WIRE[_lut_T], _logical_T_265)
node _logical_T_267 = bits(_logical_T_266, 0, 0)
node _logical_T_268 = cat(_logical_T_4, _logical_T_132)
node _logical_T_269 = dshr(_lut_WIRE[_lut_T], _logical_T_268)
node _logical_T_270 = bits(_logical_T_269, 0, 0)
node _logical_T_271 = cat(_logical_T_5, _logical_T_133)
node _logical_T_272 = dshr(_lut_WIRE[_lut_T], _logical_T_271)
node _logical_T_273 = bits(_logical_T_272, 0, 0)
node _logical_T_274 = cat(_logical_T_6, _logical_T_134)
node _logical_T_275 = dshr(_lut_WIRE[_lut_T], _logical_T_274)
node _logical_T_276 = bits(_logical_T_275, 0, 0)
node _logical_T_277 = cat(_logical_T_7, _logical_T_135)
node _logical_T_278 = dshr(_lut_WIRE[_lut_T], _logical_T_277)
node _logical_T_279 = bits(_logical_T_278, 0, 0)
node _logical_T_280 = cat(_logical_T_8, _logical_T_136)
node _logical_T_281 = dshr(_lut_WIRE[_lut_T], _logical_T_280)
node _logical_T_282 = bits(_logical_T_281, 0, 0)
node _logical_T_283 = cat(_logical_T_9, _logical_T_137)
node _logical_T_284 = dshr(_lut_WIRE[_lut_T], _logical_T_283)
node _logical_T_285 = bits(_logical_T_284, 0, 0)
node _logical_T_286 = cat(_logical_T_10, _logical_T_138)
node _logical_T_287 = dshr(_lut_WIRE[_lut_T], _logical_T_286)
node _logical_T_288 = bits(_logical_T_287, 0, 0)
node _logical_T_289 = cat(_logical_T_11, _logical_T_139)
node _logical_T_290 = dshr(_lut_WIRE[_lut_T], _logical_T_289)
node _logical_T_291 = bits(_logical_T_290, 0, 0)
node _logical_T_292 = cat(_logical_T_12, _logical_T_140)
node _logical_T_293 = dshr(_lut_WIRE[_lut_T], _logical_T_292)
node _logical_T_294 = bits(_logical_T_293, 0, 0)
node _logical_T_295 = cat(_logical_T_13, _logical_T_141)
node _logical_T_296 = dshr(_lut_WIRE[_lut_T], _logical_T_295)
node _logical_T_297 = bits(_logical_T_296, 0, 0)
node _logical_T_298 = cat(_logical_T_14, _logical_T_142)
node _logical_T_299 = dshr(_lut_WIRE[_lut_T], _logical_T_298)
node _logical_T_300 = bits(_logical_T_299, 0, 0)
node _logical_T_301 = cat(_logical_T_15, _logical_T_143)
node _logical_T_302 = dshr(_lut_WIRE[_lut_T], _logical_T_301)
node _logical_T_303 = bits(_logical_T_302, 0, 0)
node _logical_T_304 = cat(_logical_T_16, _logical_T_144)
node _logical_T_305 = dshr(_lut_WIRE[_lut_T], _logical_T_304)
node _logical_T_306 = bits(_logical_T_305, 0, 0)
node _logical_T_307 = cat(_logical_T_17, _logical_T_145)
node _logical_T_308 = dshr(_lut_WIRE[_lut_T], _logical_T_307)
node _logical_T_309 = bits(_logical_T_308, 0, 0)
node _logical_T_310 = cat(_logical_T_18, _logical_T_146)
node _logical_T_311 = dshr(_lut_WIRE[_lut_T], _logical_T_310)
node _logical_T_312 = bits(_logical_T_311, 0, 0)
node _logical_T_313 = cat(_logical_T_19, _logical_T_147)
node _logical_T_314 = dshr(_lut_WIRE[_lut_T], _logical_T_313)
node _logical_T_315 = bits(_logical_T_314, 0, 0)
node _logical_T_316 = cat(_logical_T_20, _logical_T_148)
node _logical_T_317 = dshr(_lut_WIRE[_lut_T], _logical_T_316)
node _logical_T_318 = bits(_logical_T_317, 0, 0)
node _logical_T_319 = cat(_logical_T_21, _logical_T_149)
node _logical_T_320 = dshr(_lut_WIRE[_lut_T], _logical_T_319)
node _logical_T_321 = bits(_logical_T_320, 0, 0)
node _logical_T_322 = cat(_logical_T_22, _logical_T_150)
node _logical_T_323 = dshr(_lut_WIRE[_lut_T], _logical_T_322)
node _logical_T_324 = bits(_logical_T_323, 0, 0)
node _logical_T_325 = cat(_logical_T_23, _logical_T_151)
node _logical_T_326 = dshr(_lut_WIRE[_lut_T], _logical_T_325)
node _logical_T_327 = bits(_logical_T_326, 0, 0)
node _logical_T_328 = cat(_logical_T_24, _logical_T_152)
node _logical_T_329 = dshr(_lut_WIRE[_lut_T], _logical_T_328)
node _logical_T_330 = bits(_logical_T_329, 0, 0)
node _logical_T_331 = cat(_logical_T_25, _logical_T_153)
node _logical_T_332 = dshr(_lut_WIRE[_lut_T], _logical_T_331)
node _logical_T_333 = bits(_logical_T_332, 0, 0)
node _logical_T_334 = cat(_logical_T_26, _logical_T_154)
node _logical_T_335 = dshr(_lut_WIRE[_lut_T], _logical_T_334)
node _logical_T_336 = bits(_logical_T_335, 0, 0)
node _logical_T_337 = cat(_logical_T_27, _logical_T_155)
node _logical_T_338 = dshr(_lut_WIRE[_lut_T], _logical_T_337)
node _logical_T_339 = bits(_logical_T_338, 0, 0)
node _logical_T_340 = cat(_logical_T_28, _logical_T_156)
node _logical_T_341 = dshr(_lut_WIRE[_lut_T], _logical_T_340)
node _logical_T_342 = bits(_logical_T_341, 0, 0)
node _logical_T_343 = cat(_logical_T_29, _logical_T_157)
node _logical_T_344 = dshr(_lut_WIRE[_lut_T], _logical_T_343)
node _logical_T_345 = bits(_logical_T_344, 0, 0)
node _logical_T_346 = cat(_logical_T_30, _logical_T_158)
node _logical_T_347 = dshr(_lut_WIRE[_lut_T], _logical_T_346)
node _logical_T_348 = bits(_logical_T_347, 0, 0)
node _logical_T_349 = cat(_logical_T_31, _logical_T_159)
node _logical_T_350 = dshr(_lut_WIRE[_lut_T], _logical_T_349)
node _logical_T_351 = bits(_logical_T_350, 0, 0)
node _logical_T_352 = cat(_logical_T_32, _logical_T_160)
node _logical_T_353 = dshr(_lut_WIRE[_lut_T], _logical_T_352)
node _logical_T_354 = bits(_logical_T_353, 0, 0)
node _logical_T_355 = cat(_logical_T_33, _logical_T_161)
node _logical_T_356 = dshr(_lut_WIRE[_lut_T], _logical_T_355)
node _logical_T_357 = bits(_logical_T_356, 0, 0)
node _logical_T_358 = cat(_logical_T_34, _logical_T_162)
node _logical_T_359 = dshr(_lut_WIRE[_lut_T], _logical_T_358)
node _logical_T_360 = bits(_logical_T_359, 0, 0)
node _logical_T_361 = cat(_logical_T_35, _logical_T_163)
node _logical_T_362 = dshr(_lut_WIRE[_lut_T], _logical_T_361)
node _logical_T_363 = bits(_logical_T_362, 0, 0)
node _logical_T_364 = cat(_logical_T_36, _logical_T_164)
node _logical_T_365 = dshr(_lut_WIRE[_lut_T], _logical_T_364)
node _logical_T_366 = bits(_logical_T_365, 0, 0)
node _logical_T_367 = cat(_logical_T_37, _logical_T_165)
node _logical_T_368 = dshr(_lut_WIRE[_lut_T], _logical_T_367)
node _logical_T_369 = bits(_logical_T_368, 0, 0)
node _logical_T_370 = cat(_logical_T_38, _logical_T_166)
node _logical_T_371 = dshr(_lut_WIRE[_lut_T], _logical_T_370)
node _logical_T_372 = bits(_logical_T_371, 0, 0)
node _logical_T_373 = cat(_logical_T_39, _logical_T_167)
node _logical_T_374 = dshr(_lut_WIRE[_lut_T], _logical_T_373)
node _logical_T_375 = bits(_logical_T_374, 0, 0)
node _logical_T_376 = cat(_logical_T_40, _logical_T_168)
node _logical_T_377 = dshr(_lut_WIRE[_lut_T], _logical_T_376)
node _logical_T_378 = bits(_logical_T_377, 0, 0)
node _logical_T_379 = cat(_logical_T_41, _logical_T_169)
node _logical_T_380 = dshr(_lut_WIRE[_lut_T], _logical_T_379)
node _logical_T_381 = bits(_logical_T_380, 0, 0)
node _logical_T_382 = cat(_logical_T_42, _logical_T_170)
node _logical_T_383 = dshr(_lut_WIRE[_lut_T], _logical_T_382)
node _logical_T_384 = bits(_logical_T_383, 0, 0)
node _logical_T_385 = cat(_logical_T_43, _logical_T_171)
node _logical_T_386 = dshr(_lut_WIRE[_lut_T], _logical_T_385)
node _logical_T_387 = bits(_logical_T_386, 0, 0)
node _logical_T_388 = cat(_logical_T_44, _logical_T_172)
node _logical_T_389 = dshr(_lut_WIRE[_lut_T], _logical_T_388)
node _logical_T_390 = bits(_logical_T_389, 0, 0)
node _logical_T_391 = cat(_logical_T_45, _logical_T_173)
node _logical_T_392 = dshr(_lut_WIRE[_lut_T], _logical_T_391)
node _logical_T_393 = bits(_logical_T_392, 0, 0)
node _logical_T_394 = cat(_logical_T_46, _logical_T_174)
node _logical_T_395 = dshr(_lut_WIRE[_lut_T], _logical_T_394)
node _logical_T_396 = bits(_logical_T_395, 0, 0)
node _logical_T_397 = cat(_logical_T_47, _logical_T_175)
node _logical_T_398 = dshr(_lut_WIRE[_lut_T], _logical_T_397)
node _logical_T_399 = bits(_logical_T_398, 0, 0)
node _logical_T_400 = cat(_logical_T_48, _logical_T_176)
node _logical_T_401 = dshr(_lut_WIRE[_lut_T], _logical_T_400)
node _logical_T_402 = bits(_logical_T_401, 0, 0)
node _logical_T_403 = cat(_logical_T_49, _logical_T_177)
node _logical_T_404 = dshr(_lut_WIRE[_lut_T], _logical_T_403)
node _logical_T_405 = bits(_logical_T_404, 0, 0)
node _logical_T_406 = cat(_logical_T_50, _logical_T_178)
node _logical_T_407 = dshr(_lut_WIRE[_lut_T], _logical_T_406)
node _logical_T_408 = bits(_logical_T_407, 0, 0)
node _logical_T_409 = cat(_logical_T_51, _logical_T_179)
node _logical_T_410 = dshr(_lut_WIRE[_lut_T], _logical_T_409)
node _logical_T_411 = bits(_logical_T_410, 0, 0)
node _logical_T_412 = cat(_logical_T_52, _logical_T_180)
node _logical_T_413 = dshr(_lut_WIRE[_lut_T], _logical_T_412)
node _logical_T_414 = bits(_logical_T_413, 0, 0)
node _logical_T_415 = cat(_logical_T_53, _logical_T_181)
node _logical_T_416 = dshr(_lut_WIRE[_lut_T], _logical_T_415)
node _logical_T_417 = bits(_logical_T_416, 0, 0)
node _logical_T_418 = cat(_logical_T_54, _logical_T_182)
node _logical_T_419 = dshr(_lut_WIRE[_lut_T], _logical_T_418)
node _logical_T_420 = bits(_logical_T_419, 0, 0)
node _logical_T_421 = cat(_logical_T_55, _logical_T_183)
node _logical_T_422 = dshr(_lut_WIRE[_lut_T], _logical_T_421)
node _logical_T_423 = bits(_logical_T_422, 0, 0)
node _logical_T_424 = cat(_logical_T_56, _logical_T_184)
node _logical_T_425 = dshr(_lut_WIRE[_lut_T], _logical_T_424)
node _logical_T_426 = bits(_logical_T_425, 0, 0)
node _logical_T_427 = cat(_logical_T_57, _logical_T_185)
node _logical_T_428 = dshr(_lut_WIRE[_lut_T], _logical_T_427)
node _logical_T_429 = bits(_logical_T_428, 0, 0)
node _logical_T_430 = cat(_logical_T_58, _logical_T_186)
node _logical_T_431 = dshr(_lut_WIRE[_lut_T], _logical_T_430)
node _logical_T_432 = bits(_logical_T_431, 0, 0)
node _logical_T_433 = cat(_logical_T_59, _logical_T_187)
node _logical_T_434 = dshr(_lut_WIRE[_lut_T], _logical_T_433)
node _logical_T_435 = bits(_logical_T_434, 0, 0)
node _logical_T_436 = cat(_logical_T_60, _logical_T_188)
node _logical_T_437 = dshr(_lut_WIRE[_lut_T], _logical_T_436)
node _logical_T_438 = bits(_logical_T_437, 0, 0)
node _logical_T_439 = cat(_logical_T_61, _logical_T_189)
node _logical_T_440 = dshr(_lut_WIRE[_lut_T], _logical_T_439)
node _logical_T_441 = bits(_logical_T_440, 0, 0)
node _logical_T_442 = cat(_logical_T_62, _logical_T_190)
node _logical_T_443 = dshr(_lut_WIRE[_lut_T], _logical_T_442)
node _logical_T_444 = bits(_logical_T_443, 0, 0)
node _logical_T_445 = cat(_logical_T_63, _logical_T_191)
node _logical_T_446 = dshr(_lut_WIRE[_lut_T], _logical_T_445)
node _logical_T_447 = bits(_logical_T_446, 0, 0)
node _logical_T_448 = cat(_logical_T_64, _logical_T_192)
node _logical_T_449 = dshr(_lut_WIRE[_lut_T], _logical_T_448)
node _logical_T_450 = bits(_logical_T_449, 0, 0)
node _logical_T_451 = cat(_logical_T_65, _logical_T_193)
node _logical_T_452 = dshr(_lut_WIRE[_lut_T], _logical_T_451)
node _logical_T_453 = bits(_logical_T_452, 0, 0)
node _logical_T_454 = cat(_logical_T_66, _logical_T_194)
node _logical_T_455 = dshr(_lut_WIRE[_lut_T], _logical_T_454)
node _logical_T_456 = bits(_logical_T_455, 0, 0)
node _logical_T_457 = cat(_logical_T_67, _logical_T_195)
node _logical_T_458 = dshr(_lut_WIRE[_lut_T], _logical_T_457)
node _logical_T_459 = bits(_logical_T_458, 0, 0)
node _logical_T_460 = cat(_logical_T_68, _logical_T_196)
node _logical_T_461 = dshr(_lut_WIRE[_lut_T], _logical_T_460)
node _logical_T_462 = bits(_logical_T_461, 0, 0)
node _logical_T_463 = cat(_logical_T_69, _logical_T_197)
node _logical_T_464 = dshr(_lut_WIRE[_lut_T], _logical_T_463)
node _logical_T_465 = bits(_logical_T_464, 0, 0)
node _logical_T_466 = cat(_logical_T_70, _logical_T_198)
node _logical_T_467 = dshr(_lut_WIRE[_lut_T], _logical_T_466)
node _logical_T_468 = bits(_logical_T_467, 0, 0)
node _logical_T_469 = cat(_logical_T_71, _logical_T_199)
node _logical_T_470 = dshr(_lut_WIRE[_lut_T], _logical_T_469)
node _logical_T_471 = bits(_logical_T_470, 0, 0)
node _logical_T_472 = cat(_logical_T_72, _logical_T_200)
node _logical_T_473 = dshr(_lut_WIRE[_lut_T], _logical_T_472)
node _logical_T_474 = bits(_logical_T_473, 0, 0)
node _logical_T_475 = cat(_logical_T_73, _logical_T_201)
node _logical_T_476 = dshr(_lut_WIRE[_lut_T], _logical_T_475)
node _logical_T_477 = bits(_logical_T_476, 0, 0)
node _logical_T_478 = cat(_logical_T_74, _logical_T_202)
node _logical_T_479 = dshr(_lut_WIRE[_lut_T], _logical_T_478)
node _logical_T_480 = bits(_logical_T_479, 0, 0)
node _logical_T_481 = cat(_logical_T_75, _logical_T_203)
node _logical_T_482 = dshr(_lut_WIRE[_lut_T], _logical_T_481)
node _logical_T_483 = bits(_logical_T_482, 0, 0)
node _logical_T_484 = cat(_logical_T_76, _logical_T_204)
node _logical_T_485 = dshr(_lut_WIRE[_lut_T], _logical_T_484)
node _logical_T_486 = bits(_logical_T_485, 0, 0)
node _logical_T_487 = cat(_logical_T_77, _logical_T_205)
node _logical_T_488 = dshr(_lut_WIRE[_lut_T], _logical_T_487)
node _logical_T_489 = bits(_logical_T_488, 0, 0)
node _logical_T_490 = cat(_logical_T_78, _logical_T_206)
node _logical_T_491 = dshr(_lut_WIRE[_lut_T], _logical_T_490)
node _logical_T_492 = bits(_logical_T_491, 0, 0)
node _logical_T_493 = cat(_logical_T_79, _logical_T_207)
node _logical_T_494 = dshr(_lut_WIRE[_lut_T], _logical_T_493)
node _logical_T_495 = bits(_logical_T_494, 0, 0)
node _logical_T_496 = cat(_logical_T_80, _logical_T_208)
node _logical_T_497 = dshr(_lut_WIRE[_lut_T], _logical_T_496)
node _logical_T_498 = bits(_logical_T_497, 0, 0)
node _logical_T_499 = cat(_logical_T_81, _logical_T_209)
node _logical_T_500 = dshr(_lut_WIRE[_lut_T], _logical_T_499)
node _logical_T_501 = bits(_logical_T_500, 0, 0)
node _logical_T_502 = cat(_logical_T_82, _logical_T_210)
node _logical_T_503 = dshr(_lut_WIRE[_lut_T], _logical_T_502)
node _logical_T_504 = bits(_logical_T_503, 0, 0)
node _logical_T_505 = cat(_logical_T_83, _logical_T_211)
node _logical_T_506 = dshr(_lut_WIRE[_lut_T], _logical_T_505)
node _logical_T_507 = bits(_logical_T_506, 0, 0)
node _logical_T_508 = cat(_logical_T_84, _logical_T_212)
node _logical_T_509 = dshr(_lut_WIRE[_lut_T], _logical_T_508)
node _logical_T_510 = bits(_logical_T_509, 0, 0)
node _logical_T_511 = cat(_logical_T_85, _logical_T_213)
node _logical_T_512 = dshr(_lut_WIRE[_lut_T], _logical_T_511)
node _logical_T_513 = bits(_logical_T_512, 0, 0)
node _logical_T_514 = cat(_logical_T_86, _logical_T_214)
node _logical_T_515 = dshr(_lut_WIRE[_lut_T], _logical_T_514)
node _logical_T_516 = bits(_logical_T_515, 0, 0)
node _logical_T_517 = cat(_logical_T_87, _logical_T_215)
node _logical_T_518 = dshr(_lut_WIRE[_lut_T], _logical_T_517)
node _logical_T_519 = bits(_logical_T_518, 0, 0)
node _logical_T_520 = cat(_logical_T_88, _logical_T_216)
node _logical_T_521 = dshr(_lut_WIRE[_lut_T], _logical_T_520)
node _logical_T_522 = bits(_logical_T_521, 0, 0)
node _logical_T_523 = cat(_logical_T_89, _logical_T_217)
node _logical_T_524 = dshr(_lut_WIRE[_lut_T], _logical_T_523)
node _logical_T_525 = bits(_logical_T_524, 0, 0)
node _logical_T_526 = cat(_logical_T_90, _logical_T_218)
node _logical_T_527 = dshr(_lut_WIRE[_lut_T], _logical_T_526)
node _logical_T_528 = bits(_logical_T_527, 0, 0)
node _logical_T_529 = cat(_logical_T_91, _logical_T_219)
node _logical_T_530 = dshr(_lut_WIRE[_lut_T], _logical_T_529)
node _logical_T_531 = bits(_logical_T_530, 0, 0)
node _logical_T_532 = cat(_logical_T_92, _logical_T_220)
node _logical_T_533 = dshr(_lut_WIRE[_lut_T], _logical_T_532)
node _logical_T_534 = bits(_logical_T_533, 0, 0)
node _logical_T_535 = cat(_logical_T_93, _logical_T_221)
node _logical_T_536 = dshr(_lut_WIRE[_lut_T], _logical_T_535)
node _logical_T_537 = bits(_logical_T_536, 0, 0)
node _logical_T_538 = cat(_logical_T_94, _logical_T_222)
node _logical_T_539 = dshr(_lut_WIRE[_lut_T], _logical_T_538)
node _logical_T_540 = bits(_logical_T_539, 0, 0)
node _logical_T_541 = cat(_logical_T_95, _logical_T_223)
node _logical_T_542 = dshr(_lut_WIRE[_lut_T], _logical_T_541)
node _logical_T_543 = bits(_logical_T_542, 0, 0)
node _logical_T_544 = cat(_logical_T_96, _logical_T_224)
node _logical_T_545 = dshr(_lut_WIRE[_lut_T], _logical_T_544)
node _logical_T_546 = bits(_logical_T_545, 0, 0)
node _logical_T_547 = cat(_logical_T_97, _logical_T_225)
node _logical_T_548 = dshr(_lut_WIRE[_lut_T], _logical_T_547)
node _logical_T_549 = bits(_logical_T_548, 0, 0)
node _logical_T_550 = cat(_logical_T_98, _logical_T_226)
node _logical_T_551 = dshr(_lut_WIRE[_lut_T], _logical_T_550)
node _logical_T_552 = bits(_logical_T_551, 0, 0)
node _logical_T_553 = cat(_logical_T_99, _logical_T_227)
node _logical_T_554 = dshr(_lut_WIRE[_lut_T], _logical_T_553)
node _logical_T_555 = bits(_logical_T_554, 0, 0)
node _logical_T_556 = cat(_logical_T_100, _logical_T_228)
node _logical_T_557 = dshr(_lut_WIRE[_lut_T], _logical_T_556)
node _logical_T_558 = bits(_logical_T_557, 0, 0)
node _logical_T_559 = cat(_logical_T_101, _logical_T_229)
node _logical_T_560 = dshr(_lut_WIRE[_lut_T], _logical_T_559)
node _logical_T_561 = bits(_logical_T_560, 0, 0)
node _logical_T_562 = cat(_logical_T_102, _logical_T_230)
node _logical_T_563 = dshr(_lut_WIRE[_lut_T], _logical_T_562)
node _logical_T_564 = bits(_logical_T_563, 0, 0)
node _logical_T_565 = cat(_logical_T_103, _logical_T_231)
node _logical_T_566 = dshr(_lut_WIRE[_lut_T], _logical_T_565)
node _logical_T_567 = bits(_logical_T_566, 0, 0)
node _logical_T_568 = cat(_logical_T_104, _logical_T_232)
node _logical_T_569 = dshr(_lut_WIRE[_lut_T], _logical_T_568)
node _logical_T_570 = bits(_logical_T_569, 0, 0)
node _logical_T_571 = cat(_logical_T_105, _logical_T_233)
node _logical_T_572 = dshr(_lut_WIRE[_lut_T], _logical_T_571)
node _logical_T_573 = bits(_logical_T_572, 0, 0)
node _logical_T_574 = cat(_logical_T_106, _logical_T_234)
node _logical_T_575 = dshr(_lut_WIRE[_lut_T], _logical_T_574)
node _logical_T_576 = bits(_logical_T_575, 0, 0)
node _logical_T_577 = cat(_logical_T_107, _logical_T_235)
node _logical_T_578 = dshr(_lut_WIRE[_lut_T], _logical_T_577)
node _logical_T_579 = bits(_logical_T_578, 0, 0)
node _logical_T_580 = cat(_logical_T_108, _logical_T_236)
node _logical_T_581 = dshr(_lut_WIRE[_lut_T], _logical_T_580)
node _logical_T_582 = bits(_logical_T_581, 0, 0)
node _logical_T_583 = cat(_logical_T_109, _logical_T_237)
node _logical_T_584 = dshr(_lut_WIRE[_lut_T], _logical_T_583)
node _logical_T_585 = bits(_logical_T_584, 0, 0)
node _logical_T_586 = cat(_logical_T_110, _logical_T_238)
node _logical_T_587 = dshr(_lut_WIRE[_lut_T], _logical_T_586)
node _logical_T_588 = bits(_logical_T_587, 0, 0)
node _logical_T_589 = cat(_logical_T_111, _logical_T_239)
node _logical_T_590 = dshr(_lut_WIRE[_lut_T], _logical_T_589)
node _logical_T_591 = bits(_logical_T_590, 0, 0)
node _logical_T_592 = cat(_logical_T_112, _logical_T_240)
node _logical_T_593 = dshr(_lut_WIRE[_lut_T], _logical_T_592)
node _logical_T_594 = bits(_logical_T_593, 0, 0)
node _logical_T_595 = cat(_logical_T_113, _logical_T_241)
node _logical_T_596 = dshr(_lut_WIRE[_lut_T], _logical_T_595)
node _logical_T_597 = bits(_logical_T_596, 0, 0)
node _logical_T_598 = cat(_logical_T_114, _logical_T_242)
node _logical_T_599 = dshr(_lut_WIRE[_lut_T], _logical_T_598)
node _logical_T_600 = bits(_logical_T_599, 0, 0)
node _logical_T_601 = cat(_logical_T_115, _logical_T_243)
node _logical_T_602 = dshr(_lut_WIRE[_lut_T], _logical_T_601)
node _logical_T_603 = bits(_logical_T_602, 0, 0)
node _logical_T_604 = cat(_logical_T_116, _logical_T_244)
node _logical_T_605 = dshr(_lut_WIRE[_lut_T], _logical_T_604)
node _logical_T_606 = bits(_logical_T_605, 0, 0)
node _logical_T_607 = cat(_logical_T_117, _logical_T_245)
node _logical_T_608 = dshr(_lut_WIRE[_lut_T], _logical_T_607)
node _logical_T_609 = bits(_logical_T_608, 0, 0)
node _logical_T_610 = cat(_logical_T_118, _logical_T_246)
node _logical_T_611 = dshr(_lut_WIRE[_lut_T], _logical_T_610)
node _logical_T_612 = bits(_logical_T_611, 0, 0)
node _logical_T_613 = cat(_logical_T_119, _logical_T_247)
node _logical_T_614 = dshr(_lut_WIRE[_lut_T], _logical_T_613)
node _logical_T_615 = bits(_logical_T_614, 0, 0)
node _logical_T_616 = cat(_logical_T_120, _logical_T_248)
node _logical_T_617 = dshr(_lut_WIRE[_lut_T], _logical_T_616)
node _logical_T_618 = bits(_logical_T_617, 0, 0)
node _logical_T_619 = cat(_logical_T_121, _logical_T_249)
node _logical_T_620 = dshr(_lut_WIRE[_lut_T], _logical_T_619)
node _logical_T_621 = bits(_logical_T_620, 0, 0)
node _logical_T_622 = cat(_logical_T_122, _logical_T_250)
node _logical_T_623 = dshr(_lut_WIRE[_lut_T], _logical_T_622)
node _logical_T_624 = bits(_logical_T_623, 0, 0)
node _logical_T_625 = cat(_logical_T_123, _logical_T_251)
node _logical_T_626 = dshr(_lut_WIRE[_lut_T], _logical_T_625)
node _logical_T_627 = bits(_logical_T_626, 0, 0)
node _logical_T_628 = cat(_logical_T_124, _logical_T_252)
node _logical_T_629 = dshr(_lut_WIRE[_lut_T], _logical_T_628)
node _logical_T_630 = bits(_logical_T_629, 0, 0)
node _logical_T_631 = cat(_logical_T_125, _logical_T_253)
node _logical_T_632 = dshr(_lut_WIRE[_lut_T], _logical_T_631)
node _logical_T_633 = bits(_logical_T_632, 0, 0)
node _logical_T_634 = cat(_logical_T_126, _logical_T_254)
node _logical_T_635 = dshr(_lut_WIRE[_lut_T], _logical_T_634)
node _logical_T_636 = bits(_logical_T_635, 0, 0)
node _logical_T_637 = cat(_logical_T_127, _logical_T_255)
node _logical_T_638 = dshr(_lut_WIRE[_lut_T], _logical_T_637)
node _logical_T_639 = bits(_logical_T_638, 0, 0)
node logical_lo_lo_lo_lo_lo_lo = cat(_logical_T_261, _logical_T_258)
node logical_lo_lo_lo_lo_lo_hi = cat(_logical_T_267, _logical_T_264)
node logical_lo_lo_lo_lo_lo = cat(logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo)
node logical_lo_lo_lo_lo_hi_lo = cat(_logical_T_273, _logical_T_270)
node logical_lo_lo_lo_lo_hi_hi = cat(_logical_T_279, _logical_T_276)
node logical_lo_lo_lo_lo_hi = cat(logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo)
node logical_lo_lo_lo_lo = cat(logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo)
node logical_lo_lo_lo_hi_lo_lo = cat(_logical_T_285, _logical_T_282)
node logical_lo_lo_lo_hi_lo_hi = cat(_logical_T_291, _logical_T_288)
node logical_lo_lo_lo_hi_lo = cat(logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo)
node logical_lo_lo_lo_hi_hi_lo = cat(_logical_T_297, _logical_T_294)
node logical_lo_lo_lo_hi_hi_hi = cat(_logical_T_303, _logical_T_300)
node logical_lo_lo_lo_hi_hi = cat(logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo)
node logical_lo_lo_lo_hi = cat(logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo)
node logical_lo_lo_lo = cat(logical_lo_lo_lo_hi, logical_lo_lo_lo_lo)
node logical_lo_lo_hi_lo_lo_lo = cat(_logical_T_309, _logical_T_306)
node logical_lo_lo_hi_lo_lo_hi = cat(_logical_T_315, _logical_T_312)
node logical_lo_lo_hi_lo_lo = cat(logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo)
node logical_lo_lo_hi_lo_hi_lo = cat(_logical_T_321, _logical_T_318)
node logical_lo_lo_hi_lo_hi_hi = cat(_logical_T_327, _logical_T_324)
node logical_lo_lo_hi_lo_hi = cat(logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo)
node logical_lo_lo_hi_lo = cat(logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo)
node logical_lo_lo_hi_hi_lo_lo = cat(_logical_T_333, _logical_T_330)
node logical_lo_lo_hi_hi_lo_hi = cat(_logical_T_339, _logical_T_336)
node logical_lo_lo_hi_hi_lo = cat(logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo)
node logical_lo_lo_hi_hi_hi_lo = cat(_logical_T_345, _logical_T_342)
node logical_lo_lo_hi_hi_hi_hi = cat(_logical_T_351, _logical_T_348)
node logical_lo_lo_hi_hi_hi = cat(logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo)
node logical_lo_lo_hi_hi = cat(logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo)
node logical_lo_lo_hi = cat(logical_lo_lo_hi_hi, logical_lo_lo_hi_lo)
node logical_lo_lo = cat(logical_lo_lo_hi, logical_lo_lo_lo)
node logical_lo_hi_lo_lo_lo_lo = cat(_logical_T_357, _logical_T_354)
node logical_lo_hi_lo_lo_lo_hi = cat(_logical_T_363, _logical_T_360)
node logical_lo_hi_lo_lo_lo = cat(logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo)
node logical_lo_hi_lo_lo_hi_lo = cat(_logical_T_369, _logical_T_366)
node logical_lo_hi_lo_lo_hi_hi = cat(_logical_T_375, _logical_T_372)
node logical_lo_hi_lo_lo_hi = cat(logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo)
node logical_lo_hi_lo_lo = cat(logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo)
node logical_lo_hi_lo_hi_lo_lo = cat(_logical_T_381, _logical_T_378)
node logical_lo_hi_lo_hi_lo_hi = cat(_logical_T_387, _logical_T_384)
node logical_lo_hi_lo_hi_lo = cat(logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo)
node logical_lo_hi_lo_hi_hi_lo = cat(_logical_T_393, _logical_T_390)
node logical_lo_hi_lo_hi_hi_hi = cat(_logical_T_399, _logical_T_396)
node logical_lo_hi_lo_hi_hi = cat(logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo)
node logical_lo_hi_lo_hi = cat(logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo)
node logical_lo_hi_lo = cat(logical_lo_hi_lo_hi, logical_lo_hi_lo_lo)
node logical_lo_hi_hi_lo_lo_lo = cat(_logical_T_405, _logical_T_402)
node logical_lo_hi_hi_lo_lo_hi = cat(_logical_T_411, _logical_T_408)
node logical_lo_hi_hi_lo_lo = cat(logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo)
node logical_lo_hi_hi_lo_hi_lo = cat(_logical_T_417, _logical_T_414)
node logical_lo_hi_hi_lo_hi_hi = cat(_logical_T_423, _logical_T_420)
node logical_lo_hi_hi_lo_hi = cat(logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo)
node logical_lo_hi_hi_lo = cat(logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo)
node logical_lo_hi_hi_hi_lo_lo = cat(_logical_T_429, _logical_T_426)
node logical_lo_hi_hi_hi_lo_hi = cat(_logical_T_435, _logical_T_432)
node logical_lo_hi_hi_hi_lo = cat(logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo)
node logical_lo_hi_hi_hi_hi_lo = cat(_logical_T_441, _logical_T_438)
node logical_lo_hi_hi_hi_hi_hi = cat(_logical_T_447, _logical_T_444)
node logical_lo_hi_hi_hi_hi = cat(logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo)
node logical_lo_hi_hi_hi = cat(logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo)
node logical_lo_hi_hi = cat(logical_lo_hi_hi_hi, logical_lo_hi_hi_lo)
node logical_lo_hi = cat(logical_lo_hi_hi, logical_lo_hi_lo)
node logical_lo = cat(logical_lo_hi, logical_lo_lo)
node logical_hi_lo_lo_lo_lo_lo = cat(_logical_T_453, _logical_T_450)
node logical_hi_lo_lo_lo_lo_hi = cat(_logical_T_459, _logical_T_456)
node logical_hi_lo_lo_lo_lo = cat(logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo)
node logical_hi_lo_lo_lo_hi_lo = cat(_logical_T_465, _logical_T_462)
node logical_hi_lo_lo_lo_hi_hi = cat(_logical_T_471, _logical_T_468)
node logical_hi_lo_lo_lo_hi = cat(logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo)
node logical_hi_lo_lo_lo = cat(logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo)
node logical_hi_lo_lo_hi_lo_lo = cat(_logical_T_477, _logical_T_474)
node logical_hi_lo_lo_hi_lo_hi = cat(_logical_T_483, _logical_T_480)
node logical_hi_lo_lo_hi_lo = cat(logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo)
node logical_hi_lo_lo_hi_hi_lo = cat(_logical_T_489, _logical_T_486)
node logical_hi_lo_lo_hi_hi_hi = cat(_logical_T_495, _logical_T_492)
node logical_hi_lo_lo_hi_hi = cat(logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo)
node logical_hi_lo_lo_hi = cat(logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo)
node logical_hi_lo_lo = cat(logical_hi_lo_lo_hi, logical_hi_lo_lo_lo)
node logical_hi_lo_hi_lo_lo_lo = cat(_logical_T_501, _logical_T_498)
node logical_hi_lo_hi_lo_lo_hi = cat(_logical_T_507, _logical_T_504)
node logical_hi_lo_hi_lo_lo = cat(logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo)
node logical_hi_lo_hi_lo_hi_lo = cat(_logical_T_513, _logical_T_510)
node logical_hi_lo_hi_lo_hi_hi = cat(_logical_T_519, _logical_T_516)
node logical_hi_lo_hi_lo_hi = cat(logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo)
node logical_hi_lo_hi_lo = cat(logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo)
node logical_hi_lo_hi_hi_lo_lo = cat(_logical_T_525, _logical_T_522)
node logical_hi_lo_hi_hi_lo_hi = cat(_logical_T_531, _logical_T_528)
node logical_hi_lo_hi_hi_lo = cat(logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo)
node logical_hi_lo_hi_hi_hi_lo = cat(_logical_T_537, _logical_T_534)
node logical_hi_lo_hi_hi_hi_hi = cat(_logical_T_543, _logical_T_540)
node logical_hi_lo_hi_hi_hi = cat(logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo)
node logical_hi_lo_hi_hi = cat(logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo)
node logical_hi_lo_hi = cat(logical_hi_lo_hi_hi, logical_hi_lo_hi_lo)
node logical_hi_lo = cat(logical_hi_lo_hi, logical_hi_lo_lo)
node logical_hi_hi_lo_lo_lo_lo = cat(_logical_T_549, _logical_T_546)
node logical_hi_hi_lo_lo_lo_hi = cat(_logical_T_555, _logical_T_552)
node logical_hi_hi_lo_lo_lo = cat(logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo)
node logical_hi_hi_lo_lo_hi_lo = cat(_logical_T_561, _logical_T_558)
node logical_hi_hi_lo_lo_hi_hi = cat(_logical_T_567, _logical_T_564)
node logical_hi_hi_lo_lo_hi = cat(logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo)
node logical_hi_hi_lo_lo = cat(logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo)
node logical_hi_hi_lo_hi_lo_lo = cat(_logical_T_573, _logical_T_570)
node logical_hi_hi_lo_hi_lo_hi = cat(_logical_T_579, _logical_T_576)
node logical_hi_hi_lo_hi_lo = cat(logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo)
node logical_hi_hi_lo_hi_hi_lo = cat(_logical_T_585, _logical_T_582)
node logical_hi_hi_lo_hi_hi_hi = cat(_logical_T_591, _logical_T_588)
node logical_hi_hi_lo_hi_hi = cat(logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo)
node logical_hi_hi_lo_hi = cat(logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo)
node logical_hi_hi_lo = cat(logical_hi_hi_lo_hi, logical_hi_hi_lo_lo)
node logical_hi_hi_hi_lo_lo_lo = cat(_logical_T_597, _logical_T_594)
node logical_hi_hi_hi_lo_lo_hi = cat(_logical_T_603, _logical_T_600)
node logical_hi_hi_hi_lo_lo = cat(logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo)
node logical_hi_hi_hi_lo_hi_lo = cat(_logical_T_609, _logical_T_606)
node logical_hi_hi_hi_lo_hi_hi = cat(_logical_T_615, _logical_T_612)
node logical_hi_hi_hi_lo_hi = cat(logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo)
node logical_hi_hi_hi_lo = cat(logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo)
node logical_hi_hi_hi_hi_lo_lo = cat(_logical_T_621, _logical_T_618)
node logical_hi_hi_hi_hi_lo_hi = cat(_logical_T_627, _logical_T_624)
node logical_hi_hi_hi_hi_lo = cat(logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo)
node logical_hi_hi_hi_hi_hi_lo = cat(_logical_T_633, _logical_T_630)
node logical_hi_hi_hi_hi_hi_hi = cat(_logical_T_639, _logical_T_636)
node logical_hi_hi_hi_hi_hi = cat(logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo)
node logical_hi_hi_hi_hi = cat(logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo)
node logical_hi_hi_hi = cat(logical_hi_hi_hi_hi, logical_hi_hi_hi_lo)
node logical_hi_hi = cat(logical_hi_hi_hi, logical_hi_hi_lo)
node logical_hi = cat(logical_hi_hi, logical_hi_lo)
node logical = cat(logical_hi, logical_lo)
node _select_T = mux(pick_a, UInt<1>(0h1), UInt<1>(0h0))
node _select_T_1 = mux(adder, UInt<2>(0h2), _select_T)
wire _select_WIRE : UInt<2>[8]
connect _select_WIRE[0], UInt<1>(0h1)
connect _select_WIRE[1], UInt<1>(0h1)
connect _select_WIRE[2], _select_T_1
connect _select_WIRE[3], UInt<2>(0h3)
connect _select_WIRE[4], UInt<1>(0h0)
connect _select_WIRE[5], UInt<1>(0h0)
connect _select_WIRE[6], UInt<1>(0h0)
connect _select_WIRE[7], UInt<1>(0h0)
node select = mux(io.write, UInt<1>(0h1), _select_WIRE[io.a.opcode])
node _selects_T = bits(io.a.mask, 0, 0)
node _selects_T_1 = bits(io.a.mask, 1, 1)
node _selects_T_2 = bits(io.a.mask, 2, 2)
node _selects_T_3 = bits(io.a.mask, 3, 3)
node _selects_T_4 = bits(io.a.mask, 4, 4)
node _selects_T_5 = bits(io.a.mask, 5, 5)
node _selects_T_6 = bits(io.a.mask, 6, 6)
node _selects_T_7 = bits(io.a.mask, 7, 7)
node _selects_T_8 = bits(io.a.mask, 8, 8)
node _selects_T_9 = bits(io.a.mask, 9, 9)
node _selects_T_10 = bits(io.a.mask, 10, 10)
node _selects_T_11 = bits(io.a.mask, 11, 11)
node _selects_T_12 = bits(io.a.mask, 12, 12)
node _selects_T_13 = bits(io.a.mask, 13, 13)
node _selects_T_14 = bits(io.a.mask, 14, 14)
node _selects_T_15 = bits(io.a.mask, 15, 15)
node selects_0 = mux(_selects_T, select, UInt<1>(0h0))
node selects_1 = mux(_selects_T_1, select, UInt<1>(0h0))
node selects_2 = mux(_selects_T_2, select, UInt<1>(0h0))
node selects_3 = mux(_selects_T_3, select, UInt<1>(0h0))
node selects_4 = mux(_selects_T_4, select, UInt<1>(0h0))
node selects_5 = mux(_selects_T_5, select, UInt<1>(0h0))
node selects_6 = mux(_selects_T_6, select, UInt<1>(0h0))
node selects_7 = mux(_selects_T_7, select, UInt<1>(0h0))
node selects_8 = mux(_selects_T_8, select, UInt<1>(0h0))
node selects_9 = mux(_selects_T_9, select, UInt<1>(0h0))
node selects_10 = mux(_selects_T_10, select, UInt<1>(0h0))
node selects_11 = mux(_selects_T_11, select, UInt<1>(0h0))
node selects_12 = mux(_selects_T_12, select, UInt<1>(0h0))
node selects_13 = mux(_selects_T_13, select, UInt<1>(0h0))
node selects_14 = mux(_selects_T_14, select, UInt<1>(0h0))
node selects_15 = mux(_selects_T_15, select, UInt<1>(0h0))
node _io_data_out_T = bits(io.data_in, 7, 0)
node _io_data_out_T_1 = bits(io.a.data, 7, 0)
node _io_data_out_T_2 = bits(sum, 7, 0)
node _io_data_out_T_3 = bits(logical, 7, 0)
wire _io_data_out_WIRE : UInt<8>[4]
connect _io_data_out_WIRE[0], _io_data_out_T
connect _io_data_out_WIRE[1], _io_data_out_T_1
connect _io_data_out_WIRE[2], _io_data_out_T_2
connect _io_data_out_WIRE[3], _io_data_out_T_3
node _io_data_out_T_4 = bits(io.data_in, 15, 8)
node _io_data_out_T_5 = bits(io.a.data, 15, 8)
node _io_data_out_T_6 = bits(sum, 15, 8)
node _io_data_out_T_7 = bits(logical, 15, 8)
wire _io_data_out_WIRE_1 : UInt<8>[4]
connect _io_data_out_WIRE_1[0], _io_data_out_T_4
connect _io_data_out_WIRE_1[1], _io_data_out_T_5
connect _io_data_out_WIRE_1[2], _io_data_out_T_6
connect _io_data_out_WIRE_1[3], _io_data_out_T_7
node _io_data_out_T_8 = bits(io.data_in, 23, 16)
node _io_data_out_T_9 = bits(io.a.data, 23, 16)
node _io_data_out_T_10 = bits(sum, 23, 16)
node _io_data_out_T_11 = bits(logical, 23, 16)
wire _io_data_out_WIRE_2 : UInt<8>[4]
connect _io_data_out_WIRE_2[0], _io_data_out_T_8
connect _io_data_out_WIRE_2[1], _io_data_out_T_9
connect _io_data_out_WIRE_2[2], _io_data_out_T_10
connect _io_data_out_WIRE_2[3], _io_data_out_T_11
node _io_data_out_T_12 = bits(io.data_in, 31, 24)
node _io_data_out_T_13 = bits(io.a.data, 31, 24)
node _io_data_out_T_14 = bits(sum, 31, 24)
node _io_data_out_T_15 = bits(logical, 31, 24)
wire _io_data_out_WIRE_3 : UInt<8>[4]
connect _io_data_out_WIRE_3[0], _io_data_out_T_12
connect _io_data_out_WIRE_3[1], _io_data_out_T_13
connect _io_data_out_WIRE_3[2], _io_data_out_T_14
connect _io_data_out_WIRE_3[3], _io_data_out_T_15
node _io_data_out_T_16 = bits(io.data_in, 39, 32)
node _io_data_out_T_17 = bits(io.a.data, 39, 32)
node _io_data_out_T_18 = bits(sum, 39, 32)
node _io_data_out_T_19 = bits(logical, 39, 32)
wire _io_data_out_WIRE_4 : UInt<8>[4]
connect _io_data_out_WIRE_4[0], _io_data_out_T_16
connect _io_data_out_WIRE_4[1], _io_data_out_T_17
connect _io_data_out_WIRE_4[2], _io_data_out_T_18
connect _io_data_out_WIRE_4[3], _io_data_out_T_19
node _io_data_out_T_20 = bits(io.data_in, 47, 40)
node _io_data_out_T_21 = bits(io.a.data, 47, 40)
node _io_data_out_T_22 = bits(sum, 47, 40)
node _io_data_out_T_23 = bits(logical, 47, 40)
wire _io_data_out_WIRE_5 : UInt<8>[4]
connect _io_data_out_WIRE_5[0], _io_data_out_T_20
connect _io_data_out_WIRE_5[1], _io_data_out_T_21
connect _io_data_out_WIRE_5[2], _io_data_out_T_22
connect _io_data_out_WIRE_5[3], _io_data_out_T_23
node _io_data_out_T_24 = bits(io.data_in, 55, 48)
node _io_data_out_T_25 = bits(io.a.data, 55, 48)
node _io_data_out_T_26 = bits(sum, 55, 48)
node _io_data_out_T_27 = bits(logical, 55, 48)
wire _io_data_out_WIRE_6 : UInt<8>[4]
connect _io_data_out_WIRE_6[0], _io_data_out_T_24
connect _io_data_out_WIRE_6[1], _io_data_out_T_25
connect _io_data_out_WIRE_6[2], _io_data_out_T_26
connect _io_data_out_WIRE_6[3], _io_data_out_T_27
node _io_data_out_T_28 = bits(io.data_in, 63, 56)
node _io_data_out_T_29 = bits(io.a.data, 63, 56)
node _io_data_out_T_30 = bits(sum, 63, 56)
node _io_data_out_T_31 = bits(logical, 63, 56)
wire _io_data_out_WIRE_7 : UInt<8>[4]
connect _io_data_out_WIRE_7[0], _io_data_out_T_28
connect _io_data_out_WIRE_7[1], _io_data_out_T_29
connect _io_data_out_WIRE_7[2], _io_data_out_T_30
connect _io_data_out_WIRE_7[3], _io_data_out_T_31
node _io_data_out_T_32 = bits(io.data_in, 71, 64)
node _io_data_out_T_33 = bits(io.a.data, 71, 64)
node _io_data_out_T_34 = bits(sum, 71, 64)
node _io_data_out_T_35 = bits(logical, 71, 64)
wire _io_data_out_WIRE_8 : UInt<8>[4]
connect _io_data_out_WIRE_8[0], _io_data_out_T_32
connect _io_data_out_WIRE_8[1], _io_data_out_T_33
connect _io_data_out_WIRE_8[2], _io_data_out_T_34
connect _io_data_out_WIRE_8[3], _io_data_out_T_35
node _io_data_out_T_36 = bits(io.data_in, 79, 72)
node _io_data_out_T_37 = bits(io.a.data, 79, 72)
node _io_data_out_T_38 = bits(sum, 79, 72)
node _io_data_out_T_39 = bits(logical, 79, 72)
wire _io_data_out_WIRE_9 : UInt<8>[4]
connect _io_data_out_WIRE_9[0], _io_data_out_T_36
connect _io_data_out_WIRE_9[1], _io_data_out_T_37
connect _io_data_out_WIRE_9[2], _io_data_out_T_38
connect _io_data_out_WIRE_9[3], _io_data_out_T_39
node _io_data_out_T_40 = bits(io.data_in, 87, 80)
node _io_data_out_T_41 = bits(io.a.data, 87, 80)
node _io_data_out_T_42 = bits(sum, 87, 80)
node _io_data_out_T_43 = bits(logical, 87, 80)
wire _io_data_out_WIRE_10 : UInt<8>[4]
connect _io_data_out_WIRE_10[0], _io_data_out_T_40
connect _io_data_out_WIRE_10[1], _io_data_out_T_41
connect _io_data_out_WIRE_10[2], _io_data_out_T_42
connect _io_data_out_WIRE_10[3], _io_data_out_T_43
node _io_data_out_T_44 = bits(io.data_in, 95, 88)
node _io_data_out_T_45 = bits(io.a.data, 95, 88)
node _io_data_out_T_46 = bits(sum, 95, 88)
node _io_data_out_T_47 = bits(logical, 95, 88)
wire _io_data_out_WIRE_11 : UInt<8>[4]
connect _io_data_out_WIRE_11[0], _io_data_out_T_44
connect _io_data_out_WIRE_11[1], _io_data_out_T_45
connect _io_data_out_WIRE_11[2], _io_data_out_T_46
connect _io_data_out_WIRE_11[3], _io_data_out_T_47
node _io_data_out_T_48 = bits(io.data_in, 103, 96)
node _io_data_out_T_49 = bits(io.a.data, 103, 96)
node _io_data_out_T_50 = bits(sum, 103, 96)
node _io_data_out_T_51 = bits(logical, 103, 96)
wire _io_data_out_WIRE_12 : UInt<8>[4]
connect _io_data_out_WIRE_12[0], _io_data_out_T_48
connect _io_data_out_WIRE_12[1], _io_data_out_T_49
connect _io_data_out_WIRE_12[2], _io_data_out_T_50
connect _io_data_out_WIRE_12[3], _io_data_out_T_51
node _io_data_out_T_52 = bits(io.data_in, 111, 104)
node _io_data_out_T_53 = bits(io.a.data, 111, 104)
node _io_data_out_T_54 = bits(sum, 111, 104)
node _io_data_out_T_55 = bits(logical, 111, 104)
wire _io_data_out_WIRE_13 : UInt<8>[4]
connect _io_data_out_WIRE_13[0], _io_data_out_T_52
connect _io_data_out_WIRE_13[1], _io_data_out_T_53
connect _io_data_out_WIRE_13[2], _io_data_out_T_54
connect _io_data_out_WIRE_13[3], _io_data_out_T_55
node _io_data_out_T_56 = bits(io.data_in, 119, 112)
node _io_data_out_T_57 = bits(io.a.data, 119, 112)
node _io_data_out_T_58 = bits(sum, 119, 112)
node _io_data_out_T_59 = bits(logical, 119, 112)
wire _io_data_out_WIRE_14 : UInt<8>[4]
connect _io_data_out_WIRE_14[0], _io_data_out_T_56
connect _io_data_out_WIRE_14[1], _io_data_out_T_57
connect _io_data_out_WIRE_14[2], _io_data_out_T_58
connect _io_data_out_WIRE_14[3], _io_data_out_T_59
node _io_data_out_T_60 = bits(io.data_in, 127, 120)
node _io_data_out_T_61 = bits(io.a.data, 127, 120)
node _io_data_out_T_62 = bits(sum, 127, 120)
node _io_data_out_T_63 = bits(logical, 127, 120)
wire _io_data_out_WIRE_15 : UInt<8>[4]
connect _io_data_out_WIRE_15[0], _io_data_out_T_60
connect _io_data_out_WIRE_15[1], _io_data_out_T_61
connect _io_data_out_WIRE_15[2], _io_data_out_T_62
connect _io_data_out_WIRE_15[3], _io_data_out_T_63
node io_data_out_lo_lo_lo = cat(_io_data_out_WIRE_1[selects_1], _io_data_out_WIRE[selects_0])
node io_data_out_lo_lo_hi = cat(_io_data_out_WIRE_3[selects_3], _io_data_out_WIRE_2[selects_2])
node io_data_out_lo_lo = cat(io_data_out_lo_lo_hi, io_data_out_lo_lo_lo)
node io_data_out_lo_hi_lo = cat(_io_data_out_WIRE_5[selects_5], _io_data_out_WIRE_4[selects_4])
node io_data_out_lo_hi_hi = cat(_io_data_out_WIRE_7[selects_7], _io_data_out_WIRE_6[selects_6])
node io_data_out_lo_hi = cat(io_data_out_lo_hi_hi, io_data_out_lo_hi_lo)
node io_data_out_lo = cat(io_data_out_lo_hi, io_data_out_lo_lo)
node io_data_out_hi_lo_lo = cat(_io_data_out_WIRE_9[selects_9], _io_data_out_WIRE_8[selects_8])
node io_data_out_hi_lo_hi = cat(_io_data_out_WIRE_11[selects_11], _io_data_out_WIRE_10[selects_10])
node io_data_out_hi_lo = cat(io_data_out_hi_lo_hi, io_data_out_hi_lo_lo)
node io_data_out_hi_hi_lo = cat(_io_data_out_WIRE_13[selects_13], _io_data_out_WIRE_12[selects_12])
node io_data_out_hi_hi_hi = cat(_io_data_out_WIRE_15[selects_15], _io_data_out_WIRE_14[selects_14])
node io_data_out_hi_hi = cat(io_data_out_hi_hi_hi, io_data_out_hi_hi_lo)
node io_data_out_hi = cat(io_data_out_hi_hi, io_data_out_hi_lo)
node _io_data_out_T_64 = cat(io_data_out_hi, io_data_out_lo)
connect io.data_out, _io_data_out_T_64 | module Atomics_3( // @[Atomics.scala:8:7]
input clock, // @[Atomics.scala:8:7]
input reset, // @[Atomics.scala:8:7]
input io_write, // @[Atomics.scala:10:14]
input [2:0] io_a_opcode, // @[Atomics.scala:10:14]
input [2:0] io_a_param, // @[Atomics.scala:10:14]
input [15:0] io_a_mask, // @[Atomics.scala:10:14]
input [127:0] io_a_data, // @[Atomics.scala:10:14]
input [127:0] io_data_in, // @[Atomics.scala:10:14]
output [127:0] io_data_out // @[Atomics.scala:10:14]
);
wire io_write_0 = io_write; // @[Atomics.scala:8:7]
wire [2:0] io_a_opcode_0 = io_a_opcode; // @[Atomics.scala:8:7]
wire [2:0] io_a_param_0 = io_a_param; // @[Atomics.scala:8:7]
wire [15:0] io_a_mask_0 = io_a_mask; // @[Atomics.scala:8:7]
wire [127:0] io_a_data_0 = io_a_data; // @[Atomics.scala:8:7]
wire [127:0] io_data_in_0 = io_data_in; // @[Atomics.scala:8:7]
wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6};
wire [3:0] _lut_WIRE_0 = 4'h6; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_1 = 4'hE; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_2 = 4'h8; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_3 = 4'hC; // @[Atomics.scala:34:20]
wire [1:0] _select_WIRE_0 = 2'h1; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_1 = 2'h1; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_3 = 2'h3; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_4 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_5 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_6 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_7 = 2'h0; // @[Atomics.scala:45:42]
wire io_a_corrupt = 1'h0; // @[Atomics.scala:8:7, :10:14]
wire [31:0] io_a_address = 32'h0; // @[Atomics.scala:8:7, :10:14]
wire [5:0] io_a_source = 6'h0; // @[Atomics.scala:8:7, :10:14]
wire [2:0] io_a_size = 3'h0; // @[Atomics.scala:8:7, :10:14]
wire [127:0] _io_data_out_T_64; // @[Atomics.scala:58:21]
wire [127:0] io_data_out_0; // @[Atomics.scala:8:7]
wire adder = io_a_param_0[2]; // @[Atomics.scala:8:7, :18:28]
wire unsigned_0 = io_a_param_0[1]; // @[Atomics.scala:8:7, :19:28]
wire take_max = io_a_param_0[0]; // @[Atomics.scala:8:7, :20:28]
wire [15:0] _signBit_T = ~io_a_mask_0; // @[Atomics.scala:8:7, :22:38]
wire [14:0] _signBit_T_1 = _signBit_T[15:1]; // @[Atomics.scala:22:{38,49}]
wire [15:0] _signBit_T_2 = {1'h1, _signBit_T_1}; // @[Atomics.scala:22:{32,49}]
wire [15:0] signBit = io_a_mask_0 & _signBit_T_2; // @[Atomics.scala:8:7, :22:{27,32}]
wire [127:0] _inv_d_T = ~io_data_in_0; // @[Atomics.scala:8:7, :23:38]
wire [127:0] inv_d = adder ? io_data_in_0 : _inv_d_T; // @[Atomics.scala:8:7, :18:28, :23:{18,38}]
wire _sum_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_4 = io_a_mask_0[4]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_5 = io_a_mask_0[5]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_6 = io_a_mask_0[6]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_7 = io_a_mask_0[7]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_8 = io_a_mask_0[8]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_9 = io_a_mask_0[9]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_10 = io_a_mask_0[10]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_11 = io_a_mask_0[11]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_12 = io_a_mask_0[12]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_13 = io_a_mask_0[13]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_14 = io_a_mask_0[14]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_15 = io_a_mask_0[15]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire [7:0] _sum_T_16 = {8{_sum_T}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_17 = {8{_sum_T_1}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_18 = {8{_sum_T_2}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_19 = {8{_sum_T_3}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_20 = {8{_sum_T_4}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_21 = {8{_sum_T_5}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_22 = {8{_sum_T_6}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_23 = {8{_sum_T_7}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_24 = {8{_sum_T_8}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_25 = {8{_sum_T_9}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_26 = {8{_sum_T_10}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_27 = {8{_sum_T_11}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_28 = {8{_sum_T_12}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_29 = {8{_sum_T_13}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_30 = {8{_sum_T_14}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_31 = {8{_sum_T_15}}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_lo_lo = {_sum_T_17, _sum_T_16}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_lo_hi = {_sum_T_19, _sum_T_18}; // @[Atomics.scala:24:29]
wire [31:0] sum_lo_lo = {sum_lo_lo_hi, sum_lo_lo_lo}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_hi_lo = {_sum_T_21, _sum_T_20}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo_hi_hi = {_sum_T_23, _sum_T_22}; // @[Atomics.scala:24:29]
wire [31:0] sum_lo_hi = {sum_lo_hi_hi, sum_lo_hi_lo}; // @[Atomics.scala:24:29]
wire [63:0] sum_lo = {sum_lo_hi, sum_lo_lo}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_lo_lo = {_sum_T_25, _sum_T_24}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_lo_hi = {_sum_T_27, _sum_T_26}; // @[Atomics.scala:24:29]
wire [31:0] sum_hi_lo = {sum_hi_lo_hi, sum_hi_lo_lo}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_hi_lo = {_sum_T_29, _sum_T_28}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi_hi_hi = {_sum_T_31, _sum_T_30}; // @[Atomics.scala:24:29]
wire [31:0] sum_hi_hi = {sum_hi_hi_hi, sum_hi_hi_lo}; // @[Atomics.scala:24:29]
wire [63:0] sum_hi = {sum_hi_hi, sum_hi_lo}; // @[Atomics.scala:24:29]
wire [127:0] _sum_T_32 = {sum_hi, sum_lo}; // @[Atomics.scala:24:29]
wire [127:0] _sum_T_33 = _sum_T_32 & io_a_data_0; // @[Atomics.scala:8:7, :24:{29,44}]
wire [128:0] _sum_T_34 = {1'h0, _sum_T_33} + {1'h0, inv_d}; // @[Atomics.scala:8:7, :10:14, :23:18, :24:{44,57}]
wire [127:0] sum = _sum_T_34[127:0]; // @[Atomics.scala:24:57]
wire _sign_a_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_32 = io_a_data_0[32]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_33 = io_a_data_0[33]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_34 = io_a_data_0[34]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_35 = io_a_data_0[35]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_36 = io_a_data_0[36]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_37 = io_a_data_0[37]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_38 = io_a_data_0[38]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_39 = io_a_data_0[39]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_40 = io_a_data_0[40]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_41 = io_a_data_0[41]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_42 = io_a_data_0[42]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_43 = io_a_data_0[43]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_44 = io_a_data_0[44]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_45 = io_a_data_0[45]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_46 = io_a_data_0[46]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_47 = io_a_data_0[47]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_48 = io_a_data_0[48]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_49 = io_a_data_0[49]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_50 = io_a_data_0[50]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_51 = io_a_data_0[51]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_52 = io_a_data_0[52]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_53 = io_a_data_0[53]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_54 = io_a_data_0[54]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_55 = io_a_data_0[55]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_56 = io_a_data_0[56]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_57 = io_a_data_0[57]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_58 = io_a_data_0[58]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_59 = io_a_data_0[59]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_60 = io_a_data_0[60]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_61 = io_a_data_0[61]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_62 = io_a_data_0[62]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_63 = io_a_data_0[63]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_64 = io_a_data_0[64]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_65 = io_a_data_0[65]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_66 = io_a_data_0[66]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_67 = io_a_data_0[67]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_68 = io_a_data_0[68]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_69 = io_a_data_0[69]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_70 = io_a_data_0[70]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_71 = io_a_data_0[71]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_72 = io_a_data_0[72]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_73 = io_a_data_0[73]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_74 = io_a_data_0[74]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_75 = io_a_data_0[75]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_76 = io_a_data_0[76]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_77 = io_a_data_0[77]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_78 = io_a_data_0[78]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_79 = io_a_data_0[79]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_80 = io_a_data_0[80]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_81 = io_a_data_0[81]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_82 = io_a_data_0[82]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_83 = io_a_data_0[83]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_84 = io_a_data_0[84]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_85 = io_a_data_0[85]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_86 = io_a_data_0[86]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_87 = io_a_data_0[87]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_88 = io_a_data_0[88]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_89 = io_a_data_0[89]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_90 = io_a_data_0[90]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_91 = io_a_data_0[91]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_92 = io_a_data_0[92]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_93 = io_a_data_0[93]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_94 = io_a_data_0[94]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_95 = io_a_data_0[95]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_96 = io_a_data_0[96]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_97 = io_a_data_0[97]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_98 = io_a_data_0[98]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_99 = io_a_data_0[99]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_100 = io_a_data_0[100]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_101 = io_a_data_0[101]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_102 = io_a_data_0[102]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_103 = io_a_data_0[103]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_104 = io_a_data_0[104]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_105 = io_a_data_0[105]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_106 = io_a_data_0[106]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_107 = io_a_data_0[107]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_108 = io_a_data_0[108]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_109 = io_a_data_0[109]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_110 = io_a_data_0[110]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_111 = io_a_data_0[111]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_112 = io_a_data_0[112]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_113 = io_a_data_0[113]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_114 = io_a_data_0[114]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_115 = io_a_data_0[115]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_116 = io_a_data_0[116]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_117 = io_a_data_0[117]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_118 = io_a_data_0[118]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_119 = io_a_data_0[119]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_120 = io_a_data_0[120]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_121 = io_a_data_0[121]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_122 = io_a_data_0[122]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_123 = io_a_data_0[123]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_124 = io_a_data_0[124]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_125 = io_a_data_0[125]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_126 = io_a_data_0[126]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_127 = io_a_data_0[127]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire [1:0] sign_a_lo_lo_lo = {_sign_a_T_15, _sign_a_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_lo_lo_hi = {_sign_a_T_31, _sign_a_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_lo_lo = {sign_a_lo_lo_hi, sign_a_lo_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_a_lo_hi_lo = {_sign_a_T_47, _sign_a_T_39}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_lo_hi_hi = {_sign_a_T_63, _sign_a_T_55}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_lo_hi = {sign_a_lo_hi_hi, sign_a_lo_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_a_lo = {sign_a_lo_hi, sign_a_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_a_hi_lo_lo = {_sign_a_T_79, _sign_a_T_71}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_hi_lo_hi = {_sign_a_T_95, _sign_a_T_87}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_hi_lo = {sign_a_hi_lo_hi, sign_a_hi_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_a_hi_hi_lo = {_sign_a_T_111, _sign_a_T_103}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_hi_hi_hi = {_sign_a_T_127, _sign_a_T_119}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_a_hi_hi = {sign_a_hi_hi_hi, sign_a_hi_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_a_hi = {sign_a_hi_hi, sign_a_hi_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_a_T_128 = {sign_a_hi, sign_a_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_a_T_129 = _sign_a_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_a = |_sign_a_T_129; // @[Atomics.scala:25:{83,94}]
wire _sign_d_T = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_128 = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_1 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_129 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_2 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_130 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_3 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_131 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_4 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_132 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_5 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_133 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_6 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_134 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_7 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_135 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_8 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_136 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_9 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_137 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_10 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_138 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_11 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_139 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_12 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_140 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_13 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_141 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_14 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_142 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_15 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_143 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_16 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_144 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_17 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_145 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_18 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_146 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_19 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_147 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_20 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_148 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_21 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_149 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_22 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_150 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_23 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_151 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_24 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_152 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_25 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_153 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_26 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_154 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_27 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_155 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_28 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_156 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_29 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_157 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_30 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_158 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_31 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_159 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_32 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_160 = io_data_in_0[32]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_33 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_161 = io_data_in_0[33]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_34 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_162 = io_data_in_0[34]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_35 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_163 = io_data_in_0[35]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_36 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_164 = io_data_in_0[36]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_37 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_165 = io_data_in_0[37]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_38 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_166 = io_data_in_0[38]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_39 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_167 = io_data_in_0[39]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_40 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_168 = io_data_in_0[40]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_41 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_169 = io_data_in_0[41]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_42 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_170 = io_data_in_0[42]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_43 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_171 = io_data_in_0[43]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_44 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_172 = io_data_in_0[44]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_45 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_173 = io_data_in_0[45]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_46 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_174 = io_data_in_0[46]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_47 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_175 = io_data_in_0[47]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_48 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_176 = io_data_in_0[48]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_49 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_177 = io_data_in_0[49]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_50 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_178 = io_data_in_0[50]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_51 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_179 = io_data_in_0[51]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_52 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_180 = io_data_in_0[52]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_53 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_181 = io_data_in_0[53]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_54 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_182 = io_data_in_0[54]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_55 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_183 = io_data_in_0[55]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_56 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_184 = io_data_in_0[56]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_57 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_185 = io_data_in_0[57]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_58 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_186 = io_data_in_0[58]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_59 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_187 = io_data_in_0[59]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_60 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_188 = io_data_in_0[60]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_61 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_189 = io_data_in_0[61]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_62 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_190 = io_data_in_0[62]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_63 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_191 = io_data_in_0[63]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_64 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_192 = io_data_in_0[64]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_65 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_193 = io_data_in_0[65]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_66 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_194 = io_data_in_0[66]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_67 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_195 = io_data_in_0[67]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_68 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_196 = io_data_in_0[68]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_69 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_197 = io_data_in_0[69]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_70 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_198 = io_data_in_0[70]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_71 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_199 = io_data_in_0[71]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_72 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_200 = io_data_in_0[72]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_73 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_201 = io_data_in_0[73]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_74 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_202 = io_data_in_0[74]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_75 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_203 = io_data_in_0[75]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_76 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_204 = io_data_in_0[76]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_77 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_205 = io_data_in_0[77]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_78 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_206 = io_data_in_0[78]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_79 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_207 = io_data_in_0[79]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_80 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_208 = io_data_in_0[80]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_81 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_209 = io_data_in_0[81]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_82 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_210 = io_data_in_0[82]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_83 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_211 = io_data_in_0[83]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_84 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_212 = io_data_in_0[84]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_85 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_213 = io_data_in_0[85]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_86 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_214 = io_data_in_0[86]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_87 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_215 = io_data_in_0[87]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_88 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_216 = io_data_in_0[88]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_89 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_217 = io_data_in_0[89]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_90 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_218 = io_data_in_0[90]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_91 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_219 = io_data_in_0[91]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_92 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_220 = io_data_in_0[92]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_93 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_221 = io_data_in_0[93]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_94 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_222 = io_data_in_0[94]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_95 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_223 = io_data_in_0[95]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_96 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_224 = io_data_in_0[96]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_97 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_225 = io_data_in_0[97]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_98 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_226 = io_data_in_0[98]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_99 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_227 = io_data_in_0[99]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_100 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_228 = io_data_in_0[100]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_101 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_229 = io_data_in_0[101]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_102 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_230 = io_data_in_0[102]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_103 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_231 = io_data_in_0[103]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_104 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_232 = io_data_in_0[104]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_105 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_233 = io_data_in_0[105]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_106 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_234 = io_data_in_0[106]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_107 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_235 = io_data_in_0[107]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_108 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_236 = io_data_in_0[108]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_109 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_237 = io_data_in_0[109]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_110 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_238 = io_data_in_0[110]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_111 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_239 = io_data_in_0[111]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_112 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_240 = io_data_in_0[112]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_113 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_241 = io_data_in_0[113]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_114 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_242 = io_data_in_0[114]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_115 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_243 = io_data_in_0[115]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_116 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_244 = io_data_in_0[116]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_117 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_245 = io_data_in_0[117]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_118 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_246 = io_data_in_0[118]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_119 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_247 = io_data_in_0[119]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_120 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_248 = io_data_in_0[120]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_121 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_249 = io_data_in_0[121]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_122 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_250 = io_data_in_0[122]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_123 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_251 = io_data_in_0[123]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_124 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_252 = io_data_in_0[124]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_125 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_253 = io_data_in_0[125]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_126 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_254 = io_data_in_0[126]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_127 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_255 = io_data_in_0[127]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire [1:0] sign_d_lo_lo_lo = {_sign_d_T_15, _sign_d_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_lo_lo_hi = {_sign_d_T_31, _sign_d_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_lo_lo = {sign_d_lo_lo_hi, sign_d_lo_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_d_lo_hi_lo = {_sign_d_T_47, _sign_d_T_39}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_lo_hi_hi = {_sign_d_T_63, _sign_d_T_55}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_lo_hi = {sign_d_lo_hi_hi, sign_d_lo_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_d_lo = {sign_d_lo_hi, sign_d_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_d_hi_lo_lo = {_sign_d_T_79, _sign_d_T_71}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_hi_lo_hi = {_sign_d_T_95, _sign_d_T_87}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_hi_lo = {sign_d_hi_lo_hi, sign_d_hi_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_d_hi_hi_lo = {_sign_d_T_111, _sign_d_T_103}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_hi_hi_hi = {_sign_d_T_127, _sign_d_T_119}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_d_hi_hi = {sign_d_hi_hi_hi, sign_d_hi_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_d_hi = {sign_d_hi_hi, sign_d_hi_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_d_T_128 = {sign_d_hi, sign_d_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_d_T_129 = _sign_d_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_d = |_sign_d_T_129; // @[Atomics.scala:25:{83,94}]
wire _sign_s_T = sum[0]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_1 = sum[1]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_2 = sum[2]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_3 = sum[3]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_4 = sum[4]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_5 = sum[5]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_6 = sum[6]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_7 = sum[7]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_8 = sum[8]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_9 = sum[9]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_10 = sum[10]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_11 = sum[11]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_12 = sum[12]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_13 = sum[13]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_14 = sum[14]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_15 = sum[15]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_16 = sum[16]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_17 = sum[17]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_18 = sum[18]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_19 = sum[19]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_20 = sum[20]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_21 = sum[21]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_22 = sum[22]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_23 = sum[23]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_24 = sum[24]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_25 = sum[25]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_26 = sum[26]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_27 = sum[27]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_28 = sum[28]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_29 = sum[29]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_30 = sum[30]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_31 = sum[31]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_32 = sum[32]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_33 = sum[33]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_34 = sum[34]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_35 = sum[35]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_36 = sum[36]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_37 = sum[37]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_38 = sum[38]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_39 = sum[39]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_40 = sum[40]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_41 = sum[41]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_42 = sum[42]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_43 = sum[43]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_44 = sum[44]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_45 = sum[45]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_46 = sum[46]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_47 = sum[47]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_48 = sum[48]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_49 = sum[49]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_50 = sum[50]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_51 = sum[51]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_52 = sum[52]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_53 = sum[53]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_54 = sum[54]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_55 = sum[55]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_56 = sum[56]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_57 = sum[57]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_58 = sum[58]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_59 = sum[59]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_60 = sum[60]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_61 = sum[61]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_62 = sum[62]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_63 = sum[63]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_64 = sum[64]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_65 = sum[65]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_66 = sum[66]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_67 = sum[67]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_68 = sum[68]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_69 = sum[69]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_70 = sum[70]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_71 = sum[71]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_72 = sum[72]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_73 = sum[73]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_74 = sum[74]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_75 = sum[75]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_76 = sum[76]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_77 = sum[77]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_78 = sum[78]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_79 = sum[79]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_80 = sum[80]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_81 = sum[81]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_82 = sum[82]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_83 = sum[83]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_84 = sum[84]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_85 = sum[85]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_86 = sum[86]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_87 = sum[87]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_88 = sum[88]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_89 = sum[89]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_90 = sum[90]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_91 = sum[91]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_92 = sum[92]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_93 = sum[93]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_94 = sum[94]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_95 = sum[95]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_96 = sum[96]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_97 = sum[97]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_98 = sum[98]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_99 = sum[99]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_100 = sum[100]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_101 = sum[101]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_102 = sum[102]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_103 = sum[103]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_104 = sum[104]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_105 = sum[105]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_106 = sum[106]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_107 = sum[107]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_108 = sum[108]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_109 = sum[109]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_110 = sum[110]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_111 = sum[111]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_112 = sum[112]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_113 = sum[113]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_114 = sum[114]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_115 = sum[115]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_116 = sum[116]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_117 = sum[117]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_118 = sum[118]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_119 = sum[119]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_120 = sum[120]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_121 = sum[121]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_122 = sum[122]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_123 = sum[123]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_124 = sum[124]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_125 = sum[125]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_126 = sum[126]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_127 = sum[127]; // @[Atomics.scala:24:57, :25:36]
wire [1:0] sign_s_lo_lo_lo = {_sign_s_T_15, _sign_s_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_lo_lo_hi = {_sign_s_T_31, _sign_s_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_lo_lo = {sign_s_lo_lo_hi, sign_s_lo_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_s_lo_hi_lo = {_sign_s_T_47, _sign_s_T_39}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_lo_hi_hi = {_sign_s_T_63, _sign_s_T_55}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_lo_hi = {sign_s_lo_hi_hi, sign_s_lo_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_s_lo = {sign_s_lo_hi, sign_s_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_s_hi_lo_lo = {_sign_s_T_79, _sign_s_T_71}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_hi_lo_hi = {_sign_s_T_95, _sign_s_T_87}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_hi_lo = {sign_s_hi_lo_hi, sign_s_hi_lo_lo}; // @[Atomics.scala:25:33]
wire [1:0] sign_s_hi_hi_lo = {_sign_s_T_111, _sign_s_T_103}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_hi_hi_hi = {_sign_s_T_127, _sign_s_T_119}; // @[Atomics.scala:25:{33,36}]
wire [3:0] sign_s_hi_hi = {sign_s_hi_hi_hi, sign_s_hi_hi_lo}; // @[Atomics.scala:25:33]
wire [7:0] sign_s_hi = {sign_s_hi_hi, sign_s_hi_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_s_T_128 = {sign_s_hi, sign_s_lo}; // @[Atomics.scala:25:33]
wire [15:0] _sign_s_T_129 = _sign_s_T_128 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_s = |_sign_s_T_129; // @[Atomics.scala:25:{83,94}]
wire a_bigger_uneq = unsigned_0 == sign_a; // @[Atomics.scala:19:28, :25:94, :29:32]
wire _a_bigger_T = sign_a == sign_d; // @[Atomics.scala:25:94, :30:29]
wire _a_bigger_T_1 = ~sign_s; // @[Atomics.scala:25:94, :30:41]
wire a_bigger = _a_bigger_T ? _a_bigger_T_1 : a_bigger_uneq; // @[Atomics.scala:29:32, :30:{21,29,41}]
wire pick_a = take_max == a_bigger; // @[Atomics.scala:20:28, :30:21, :31:25]
wire _select_T = pick_a; // @[Atomics.scala:31:25, :48:24]
wire [1:0] _lut_T = io_a_param_0[1:0]; // @[Atomics.scala:8:7, :39:15]
wire [1:0] _logical_T_256 = {_logical_T, _logical_T_128}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_257 = _GEN[_lut_T] >> _logical_T_256; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_258 = _logical_T_257[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_259 = {_logical_T_1, _logical_T_129}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_260 = _GEN[_lut_T] >> _logical_T_259; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_261 = _logical_T_260[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_262 = {_logical_T_2, _logical_T_130}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_263 = _GEN[_lut_T] >> _logical_T_262; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_264 = _logical_T_263[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_265 = {_logical_T_3, _logical_T_131}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_266 = _GEN[_lut_T] >> _logical_T_265; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_267 = _logical_T_266[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_268 = {_logical_T_4, _logical_T_132}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_269 = _GEN[_lut_T] >> _logical_T_268; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_270 = _logical_T_269[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_271 = {_logical_T_5, _logical_T_133}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_272 = _GEN[_lut_T] >> _logical_T_271; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_273 = _logical_T_272[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_274 = {_logical_T_6, _logical_T_134}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_275 = _GEN[_lut_T] >> _logical_T_274; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_276 = _logical_T_275[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_277 = {_logical_T_7, _logical_T_135}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_278 = _GEN[_lut_T] >> _logical_T_277; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_279 = _logical_T_278[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_280 = {_logical_T_8, _logical_T_136}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_281 = _GEN[_lut_T] >> _logical_T_280; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_282 = _logical_T_281[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_283 = {_logical_T_9, _logical_T_137}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_284 = _GEN[_lut_T] >> _logical_T_283; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_285 = _logical_T_284[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_286 = {_logical_T_10, _logical_T_138}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_287 = _GEN[_lut_T] >> _logical_T_286; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_288 = _logical_T_287[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_289 = {_logical_T_11, _logical_T_139}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_290 = _GEN[_lut_T] >> _logical_T_289; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_291 = _logical_T_290[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_292 = {_logical_T_12, _logical_T_140}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_293 = _GEN[_lut_T] >> _logical_T_292; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_294 = _logical_T_293[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_295 = {_logical_T_13, _logical_T_141}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_296 = _GEN[_lut_T] >> _logical_T_295; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_297 = _logical_T_296[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_298 = {_logical_T_14, _logical_T_142}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_299 = _GEN[_lut_T] >> _logical_T_298; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_300 = _logical_T_299[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_301 = {_logical_T_15, _logical_T_143}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_302 = _GEN[_lut_T] >> _logical_T_301; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_303 = _logical_T_302[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_304 = {_logical_T_16, _logical_T_144}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_305 = _GEN[_lut_T] >> _logical_T_304; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_306 = _logical_T_305[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_307 = {_logical_T_17, _logical_T_145}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_308 = _GEN[_lut_T] >> _logical_T_307; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_309 = _logical_T_308[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_310 = {_logical_T_18, _logical_T_146}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_311 = _GEN[_lut_T] >> _logical_T_310; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_312 = _logical_T_311[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_313 = {_logical_T_19, _logical_T_147}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_314 = _GEN[_lut_T] >> _logical_T_313; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_315 = _logical_T_314[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_316 = {_logical_T_20, _logical_T_148}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_317 = _GEN[_lut_T] >> _logical_T_316; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_318 = _logical_T_317[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_319 = {_logical_T_21, _logical_T_149}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_320 = _GEN[_lut_T] >> _logical_T_319; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_321 = _logical_T_320[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_322 = {_logical_T_22, _logical_T_150}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_323 = _GEN[_lut_T] >> _logical_T_322; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_324 = _logical_T_323[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_325 = {_logical_T_23, _logical_T_151}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_326 = _GEN[_lut_T] >> _logical_T_325; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_327 = _logical_T_326[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_328 = {_logical_T_24, _logical_T_152}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_329 = _GEN[_lut_T] >> _logical_T_328; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_330 = _logical_T_329[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_331 = {_logical_T_25, _logical_T_153}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_332 = _GEN[_lut_T] >> _logical_T_331; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_333 = _logical_T_332[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_334 = {_logical_T_26, _logical_T_154}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_335 = _GEN[_lut_T] >> _logical_T_334; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_336 = _logical_T_335[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_337 = {_logical_T_27, _logical_T_155}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_338 = _GEN[_lut_T] >> _logical_T_337; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_339 = _logical_T_338[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_340 = {_logical_T_28, _logical_T_156}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_341 = _GEN[_lut_T] >> _logical_T_340; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_342 = _logical_T_341[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_343 = {_logical_T_29, _logical_T_157}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_344 = _GEN[_lut_T] >> _logical_T_343; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_345 = _logical_T_344[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_346 = {_logical_T_30, _logical_T_158}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_347 = _GEN[_lut_T] >> _logical_T_346; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_348 = _logical_T_347[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_349 = {_logical_T_31, _logical_T_159}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_350 = _GEN[_lut_T] >> _logical_T_349; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_351 = _logical_T_350[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_352 = {_logical_T_32, _logical_T_160}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_353 = _GEN[_lut_T] >> _logical_T_352; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_354 = _logical_T_353[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_355 = {_logical_T_33, _logical_T_161}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_356 = _GEN[_lut_T] >> _logical_T_355; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_357 = _logical_T_356[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_358 = {_logical_T_34, _logical_T_162}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_359 = _GEN[_lut_T] >> _logical_T_358; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_360 = _logical_T_359[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_361 = {_logical_T_35, _logical_T_163}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_362 = _GEN[_lut_T] >> _logical_T_361; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_363 = _logical_T_362[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_364 = {_logical_T_36, _logical_T_164}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_365 = _GEN[_lut_T] >> _logical_T_364; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_366 = _logical_T_365[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_367 = {_logical_T_37, _logical_T_165}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_368 = _GEN[_lut_T] >> _logical_T_367; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_369 = _logical_T_368[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_370 = {_logical_T_38, _logical_T_166}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_371 = _GEN[_lut_T] >> _logical_T_370; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_372 = _logical_T_371[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_373 = {_logical_T_39, _logical_T_167}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_374 = _GEN[_lut_T] >> _logical_T_373; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_375 = _logical_T_374[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_376 = {_logical_T_40, _logical_T_168}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_377 = _GEN[_lut_T] >> _logical_T_376; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_378 = _logical_T_377[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_379 = {_logical_T_41, _logical_T_169}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_380 = _GEN[_lut_T] >> _logical_T_379; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_381 = _logical_T_380[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_382 = {_logical_T_42, _logical_T_170}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_383 = _GEN[_lut_T] >> _logical_T_382; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_384 = _logical_T_383[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_385 = {_logical_T_43, _logical_T_171}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_386 = _GEN[_lut_T] >> _logical_T_385; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_387 = _logical_T_386[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_388 = {_logical_T_44, _logical_T_172}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_389 = _GEN[_lut_T] >> _logical_T_388; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_390 = _logical_T_389[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_391 = {_logical_T_45, _logical_T_173}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_392 = _GEN[_lut_T] >> _logical_T_391; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_393 = _logical_T_392[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_394 = {_logical_T_46, _logical_T_174}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_395 = _GEN[_lut_T] >> _logical_T_394; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_396 = _logical_T_395[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_397 = {_logical_T_47, _logical_T_175}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_398 = _GEN[_lut_T] >> _logical_T_397; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_399 = _logical_T_398[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_400 = {_logical_T_48, _logical_T_176}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_401 = _GEN[_lut_T] >> _logical_T_400; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_402 = _logical_T_401[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_403 = {_logical_T_49, _logical_T_177}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_404 = _GEN[_lut_T] >> _logical_T_403; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_405 = _logical_T_404[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_406 = {_logical_T_50, _logical_T_178}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_407 = _GEN[_lut_T] >> _logical_T_406; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_408 = _logical_T_407[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_409 = {_logical_T_51, _logical_T_179}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_410 = _GEN[_lut_T] >> _logical_T_409; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_411 = _logical_T_410[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_412 = {_logical_T_52, _logical_T_180}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_413 = _GEN[_lut_T] >> _logical_T_412; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_414 = _logical_T_413[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_415 = {_logical_T_53, _logical_T_181}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_416 = _GEN[_lut_T] >> _logical_T_415; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_417 = _logical_T_416[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_418 = {_logical_T_54, _logical_T_182}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_419 = _GEN[_lut_T] >> _logical_T_418; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_420 = _logical_T_419[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_421 = {_logical_T_55, _logical_T_183}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_422 = _GEN[_lut_T] >> _logical_T_421; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_423 = _logical_T_422[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_424 = {_logical_T_56, _logical_T_184}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_425 = _GEN[_lut_T] >> _logical_T_424; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_426 = _logical_T_425[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_427 = {_logical_T_57, _logical_T_185}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_428 = _GEN[_lut_T] >> _logical_T_427; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_429 = _logical_T_428[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_430 = {_logical_T_58, _logical_T_186}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_431 = _GEN[_lut_T] >> _logical_T_430; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_432 = _logical_T_431[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_433 = {_logical_T_59, _logical_T_187}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_434 = _GEN[_lut_T] >> _logical_T_433; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_435 = _logical_T_434[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_436 = {_logical_T_60, _logical_T_188}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_437 = _GEN[_lut_T] >> _logical_T_436; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_438 = _logical_T_437[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_439 = {_logical_T_61, _logical_T_189}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_440 = _GEN[_lut_T] >> _logical_T_439; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_441 = _logical_T_440[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_442 = {_logical_T_62, _logical_T_190}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_443 = _GEN[_lut_T] >> _logical_T_442; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_444 = _logical_T_443[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_445 = {_logical_T_63, _logical_T_191}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_446 = _GEN[_lut_T] >> _logical_T_445; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_447 = _logical_T_446[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_448 = {_logical_T_64, _logical_T_192}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_449 = _GEN[_lut_T] >> _logical_T_448; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_450 = _logical_T_449[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_451 = {_logical_T_65, _logical_T_193}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_452 = _GEN[_lut_T] >> _logical_T_451; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_453 = _logical_T_452[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_454 = {_logical_T_66, _logical_T_194}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_455 = _GEN[_lut_T] >> _logical_T_454; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_456 = _logical_T_455[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_457 = {_logical_T_67, _logical_T_195}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_458 = _GEN[_lut_T] >> _logical_T_457; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_459 = _logical_T_458[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_460 = {_logical_T_68, _logical_T_196}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_461 = _GEN[_lut_T] >> _logical_T_460; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_462 = _logical_T_461[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_463 = {_logical_T_69, _logical_T_197}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_464 = _GEN[_lut_T] >> _logical_T_463; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_465 = _logical_T_464[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_466 = {_logical_T_70, _logical_T_198}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_467 = _GEN[_lut_T] >> _logical_T_466; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_468 = _logical_T_467[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_469 = {_logical_T_71, _logical_T_199}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_470 = _GEN[_lut_T] >> _logical_T_469; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_471 = _logical_T_470[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_472 = {_logical_T_72, _logical_T_200}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_473 = _GEN[_lut_T] >> _logical_T_472; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_474 = _logical_T_473[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_475 = {_logical_T_73, _logical_T_201}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_476 = _GEN[_lut_T] >> _logical_T_475; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_477 = _logical_T_476[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_478 = {_logical_T_74, _logical_T_202}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_479 = _GEN[_lut_T] >> _logical_T_478; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_480 = _logical_T_479[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_481 = {_logical_T_75, _logical_T_203}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_482 = _GEN[_lut_T] >> _logical_T_481; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_483 = _logical_T_482[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_484 = {_logical_T_76, _logical_T_204}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_485 = _GEN[_lut_T] >> _logical_T_484; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_486 = _logical_T_485[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_487 = {_logical_T_77, _logical_T_205}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_488 = _GEN[_lut_T] >> _logical_T_487; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_489 = _logical_T_488[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_490 = {_logical_T_78, _logical_T_206}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_491 = _GEN[_lut_T] >> _logical_T_490; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_492 = _logical_T_491[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_493 = {_logical_T_79, _logical_T_207}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_494 = _GEN[_lut_T] >> _logical_T_493; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_495 = _logical_T_494[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_496 = {_logical_T_80, _logical_T_208}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_497 = _GEN[_lut_T] >> _logical_T_496; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_498 = _logical_T_497[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_499 = {_logical_T_81, _logical_T_209}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_500 = _GEN[_lut_T] >> _logical_T_499; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_501 = _logical_T_500[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_502 = {_logical_T_82, _logical_T_210}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_503 = _GEN[_lut_T] >> _logical_T_502; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_504 = _logical_T_503[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_505 = {_logical_T_83, _logical_T_211}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_506 = _GEN[_lut_T] >> _logical_T_505; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_507 = _logical_T_506[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_508 = {_logical_T_84, _logical_T_212}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_509 = _GEN[_lut_T] >> _logical_T_508; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_510 = _logical_T_509[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_511 = {_logical_T_85, _logical_T_213}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_512 = _GEN[_lut_T] >> _logical_T_511; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_513 = _logical_T_512[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_514 = {_logical_T_86, _logical_T_214}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_515 = _GEN[_lut_T] >> _logical_T_514; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_516 = _logical_T_515[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_517 = {_logical_T_87, _logical_T_215}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_518 = _GEN[_lut_T] >> _logical_T_517; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_519 = _logical_T_518[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_520 = {_logical_T_88, _logical_T_216}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_521 = _GEN[_lut_T] >> _logical_T_520; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_522 = _logical_T_521[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_523 = {_logical_T_89, _logical_T_217}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_524 = _GEN[_lut_T] >> _logical_T_523; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_525 = _logical_T_524[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_526 = {_logical_T_90, _logical_T_218}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_527 = _GEN[_lut_T] >> _logical_T_526; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_528 = _logical_T_527[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_529 = {_logical_T_91, _logical_T_219}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_530 = _GEN[_lut_T] >> _logical_T_529; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_531 = _logical_T_530[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_532 = {_logical_T_92, _logical_T_220}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_533 = _GEN[_lut_T] >> _logical_T_532; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_534 = _logical_T_533[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_535 = {_logical_T_93, _logical_T_221}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_536 = _GEN[_lut_T] >> _logical_T_535; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_537 = _logical_T_536[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_538 = {_logical_T_94, _logical_T_222}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_539 = _GEN[_lut_T] >> _logical_T_538; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_540 = _logical_T_539[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_541 = {_logical_T_95, _logical_T_223}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_542 = _GEN[_lut_T] >> _logical_T_541; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_543 = _logical_T_542[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_544 = {_logical_T_96, _logical_T_224}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_545 = _GEN[_lut_T] >> _logical_T_544; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_546 = _logical_T_545[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_547 = {_logical_T_97, _logical_T_225}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_548 = _GEN[_lut_T] >> _logical_T_547; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_549 = _logical_T_548[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_550 = {_logical_T_98, _logical_T_226}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_551 = _GEN[_lut_T] >> _logical_T_550; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_552 = _logical_T_551[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_553 = {_logical_T_99, _logical_T_227}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_554 = _GEN[_lut_T] >> _logical_T_553; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_555 = _logical_T_554[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_556 = {_logical_T_100, _logical_T_228}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_557 = _GEN[_lut_T] >> _logical_T_556; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_558 = _logical_T_557[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_559 = {_logical_T_101, _logical_T_229}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_560 = _GEN[_lut_T] >> _logical_T_559; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_561 = _logical_T_560[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_562 = {_logical_T_102, _logical_T_230}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_563 = _GEN[_lut_T] >> _logical_T_562; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_564 = _logical_T_563[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_565 = {_logical_T_103, _logical_T_231}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_566 = _GEN[_lut_T] >> _logical_T_565; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_567 = _logical_T_566[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_568 = {_logical_T_104, _logical_T_232}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_569 = _GEN[_lut_T] >> _logical_T_568; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_570 = _logical_T_569[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_571 = {_logical_T_105, _logical_T_233}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_572 = _GEN[_lut_T] >> _logical_T_571; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_573 = _logical_T_572[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_574 = {_logical_T_106, _logical_T_234}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_575 = _GEN[_lut_T] >> _logical_T_574; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_576 = _logical_T_575[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_577 = {_logical_T_107, _logical_T_235}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_578 = _GEN[_lut_T] >> _logical_T_577; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_579 = _logical_T_578[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_580 = {_logical_T_108, _logical_T_236}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_581 = _GEN[_lut_T] >> _logical_T_580; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_582 = _logical_T_581[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_583 = {_logical_T_109, _logical_T_237}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_584 = _GEN[_lut_T] >> _logical_T_583; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_585 = _logical_T_584[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_586 = {_logical_T_110, _logical_T_238}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_587 = _GEN[_lut_T] >> _logical_T_586; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_588 = _logical_T_587[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_589 = {_logical_T_111, _logical_T_239}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_590 = _GEN[_lut_T] >> _logical_T_589; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_591 = _logical_T_590[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_592 = {_logical_T_112, _logical_T_240}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_593 = _GEN[_lut_T] >> _logical_T_592; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_594 = _logical_T_593[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_595 = {_logical_T_113, _logical_T_241}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_596 = _GEN[_lut_T] >> _logical_T_595; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_597 = _logical_T_596[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_598 = {_logical_T_114, _logical_T_242}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_599 = _GEN[_lut_T] >> _logical_T_598; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_600 = _logical_T_599[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_601 = {_logical_T_115, _logical_T_243}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_602 = _GEN[_lut_T] >> _logical_T_601; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_603 = _logical_T_602[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_604 = {_logical_T_116, _logical_T_244}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_605 = _GEN[_lut_T] >> _logical_T_604; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_606 = _logical_T_605[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_607 = {_logical_T_117, _logical_T_245}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_608 = _GEN[_lut_T] >> _logical_T_607; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_609 = _logical_T_608[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_610 = {_logical_T_118, _logical_T_246}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_611 = _GEN[_lut_T] >> _logical_T_610; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_612 = _logical_T_611[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_613 = {_logical_T_119, _logical_T_247}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_614 = _GEN[_lut_T] >> _logical_T_613; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_615 = _logical_T_614[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_616 = {_logical_T_120, _logical_T_248}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_617 = _GEN[_lut_T] >> _logical_T_616; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_618 = _logical_T_617[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_619 = {_logical_T_121, _logical_T_249}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_620 = _GEN[_lut_T] >> _logical_T_619; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_621 = _logical_T_620[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_622 = {_logical_T_122, _logical_T_250}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_623 = _GEN[_lut_T] >> _logical_T_622; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_624 = _logical_T_623[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_625 = {_logical_T_123, _logical_T_251}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_626 = _GEN[_lut_T] >> _logical_T_625; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_627 = _logical_T_626[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_628 = {_logical_T_124, _logical_T_252}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_629 = _GEN[_lut_T] >> _logical_T_628; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_630 = _logical_T_629[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_631 = {_logical_T_125, _logical_T_253}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_632 = _GEN[_lut_T] >> _logical_T_631; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_633 = _logical_T_632[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_634 = {_logical_T_126, _logical_T_254}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_635 = _GEN[_lut_T] >> _logical_T_634; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_636 = _logical_T_635[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_637 = {_logical_T_127, _logical_T_255}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_638 = _GEN[_lut_T] >> _logical_T_637; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_639 = _logical_T_638[0]; // @[Atomics.scala:41:8]
wire [1:0] logical_lo_lo_lo_lo_lo_lo = {_logical_T_261, _logical_T_258}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_lo_lo_hi = {_logical_T_267, _logical_T_264}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_lo_lo = {logical_lo_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_lo_lo_hi_lo = {_logical_T_273, _logical_T_270}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_lo_hi_hi = {_logical_T_279, _logical_T_276}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_lo_hi = {logical_lo_lo_lo_lo_hi_hi, logical_lo_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_lo_lo = {logical_lo_lo_lo_lo_hi, logical_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_lo_hi_lo_lo = {_logical_T_285, _logical_T_282}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_hi_lo_hi = {_logical_T_291, _logical_T_288}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_hi_lo = {logical_lo_lo_lo_hi_lo_hi, logical_lo_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_lo_hi_hi_lo = {_logical_T_297, _logical_T_294}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_hi_hi_hi = {_logical_T_303, _logical_T_300}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo_hi_hi = {logical_lo_lo_lo_hi_hi_hi, logical_lo_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_lo_hi = {logical_lo_lo_lo_hi_hi, logical_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_lo_lo = {logical_lo_lo_lo_hi, logical_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_lo_lo_lo = {_logical_T_309, _logical_T_306}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_lo_lo_hi = {_logical_T_315, _logical_T_312}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_lo_lo = {logical_lo_lo_hi_lo_lo_hi, logical_lo_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_lo_hi_lo = {_logical_T_321, _logical_T_318}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_lo_hi_hi = {_logical_T_327, _logical_T_324}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_lo_hi = {logical_lo_lo_hi_lo_hi_hi, logical_lo_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_hi_lo = {logical_lo_lo_hi_lo_hi, logical_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_hi_lo_lo = {_logical_T_333, _logical_T_330}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_hi_lo_hi = {_logical_T_339, _logical_T_336}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_hi_lo = {logical_lo_lo_hi_hi_lo_hi, logical_lo_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_hi_hi_lo = {_logical_T_345, _logical_T_342}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_hi_hi_hi = {_logical_T_351, _logical_T_348}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi_hi_hi = {logical_lo_lo_hi_hi_hi_hi, logical_lo_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo_hi_hi = {logical_lo_lo_hi_hi_hi, logical_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_lo_hi = {logical_lo_lo_hi_hi, logical_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_lo_lo = {logical_lo_lo_hi, logical_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_lo_lo_lo = {_logical_T_357, _logical_T_354}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_lo_lo_hi = {_logical_T_363, _logical_T_360}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_lo_lo = {logical_lo_hi_lo_lo_lo_hi, logical_lo_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_lo_hi_lo = {_logical_T_369, _logical_T_366}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_lo_hi_hi = {_logical_T_375, _logical_T_372}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_lo_hi = {logical_lo_hi_lo_lo_hi_hi, logical_lo_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_lo_lo = {logical_lo_hi_lo_lo_hi, logical_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_hi_lo_lo = {_logical_T_381, _logical_T_378}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_hi_lo_hi = {_logical_T_387, _logical_T_384}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_hi_lo = {logical_lo_hi_lo_hi_lo_hi, logical_lo_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_hi_hi_lo = {_logical_T_393, _logical_T_390}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_hi_hi_hi = {_logical_T_399, _logical_T_396}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo_hi_hi = {logical_lo_hi_lo_hi_hi_hi, logical_lo_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_lo_hi = {logical_lo_hi_lo_hi_hi, logical_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_hi_lo = {logical_lo_hi_lo_hi, logical_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_lo_lo_lo = {_logical_T_405, _logical_T_402}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_lo_lo_hi = {_logical_T_411, _logical_T_408}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_lo_lo = {logical_lo_hi_hi_lo_lo_hi, logical_lo_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_lo_hi_lo = {_logical_T_417, _logical_T_414}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_lo_hi_hi = {_logical_T_423, _logical_T_420}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_lo_hi = {logical_lo_hi_hi_lo_hi_hi, logical_lo_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_hi_lo = {logical_lo_hi_hi_lo_hi, logical_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_hi_lo_lo = {_logical_T_429, _logical_T_426}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_hi_lo_hi = {_logical_T_435, _logical_T_432}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_hi_lo = {logical_lo_hi_hi_hi_lo_hi, logical_lo_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_hi_hi_lo = {_logical_T_441, _logical_T_438}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_hi_hi_hi = {_logical_T_447, _logical_T_444}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi_hi_hi = {logical_lo_hi_hi_hi_hi_hi, logical_lo_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi_hi_hi = {logical_lo_hi_hi_hi_hi, logical_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo_hi_hi = {logical_lo_hi_hi_hi, logical_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_lo_hi = {logical_lo_hi_hi, logical_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [63:0] logical_lo = {logical_lo_hi, logical_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_lo_lo_lo = {_logical_T_453, _logical_T_450}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_lo_lo_hi = {_logical_T_459, _logical_T_456}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_lo_lo = {logical_hi_lo_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_lo_hi_lo = {_logical_T_465, _logical_T_462}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_lo_hi_hi = {_logical_T_471, _logical_T_468}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_lo_hi = {logical_hi_lo_lo_lo_hi_hi, logical_hi_lo_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_lo_lo = {logical_hi_lo_lo_lo_hi, logical_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_hi_lo_lo = {_logical_T_477, _logical_T_474}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_hi_lo_hi = {_logical_T_483, _logical_T_480}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_hi_lo = {logical_hi_lo_lo_hi_lo_hi, logical_hi_lo_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_hi_hi_lo = {_logical_T_489, _logical_T_486}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_hi_hi_hi = {_logical_T_495, _logical_T_492}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo_hi_hi = {logical_hi_lo_lo_hi_hi_hi, logical_hi_lo_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_lo_hi = {logical_hi_lo_lo_hi_hi, logical_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_lo_lo = {logical_hi_lo_lo_hi, logical_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_lo_lo_lo = {_logical_T_501, _logical_T_498}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_lo_lo_hi = {_logical_T_507, _logical_T_504}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_lo_lo = {logical_hi_lo_hi_lo_lo_hi, logical_hi_lo_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_lo_hi_lo = {_logical_T_513, _logical_T_510}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_lo_hi_hi = {_logical_T_519, _logical_T_516}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_lo_hi = {logical_hi_lo_hi_lo_hi_hi, logical_hi_lo_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_hi_lo = {logical_hi_lo_hi_lo_hi, logical_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_hi_lo_lo = {_logical_T_525, _logical_T_522}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_hi_lo_hi = {_logical_T_531, _logical_T_528}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_hi_lo = {logical_hi_lo_hi_hi_lo_hi, logical_hi_lo_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_hi_hi_lo = {_logical_T_537, _logical_T_534}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_hi_hi_hi = {_logical_T_543, _logical_T_540}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi_hi_hi = {logical_hi_lo_hi_hi_hi_hi, logical_hi_lo_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo_hi_hi = {logical_hi_lo_hi_hi_hi, logical_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_lo_hi = {logical_hi_lo_hi_hi, logical_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_hi_lo = {logical_hi_lo_hi, logical_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_lo_lo_lo = {_logical_T_549, _logical_T_546}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_lo_lo_hi = {_logical_T_555, _logical_T_552}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_lo_lo = {logical_hi_hi_lo_lo_lo_hi, logical_hi_hi_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_lo_hi_lo = {_logical_T_561, _logical_T_558}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_lo_hi_hi = {_logical_T_567, _logical_T_564}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_lo_hi = {logical_hi_hi_lo_lo_hi_hi, logical_hi_hi_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_lo_lo = {logical_hi_hi_lo_lo_hi, logical_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_hi_lo_lo = {_logical_T_573, _logical_T_570}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_hi_lo_hi = {_logical_T_579, _logical_T_576}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_hi_lo = {logical_hi_hi_lo_hi_lo_hi, logical_hi_hi_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_hi_hi_lo = {_logical_T_585, _logical_T_582}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_hi_hi_hi = {_logical_T_591, _logical_T_588}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo_hi_hi = {logical_hi_hi_lo_hi_hi_hi, logical_hi_hi_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_lo_hi = {logical_hi_hi_lo_hi_hi, logical_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_hi_lo = {logical_hi_hi_lo_hi, logical_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_lo_lo_lo = {_logical_T_597, _logical_T_594}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_lo_lo_hi = {_logical_T_603, _logical_T_600}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_lo_lo = {logical_hi_hi_hi_lo_lo_hi, logical_hi_hi_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_lo_hi_lo = {_logical_T_609, _logical_T_606}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_lo_hi_hi = {_logical_T_615, _logical_T_612}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_lo_hi = {logical_hi_hi_hi_lo_hi_hi, logical_hi_hi_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_hi_lo = {logical_hi_hi_hi_lo_hi, logical_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_hi_lo_lo = {_logical_T_621, _logical_T_618}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_hi_lo_hi = {_logical_T_627, _logical_T_624}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_hi_lo = {logical_hi_hi_hi_hi_lo_hi, logical_hi_hi_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_hi_hi_lo = {_logical_T_633, _logical_T_630}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_hi_hi_hi = {_logical_T_639, _logical_T_636}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi_hi_hi = {logical_hi_hi_hi_hi_hi, logical_hi_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi_hi_hi = {logical_hi_hi_hi_hi, logical_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical_hi_hi = {logical_hi_hi_hi, logical_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [63:0] logical_hi = {logical_hi_hi, logical_hi_lo}; // @[Atomics.scala:40:20]
wire [127:0] logical = {logical_hi, logical_lo}; // @[Atomics.scala:40:20]
wire [1:0] _select_T_1 = adder ? 2'h2 : {1'h0, _select_T}; // @[Atomics.scala:8:7, :10:14, :18:28, :48:{8,24}]
wire [1:0] _select_WIRE_2 = _select_T_1; // @[Atomics.scala:45:42, :48:8]
wire [7:0][1:0] _GEN_0 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {_select_WIRE_2}, {2'h1}, {2'h1}}; // @[Atomics.scala:45:{19,42}]
wire [1:0] select = io_write_0 ? 2'h1 : _GEN_0[io_a_opcode_0]; // @[Atomics.scala:8:7, :45:19]
wire [1:0] selects_0 = _selects_T ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_1 = _selects_T_1 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_2 = _selects_T_2 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_3 = _selects_T_3 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_4 = _selects_T_4 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_5 = _selects_T_5 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_6 = _selects_T_6 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_7 = _selects_T_7 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_8 = _selects_T_8 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_9 = _selects_T_9 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_10 = _selects_T_10 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_11 = _selects_T_11 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_12 = _selects_T_12 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_13 = _selects_T_13 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_14 = _selects_T_14 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_15 = _selects_T_15 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [7:0] _io_data_out_T = io_data_in_0[7:0]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_0 = _io_data_out_T; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_1 = io_a_data_0[7:0]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1 = _io_data_out_T_1; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_2 = sum[7:0]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_2 = _io_data_out_T_2; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_3 = logical[7:0]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_3 = _io_data_out_T_3; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_4 = io_data_in_0[15:8]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1_0 = _io_data_out_T_4; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_5 = io_a_data_0[15:8]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1_1 = _io_data_out_T_5; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_6 = sum[15:8]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_1_2 = _io_data_out_T_6; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_7 = logical[15:8]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_1_3 = _io_data_out_T_7; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_8 = io_data_in_0[23:16]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_2_0 = _io_data_out_T_8; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_9 = io_a_data_0[23:16]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_2_1 = _io_data_out_T_9; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_10 = sum[23:16]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_2_2 = _io_data_out_T_10; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_11 = logical[23:16]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_2_3 = _io_data_out_T_11; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_12 = io_data_in_0[31:24]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_3_0 = _io_data_out_T_12; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_13 = io_a_data_0[31:24]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_3_1 = _io_data_out_T_13; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_14 = sum[31:24]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_3_2 = _io_data_out_T_14; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_15 = logical[31:24]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_3_3 = _io_data_out_T_15; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_16 = io_data_in_0[39:32]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_4_0 = _io_data_out_T_16; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_17 = io_a_data_0[39:32]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_4_1 = _io_data_out_T_17; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_18 = sum[39:32]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_4_2 = _io_data_out_T_18; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_19 = logical[39:32]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_4_3 = _io_data_out_T_19; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_20 = io_data_in_0[47:40]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_5_0 = _io_data_out_T_20; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_21 = io_a_data_0[47:40]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_5_1 = _io_data_out_T_21; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_22 = sum[47:40]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_5_2 = _io_data_out_T_22; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_23 = logical[47:40]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_5_3 = _io_data_out_T_23; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_24 = io_data_in_0[55:48]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_6_0 = _io_data_out_T_24; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_25 = io_a_data_0[55:48]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_6_1 = _io_data_out_T_25; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_26 = sum[55:48]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_6_2 = _io_data_out_T_26; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_27 = logical[55:48]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_6_3 = _io_data_out_T_27; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_28 = io_data_in_0[63:56]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_7_0 = _io_data_out_T_28; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_29 = io_a_data_0[63:56]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_7_1 = _io_data_out_T_29; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_30 = sum[63:56]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_7_2 = _io_data_out_T_30; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_31 = logical[63:56]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_7_3 = _io_data_out_T_31; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_32 = io_data_in_0[71:64]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_8_0 = _io_data_out_T_32; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_33 = io_a_data_0[71:64]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_8_1 = _io_data_out_T_33; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_34 = sum[71:64]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_8_2 = _io_data_out_T_34; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_35 = logical[71:64]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_8_3 = _io_data_out_T_35; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_36 = io_data_in_0[79:72]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_9_0 = _io_data_out_T_36; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_37 = io_a_data_0[79:72]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_9_1 = _io_data_out_T_37; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_38 = sum[79:72]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_9_2 = _io_data_out_T_38; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_39 = logical[79:72]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_9_3 = _io_data_out_T_39; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_40 = io_data_in_0[87:80]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_10_0 = _io_data_out_T_40; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_41 = io_a_data_0[87:80]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_10_1 = _io_data_out_T_41; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_42 = sum[87:80]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_10_2 = _io_data_out_T_42; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_43 = logical[87:80]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_10_3 = _io_data_out_T_43; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_44 = io_data_in_0[95:88]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_11_0 = _io_data_out_T_44; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_45 = io_a_data_0[95:88]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_11_1 = _io_data_out_T_45; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_46 = sum[95:88]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_11_2 = _io_data_out_T_46; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_47 = logical[95:88]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_11_3 = _io_data_out_T_47; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_48 = io_data_in_0[103:96]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_12_0 = _io_data_out_T_48; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_49 = io_a_data_0[103:96]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_12_1 = _io_data_out_T_49; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_50 = sum[103:96]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_12_2 = _io_data_out_T_50; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_51 = logical[103:96]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_12_3 = _io_data_out_T_51; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_52 = io_data_in_0[111:104]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_13_0 = _io_data_out_T_52; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_53 = io_a_data_0[111:104]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_13_1 = _io_data_out_T_53; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_54 = sum[111:104]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_13_2 = _io_data_out_T_54; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_55 = logical[111:104]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_13_3 = _io_data_out_T_55; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_56 = io_data_in_0[119:112]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_14_0 = _io_data_out_T_56; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_57 = io_a_data_0[119:112]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_14_1 = _io_data_out_T_57; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_58 = sum[119:112]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_14_2 = _io_data_out_T_58; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_59 = logical[119:112]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_14_3 = _io_data_out_T_59; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_60 = io_data_in_0[127:120]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_15_0 = _io_data_out_T_60; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_61 = io_a_data_0[127:120]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_15_1 = _io_data_out_T_61; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_62 = sum[127:120]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_15_2 = _io_data_out_T_62; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_63 = logical[127:120]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_15_3 = _io_data_out_T_63; // @[Atomics.scala:59:{12,59}]
wire [3:0][7:0] _GEN_1 = {{_io_data_out_WIRE_1_3}, {_io_data_out_WIRE_1_2}, {_io_data_out_WIRE_1_1}, {_io_data_out_WIRE_1_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_2 = {{_io_data_out_WIRE_3}, {_io_data_out_WIRE_2}, {_io_data_out_WIRE_1}, {_io_data_out_WIRE_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_lo_lo = {_GEN_1[selects_1], _GEN_2[selects_0]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_3 = {{_io_data_out_WIRE_3_3}, {_io_data_out_WIRE_3_2}, {_io_data_out_WIRE_3_1}, {_io_data_out_WIRE_3_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_4 = {{_io_data_out_WIRE_2_3}, {_io_data_out_WIRE_2_2}, {_io_data_out_WIRE_2_1}, {_io_data_out_WIRE_2_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_lo_hi = {_GEN_3[selects_3], _GEN_4[selects_2]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_lo_lo = {io_data_out_lo_lo_hi, io_data_out_lo_lo_lo}; // @[Atomics.scala:58:21]
wire [3:0][7:0] _GEN_5 = {{_io_data_out_WIRE_5_3}, {_io_data_out_WIRE_5_2}, {_io_data_out_WIRE_5_1}, {_io_data_out_WIRE_5_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_6 = {{_io_data_out_WIRE_4_3}, {_io_data_out_WIRE_4_2}, {_io_data_out_WIRE_4_1}, {_io_data_out_WIRE_4_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_hi_lo = {_GEN_5[selects_5], _GEN_6[selects_4]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_7 = {{_io_data_out_WIRE_7_3}, {_io_data_out_WIRE_7_2}, {_io_data_out_WIRE_7_1}, {_io_data_out_WIRE_7_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_8 = {{_io_data_out_WIRE_6_3}, {_io_data_out_WIRE_6_2}, {_io_data_out_WIRE_6_1}, {_io_data_out_WIRE_6_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo_hi_hi = {_GEN_7[selects_7], _GEN_8[selects_6]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_lo_hi = {io_data_out_lo_hi_hi, io_data_out_lo_hi_lo}; // @[Atomics.scala:58:21]
wire [63:0] io_data_out_lo = {io_data_out_lo_hi, io_data_out_lo_lo}; // @[Atomics.scala:58:21]
wire [3:0][7:0] _GEN_9 = {{_io_data_out_WIRE_9_3}, {_io_data_out_WIRE_9_2}, {_io_data_out_WIRE_9_1}, {_io_data_out_WIRE_9_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_10 = {{_io_data_out_WIRE_8_3}, {_io_data_out_WIRE_8_2}, {_io_data_out_WIRE_8_1}, {_io_data_out_WIRE_8_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_lo_lo = {_GEN_9[selects_9], _GEN_10[selects_8]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_11 = {{_io_data_out_WIRE_11_3}, {_io_data_out_WIRE_11_2}, {_io_data_out_WIRE_11_1}, {_io_data_out_WIRE_11_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_12 = {{_io_data_out_WIRE_10_3}, {_io_data_out_WIRE_10_2}, {_io_data_out_WIRE_10_1}, {_io_data_out_WIRE_10_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_lo_hi = {_GEN_11[selects_11], _GEN_12[selects_10]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_hi_lo = {io_data_out_hi_lo_hi, io_data_out_hi_lo_lo}; // @[Atomics.scala:58:21]
wire [3:0][7:0] _GEN_13 = {{_io_data_out_WIRE_13_3}, {_io_data_out_WIRE_13_2}, {_io_data_out_WIRE_13_1}, {_io_data_out_WIRE_13_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_14 = {{_io_data_out_WIRE_12_3}, {_io_data_out_WIRE_12_2}, {_io_data_out_WIRE_12_1}, {_io_data_out_WIRE_12_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_hi_lo = {_GEN_13[selects_13], _GEN_14[selects_12]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_15 = {{_io_data_out_WIRE_15_3}, {_io_data_out_WIRE_15_2}, {_io_data_out_WIRE_15_1}, {_io_data_out_WIRE_15_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_16 = {{_io_data_out_WIRE_14_3}, {_io_data_out_WIRE_14_2}, {_io_data_out_WIRE_14_1}, {_io_data_out_WIRE_14_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi_hi_hi = {_GEN_15[selects_15], _GEN_16[selects_14]}; // @[Atomics.scala:57:47, :58:21]
wire [31:0] io_data_out_hi_hi = {io_data_out_hi_hi_hi, io_data_out_hi_hi_lo}; // @[Atomics.scala:58:21]
wire [63:0] io_data_out_hi = {io_data_out_hi_hi, io_data_out_hi_lo}; // @[Atomics.scala:58:21]
assign _io_data_out_T_64 = {io_data_out_hi, io_data_out_lo}; // @[Atomics.scala:58:21]
assign io_data_out_0 = _io_data_out_T_64; // @[Atomics.scala:8:7, :58:21]
assign io_data_out = io_data_out_0; // @[Atomics.scala:8:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e8_s24_6 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
inst divSqrtRawFN of DivSqrtRawFN_small_e8_s24_6
connect divSqrtRawFN.clock, clock
connect divSqrtRawFN.reset, reset
connect io.inReady, divSqrtRawFN.io.inReady
connect divSqrtRawFN.io.inValid, io.inValid
connect divSqrtRawFN.io.sqrtOp, io.sqrtOp
node divSqrtRawFN_io_a_exp = bits(io.a, 31, 23)
node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 8, 6)
node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 8, 7)
node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 6, 6)
node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T)
connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1
node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 6, 6)
node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1)
connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2
connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero
node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T
node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp)
connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T
node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T)
node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2)
connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3
connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig
connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp
connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign
connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero
connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf
connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN
node divSqrtRawFN_io_b_exp = bits(io.b, 31, 23)
node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 8, 6)
node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 8, 7)
node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 6, 6)
node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T)
connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1
node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 6, 6)
node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1)
connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2
connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero
node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T
node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp)
connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T
node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0))
node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T)
node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2)
connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3
connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig
connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp
connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign
connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero
connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf
connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN
connect divSqrtRawFN.io.roundingMode, io.roundingMode
connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div
connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt
connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut
connect io.invalidExc, divSqrtRawFN.io.invalidExc
connect io.infiniteExc, divSqrtRawFN.io.infiniteExc
connect io.rawOut, divSqrtRawFN.io.rawOut | module DivSqrtRecFMToRaw_small_e8_s24_6( // @[DivSqrtRecFN_small.scala:422:5]
input clock, // @[DivSqrtRecFN_small.scala:422:5]
input reset, // @[DivSqrtRecFN_small.scala:422:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:426:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:426:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16]
input [32:0] io_a, // @[DivSqrtRecFN_small.scala:426:16]
input [32:0] io_b, // @[DivSqrtRecFN_small.scala:426:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16]
output [9:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16]
output [26:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5]
wire [32:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5]
wire [32:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [9:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [26:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
wire [8:0] divSqrtRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] divSqrtRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
DivSqrtRawFN_small_e8_s24_6 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5]
.io_rawOutValid_div (io_rawOutValid_div_0),
.io_rawOutValid_sqrt (io_rawOutValid_sqrt_0),
.io_roundingModeOut (io_roundingModeOut_0),
.io_invalidExc (io_invalidExc_0),
.io_infiniteExc (io_infiniteExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (io_rawOut_sig_0)
); // @[DivSqrtRecFN_small.scala:446:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_82 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_93
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_82( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_93 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_226 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_226( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_195 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_451
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_195( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_451 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain_1 :
output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_rockettile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_rockettile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip element_reset_domain_rockettile_reset_vector_in : UInt<32>, flip element_reset_domain_rockettile_hartid_in : UInt<2>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst element_reset_domain of HierarchicalElementResetDomain_1
inst clockNode of FixedClockBroadcast_1_2
inst buffer of TLBuffer_a32d128s2k4z4c_3
connect buffer.clock, childClock
connect buffer.reset, childReset
inst buffer_1 of TLBuffer_4
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst intsink of IntSyncAsyncCrossingSink_n1x1_1
connect intsink.clock, childClock
connect intsink.reset, childReset
inst intsink_1 of IntSyncSyncCrossingSink_n1x2_1
inst intsink_2 of IntSyncSyncCrossingSink_n1x1_5
inst intsink_3 of IntSyncSyncCrossingSink_n1x1_6
inst intsink_4 of IntSyncSyncCrossingSink_n1x1_7
inst intsource of IntSyncCrossingSource_n1x1_3
connect intsource.clock, childClock
connect intsource.reset, childReset
inst intsink_5 of IntSyncSyncCrossingSink_n1x1_8
inst intsource_1 of IntSyncCrossingSource_n1x1_4
connect intsource_1.clock, childClock
connect intsource_1.reset, childReset
inst intsink_6 of IntSyncSyncCrossingSink_n1x1_9
inst intsource_2 of IntSyncCrossingSource_n1x1_5
connect intsource_2.clock, childClock
connect intsource_2.reset, childReset
wire tapClockNodeOut : { clock : Clock, reset : Reset}
invalidate tapClockNodeOut.reset
invalidate tapClockNodeOut.clock
wire tapClockNodeIn : { clock : Clock, reset : Reset}
invalidate tapClockNodeIn.reset
invalidate tapClockNodeIn.clock
connect tapClockNodeOut, tapClockNodeIn
wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate tlMasterClockXingOut.e.bits.sink
invalidate tlMasterClockXingOut.e.valid
invalidate tlMasterClockXingOut.e.ready
invalidate tlMasterClockXingOut.d.bits.corrupt
invalidate tlMasterClockXingOut.d.bits.data
invalidate tlMasterClockXingOut.d.bits.denied
invalidate tlMasterClockXingOut.d.bits.sink
invalidate tlMasterClockXingOut.d.bits.source
invalidate tlMasterClockXingOut.d.bits.size
invalidate tlMasterClockXingOut.d.bits.param
invalidate tlMasterClockXingOut.d.bits.opcode
invalidate tlMasterClockXingOut.d.valid
invalidate tlMasterClockXingOut.d.ready
invalidate tlMasterClockXingOut.c.bits.corrupt
invalidate tlMasterClockXingOut.c.bits.data
invalidate tlMasterClockXingOut.c.bits.address
invalidate tlMasterClockXingOut.c.bits.source
invalidate tlMasterClockXingOut.c.bits.size
invalidate tlMasterClockXingOut.c.bits.param
invalidate tlMasterClockXingOut.c.bits.opcode
invalidate tlMasterClockXingOut.c.valid
invalidate tlMasterClockXingOut.c.ready
invalidate tlMasterClockXingOut.b.bits.corrupt
invalidate tlMasterClockXingOut.b.bits.data
invalidate tlMasterClockXingOut.b.bits.mask
invalidate tlMasterClockXingOut.b.bits.address
invalidate tlMasterClockXingOut.b.bits.source
invalidate tlMasterClockXingOut.b.bits.size
invalidate tlMasterClockXingOut.b.bits.param
invalidate tlMasterClockXingOut.b.bits.opcode
invalidate tlMasterClockXingOut.b.valid
invalidate tlMasterClockXingOut.b.ready
invalidate tlMasterClockXingOut.a.bits.corrupt
invalidate tlMasterClockXingOut.a.bits.data
invalidate tlMasterClockXingOut.a.bits.mask
invalidate tlMasterClockXingOut.a.bits.address
invalidate tlMasterClockXingOut.a.bits.source
invalidate tlMasterClockXingOut.a.bits.size
invalidate tlMasterClockXingOut.a.bits.param
invalidate tlMasterClockXingOut.a.bits.opcode
invalidate tlMasterClockXingOut.a.valid
invalidate tlMasterClockXingOut.a.ready
wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate tlMasterClockXingIn.e.bits.sink
invalidate tlMasterClockXingIn.e.valid
invalidate tlMasterClockXingIn.e.ready
invalidate tlMasterClockXingIn.d.bits.corrupt
invalidate tlMasterClockXingIn.d.bits.data
invalidate tlMasterClockXingIn.d.bits.denied
invalidate tlMasterClockXingIn.d.bits.sink
invalidate tlMasterClockXingIn.d.bits.source
invalidate tlMasterClockXingIn.d.bits.size
invalidate tlMasterClockXingIn.d.bits.param
invalidate tlMasterClockXingIn.d.bits.opcode
invalidate tlMasterClockXingIn.d.valid
invalidate tlMasterClockXingIn.d.ready
invalidate tlMasterClockXingIn.c.bits.corrupt
invalidate tlMasterClockXingIn.c.bits.data
invalidate tlMasterClockXingIn.c.bits.address
invalidate tlMasterClockXingIn.c.bits.source
invalidate tlMasterClockXingIn.c.bits.size
invalidate tlMasterClockXingIn.c.bits.param
invalidate tlMasterClockXingIn.c.bits.opcode
invalidate tlMasterClockXingIn.c.valid
invalidate tlMasterClockXingIn.c.ready
invalidate tlMasterClockXingIn.b.bits.corrupt
invalidate tlMasterClockXingIn.b.bits.data
invalidate tlMasterClockXingIn.b.bits.mask
invalidate tlMasterClockXingIn.b.bits.address
invalidate tlMasterClockXingIn.b.bits.source
invalidate tlMasterClockXingIn.b.bits.size
invalidate tlMasterClockXingIn.b.bits.param
invalidate tlMasterClockXingIn.b.bits.opcode
invalidate tlMasterClockXingIn.b.valid
invalidate tlMasterClockXingIn.b.ready
invalidate tlMasterClockXingIn.a.bits.corrupt
invalidate tlMasterClockXingIn.a.bits.data
invalidate tlMasterClockXingIn.a.bits.mask
invalidate tlMasterClockXingIn.a.bits.address
invalidate tlMasterClockXingIn.a.bits.source
invalidate tlMasterClockXingIn.a.bits.size
invalidate tlMasterClockXingIn.a.bits.param
invalidate tlMasterClockXingIn.a.bits.opcode
invalidate tlMasterClockXingIn.a.valid
invalidate tlMasterClockXingIn.a.ready
connect tlMasterClockXingOut, tlMasterClockXingIn
wire intInClockXingOut : { sync : UInt<1>[2]}
invalidate intInClockXingOut.sync[0]
invalidate intInClockXingOut.sync[1]
wire intInClockXingIn : { sync : UInt<1>[2]}
invalidate intInClockXingIn.sync[0]
invalidate intInClockXingIn.sync[1]
connect intInClockXingOut, intInClockXingIn
wire intInClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_1.sync[0]
wire intInClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_1.sync[0]
connect intInClockXingOut_1, intInClockXingIn_1
wire intInClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_2.sync[0]
wire intInClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_2.sync[0]
connect intInClockXingOut_2, intInClockXingIn_2
wire intOutClockXingOut : { sync : UInt<1>[1]}
invalidate intOutClockXingOut.sync[0]
wire intOutClockXingIn : { sync : UInt<1>[1]}
invalidate intOutClockXingIn.sync[0]
connect intOutClockXingOut, intOutClockXingIn
wire intOutClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_1.sync[0]
wire intOutClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_1.sync[0]
connect intOutClockXingOut_1, intOutClockXingIn_1
wire intOutClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_2.sync[0]
wire intOutClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_2.sync[0]
connect intOutClockXingOut_2, intOutClockXingIn_2
wire intOutClockXingOut_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_3.sync[0]
wire intOutClockXingIn_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_3.sync[0]
connect intOutClockXingOut_3, intOutClockXingIn_3
wire intOutClockXingOut_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_4.sync[0]
wire intOutClockXingIn_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_4.sync[0]
connect intOutClockXingOut_4, intOutClockXingIn_4
wire intOutClockXingOut_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_5.sync[0]
wire intOutClockXingIn_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_5.sync[0]
connect intOutClockXingOut_5, intOutClockXingIn_5
connect clockNode.auto.anon_in, tapClockNodeOut
connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out
connect intsource.auto.in[0], element_reset_domain.auto.rockettile_halt_out[0]
connect intsource_2.auto.in[0], element_reset_domain.auto.rockettile_cease_out[0]
connect intsource_1.auto.in[0], element_reset_domain.auto.rockettile_wfi_out[0]
connect buffer.auto.in, element_reset_domain.auto.rockettile_buffer_out
connect tlMasterClockXingIn.e.bits, buffer.auto.out.e.bits
connect tlMasterClockXingIn.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, tlMasterClockXingIn.e.ready
connect buffer.auto.out.d, tlMasterClockXingIn.d
connect tlMasterClockXingIn.c.bits, buffer.auto.out.c.bits
connect tlMasterClockXingIn.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, tlMasterClockXingIn.c.ready
connect buffer.auto.out.b, tlMasterClockXingIn.b
connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits
connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready
connect element_reset_domain.auto.rockettile_int_local_in_0[0], intsink.auto.out[0]
connect element_reset_domain.auto.rockettile_int_local_in_1[0], intsink_1.auto.out[0]
connect element_reset_domain.auto.rockettile_int_local_in_1[1], intsink_1.auto.out[1]
connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0]
connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1]
connect element_reset_domain.auto.rockettile_int_local_in_2[0], intsink_2.auto.out[0]
connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0]
connect element_reset_domain.auto.rockettile_int_local_in_3[0], intsink_3.auto.out[0]
connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0]
connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0]
connect intOutClockXingIn, intOutClockXingOut_1
connect intOutClockXingIn_1, intsource.auto.out
connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0]
connect intOutClockXingIn_2, intOutClockXingOut_3
connect intOutClockXingIn_3, intsource_1.auto.out
connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0]
connect intOutClockXingIn_4, intOutClockXingOut_5
connect intOutClockXingIn_5, intsource_2.auto.out
connect tapClockNodeIn, auto.tap_clock_in
connect auto.tl_master_clock_xing_out, tlMasterClockXingOut
connect intInClockXingIn, auto.int_in_clock_xing_in_0
connect intInClockXingIn_1, auto.int_in_clock_xing_in_1
connect intInClockXingIn_2, auto.int_in_clock_xing_in_2
connect element_reset_domain.auto.rockettile_hartid_in, auto.element_reset_domain_rockettile_hartid_in
connect element_reset_domain.auto.rockettile_reset_vector_in, auto.element_reset_domain_rockettile_reset_vector_in
connect auto.element_reset_domain_rockettile_trace_source_out.time, element_reset_domain.auto.rockettile_trace_source_out.time
connect auto.element_reset_domain_rockettile_trace_source_out.insns, element_reset_domain.auto.rockettile_trace_source_out.insns
connect auto.element_reset_domain_rockettile_trace_core_source_out.cause, element_reset_domain.auto.rockettile_trace_core_source_out.cause
connect auto.element_reset_domain_rockettile_trace_core_source_out.tval, element_reset_domain.auto.rockettile_trace_core_source_out.tval
connect auto.element_reset_domain_rockettile_trace_core_source_out.priv, element_reset_domain.auto.rockettile_trace_core_source_out.priv
connect auto.element_reset_domain_rockettile_trace_core_source_out.group, element_reset_domain.auto.rockettile_trace_core_source_out.group
connect intsink.auto.in.sync[0], auto.intsink_in.sync[0]
connect auto.intsink_out_0, intsink_4.auto.out
connect auto.intsink_out_1, intsink_5.auto.out
connect auto.intsink_out_2, intsink_6.auto.out
connect childClock, tapClockNodeIn.clock
connect childReset, tapClockNodeIn.reset
connect clock, tapClockNodeIn.clock
connect reset, tapClockNodeIn.reset
extmodule plusarg_reader_100 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_101 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TilePRCIDomain_1( // @[ClockDomain.scala:14:9]
output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [3:0] auto_tl_master_clock_xing_out_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [15:0] auto_tl_master_clock_xing_out_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9]
wire [15:0] tlMasterClockXingOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17]
wire [15:0] tlMasterClockXingIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [127:0] auto_tl_master_clock_xing_out_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9]
wire [127:0] tlMasterClockXingOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17]
wire [127:0] tlMasterClockXingIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire element_reset_domain_auto_rockettile_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [127:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [15:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_d_valid; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_e_valid; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31]
wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31]
assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17]
wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9]
assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9]
wire [127:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9]
assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17]
assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17]
assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
RocketTile_1 element_reset_domain_rockettile ( // @[HasTiles.scala:164:59]
.clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31]
.reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_out_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data),
.auto_buffer_out_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready),
.auto_buffer_out_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data),
.auto_buffer_out_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready),
.auto_buffer_out_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink),
.auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0),
.auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9]
.auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9]
.auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid),
.auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr),
.auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn),
.auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv),
.auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception),
.auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt),
.auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause),
.auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval),
.auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time),
.auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9]
); // @[HasTiles.scala:164:59]
TLBuffer_a32d128s2k4z4c_3 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (element_reset_domain_auto_rockettile_buffer_out_a_ready),
.auto_in_a_valid (element_reset_domain_auto_rockettile_buffer_out_a_valid), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_b_ready (element_reset_domain_auto_rockettile_buffer_out_b_ready), // @[ClockDomain.scala:14:9]
.auto_in_b_valid (element_reset_domain_auto_rockettile_buffer_out_b_valid),
.auto_in_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_b_bits_opcode),
.auto_in_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_b_bits_param),
.auto_in_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_b_bits_size),
.auto_in_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_b_bits_source),
.auto_in_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_b_bits_address),
.auto_in_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_b_bits_mask),
.auto_in_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_b_bits_data),
.auto_in_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_b_bits_corrupt),
.auto_in_c_ready (element_reset_domain_auto_rockettile_buffer_out_c_ready),
.auto_in_c_valid (element_reset_domain_auto_rockettile_buffer_out_c_valid), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (element_reset_domain_auto_rockettile_buffer_out_d_ready), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (element_reset_domain_auto_rockettile_buffer_out_d_valid),
.auto_in_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_d_bits_opcode),
.auto_in_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_d_bits_param),
.auto_in_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_d_bits_size),
.auto_in_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_d_bits_source),
.auto_in_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_d_bits_sink),
.auto_in_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_d_bits_denied),
.auto_in_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_d_bits_data),
.auto_in_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_d_bits_corrupt),
.auto_in_e_ready (element_reset_domain_auto_rockettile_buffer_out_e_ready),
.auto_in_e_valid (element_reset_domain_auto_rockettile_buffer_out_e_valid), // @[ClockDomain.scala:14:9]
.auto_in_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9]
.auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlMasterClockXingIn_a_valid),
.auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode),
.auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param),
.auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size),
.auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source),
.auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address),
.auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask),
.auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data),
.auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt),
.auto_out_b_ready (tlMasterClockXingIn_b_ready),
.auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17]
.auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17]
.auto_out_c_valid (tlMasterClockXingIn_c_valid),
.auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode),
.auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param),
.auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size),
.auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source),
.auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address),
.auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data),
.auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt),
.auto_out_d_ready (tlMasterClockXingIn_d_ready),
.auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17]
.auto_out_e_valid (tlMasterClockXingIn_e_valid),
.auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink)
); // @[Buffer.scala:75:28]
TLBuffer_4 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1_1 intsink ( // @[Crossing.scala:86:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2_1 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0),
.auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_5 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_6 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_7 intsink_4 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_8 intsink_5 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (auto_intsink_out_1_0_0)
); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_4 intsource_1 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9]
.auto_out_sync_0 (intOutClockXingIn_3_sync_0)
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_9 intsink_6 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_5 intsource_2 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a32d256s5k3z4u_13 :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a32d256s5k3z4u_13( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [31:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [31:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [255:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [31:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [31:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output [255:0] io_deq_bits_data, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [31:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [31:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [31:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [255:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [31:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [31:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [255:0] io_deq_bits_data_0; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [3:0] saved_size; // @[Repeater.scala:21:18]
reg [4:0] saved_source; // @[Repeater.scala:21:18]
reg [31:0] saved_address; // @[Repeater.scala:21:18]
reg [31:0] saved_mask; // @[Repeater.scala:21:18]
reg [255:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_195 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_351
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_195( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_351 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ConstellationPeripheryBus :
output auto : { coupler_to_prci_ctrl_fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bootrom_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_debug_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_plic_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_clint_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_pbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_l2_ctrl_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip cbus_clock_groups_in : { member : { cbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
input custom_boot : UInt<1>
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst cbus_clock_groups of ClockGroupAggregator_cbus
inst clockGroup of ClockGroup_3
inst fixedClockNode of FixedClockBroadcast_7
inst broadcast of BundleBridgeNexus_NoOutput_3
inst fixer of TLFIFOFixer_2
connect fixer.clock, childClock
connect fixer.reset, childReset
inst in_xbar of TLXbar_i2_o1_a29d64s7k1z4u
connect in_xbar.clock, childClock
connect in_xbar.reset, childReset
inst out_noc of TLNoC_1
connect out_noc.clock, childClock
connect out_noc.reset, childReset
inst buffer of TLBuffer_a29d64s7k1z4u
connect buffer.clock, childClock
connect buffer.reset, childReset
inst atomics of TLAtomicAutomata
connect atomics.clock, childClock
connect atomics.reset, childReset
inst wrapped_error_device of ErrorDeviceWrapper
connect wrapped_error_device.clock, childClock
connect wrapped_error_device.reset, childReset
inst coupler_to_l2_ctrl of TLInterconnectCoupler_cbus_to_l2_ctrl
connect coupler_to_l2_ctrl.clock, childClock
connect coupler_to_l2_ctrl.reset, childReset
inst buffer_1 of TLBuffer_a29d64s6k1z4u
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst coupler_to_bus_named_pbus of TLInterconnectCoupler_cbus_to_bus_named_pbus
connect coupler_to_bus_named_pbus.clock, childClock
connect coupler_to_bus_named_pbus.reset, childReset
inst coupler_to_clint of TLInterconnectCoupler_cbus_to_clint
connect coupler_to_clint.clock, childClock
connect coupler_to_clint.reset, childReset
inst coupler_to_plic of TLInterconnectCoupler_cbus_to_plic
connect coupler_to_plic.clock, childClock
connect coupler_to_plic.reset, childReset
inst coupler_to_debug of TLInterconnectCoupler_cbus_to_debug
connect coupler_to_debug.clock, childClock
connect coupler_to_debug.reset, childReset
inst coupler_to_rockettile of TLInterconnectCoupler_cbus_to_rockettile
connect coupler_to_rockettile.clock, childClock
connect coupler_to_rockettile.reset, childReset
inst coupler_to_rockettile_1 of TLInterconnectCoupler_cbus_to_rockettile_1
connect coupler_to_rockettile_1.clock, childClock
connect coupler_to_rockettile_1.reset, childReset
inst coupler_to_rockettile_2 of TLInterconnectCoupler_cbus_to_rockettile_2
connect coupler_to_rockettile_2.clock, childClock
connect coupler_to_rockettile_2.reset, childReset
inst coupler_to_rockettile_3 of TLInterconnectCoupler_cbus_to_rockettile_3
connect coupler_to_rockettile_3.clock, childClock
connect coupler_to_rockettile_3.reset, childReset
inst coupler_to_rockettile_4 of TLInterconnectCoupler_cbus_to_rockettile_4
connect coupler_to_rockettile_4.clock, childClock
connect coupler_to_rockettile_4.reset, childReset
inst coupler_to_rockettile_5 of TLInterconnectCoupler_cbus_to_rockettile_5
connect coupler_to_rockettile_5.clock, childClock
connect coupler_to_rockettile_5.reset, childReset
inst coupler_to_rockettile_6 of TLInterconnectCoupler_cbus_to_rockettile_6
connect coupler_to_rockettile_6.clock, childClock
connect coupler_to_rockettile_6.reset, childReset
inst coupler_to_rockettile_7 of TLInterconnectCoupler_cbus_to_rockettile_7
connect coupler_to_rockettile_7.clock, childClock
connect coupler_to_rockettile_7.reset, childReset
inst coupler_to_bootrom of TLInterconnectCoupler_cbus_to_bootrom
connect coupler_to_bootrom.clock, childClock
connect coupler_to_bootrom.reset, childReset
inst coupler_from_port_named_custom_boot_pin of TLInterconnectCoupler_cbus_from_port_named_custom_boot_pin
connect coupler_from_port_named_custom_boot_pin.clock, childClock
connect coupler_from_port_named_custom_boot_pin.reset, childReset
inst coupler_to_prci_ctrl of TLInterconnectCoupler_cbus_to_prci_ctrl
connect coupler_to_prci_ctrl.clock, childClock
connect coupler_to_prci_ctrl.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingOut.d.bits.corrupt
invalidate bus_xingOut.d.bits.data
invalidate bus_xingOut.d.bits.denied
invalidate bus_xingOut.d.bits.sink
invalidate bus_xingOut.d.bits.source
invalidate bus_xingOut.d.bits.size
invalidate bus_xingOut.d.bits.param
invalidate bus_xingOut.d.bits.opcode
invalidate bus_xingOut.d.valid
invalidate bus_xingOut.d.ready
invalidate bus_xingOut.a.bits.corrupt
invalidate bus_xingOut.a.bits.data
invalidate bus_xingOut.a.bits.mask
invalidate bus_xingOut.a.bits.address
invalidate bus_xingOut.a.bits.source
invalidate bus_xingOut.a.bits.size
invalidate bus_xingOut.a.bits.param
invalidate bus_xingOut.a.bits.opcode
invalidate bus_xingOut.a.valid
invalidate bus_xingOut.a.ready
wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingIn.d.bits.corrupt
invalidate bus_xingIn.d.bits.data
invalidate bus_xingIn.d.bits.denied
invalidate bus_xingIn.d.bits.sink
invalidate bus_xingIn.d.bits.source
invalidate bus_xingIn.d.bits.size
invalidate bus_xingIn.d.bits.param
invalidate bus_xingIn.d.bits.opcode
invalidate bus_xingIn.d.valid
invalidate bus_xingIn.d.ready
invalidate bus_xingIn.a.bits.corrupt
invalidate bus_xingIn.a.bits.data
invalidate bus_xingIn.a.bits.mask
invalidate bus_xingIn.a.bits.address
invalidate bus_xingIn.a.bits.source
invalidate bus_xingIn.a.bits.size
invalidate bus_xingIn.a.bits.param
invalidate bus_xingIn.a.bits.opcode
invalidate bus_xingIn.a.valid
invalidate bus_xingIn.a.ready
connect bus_xingOut, bus_xingIn
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect clockGroup.auto.in, cbus_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect out_noc.auto.in, fixer.auto.anon_out
connect atomics.auto.in, in_xbar.auto.anon_out
connect wrapped_error_device.auto.buffer_in, out_noc.auto.out_0
connect coupler_to_l2_ctrl.auto.tl_in, out_noc.auto.out_1
connect coupler_to_bus_named_pbus.auto.widget_anon_in, out_noc.auto.out_2
connect coupler_to_clint.auto.tl_in, out_noc.auto.out_3
connect coupler_to_plic.auto.tl_in, out_noc.auto.out_4
connect coupler_to_debug.auto.tl_in, out_noc.auto.out_5
connect coupler_to_bootrom.auto.tl_in, out_noc.auto.out_6
connect coupler_to_prci_ctrl.auto.tl_in, out_noc.auto.out_7
connect fixer.auto.anon_in, buffer.auto.out
connect buffer.auto.in, atomics.auto.out
connect in_xbar.auto.anon_in_0, buffer_1.auto.out
connect buffer_1.auto.in, bus_xingOut
connect coupler_from_port_named_custom_boot_pin.auto.tl_in, nodeOut
connect in_xbar.auto.anon_in_1, coupler_from_port_named_custom_boot_pin.auto.tl_out
connect bus_xingIn, auto.bus_xing_in
connect cbus_clock_groups.auto.in, auto.cbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3
connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4
connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5
connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6
connect coupler_to_l2_ctrl.auto.buffer_out.d, auto.coupler_to_l2_ctrl_buffer_out.d
connect auto.coupler_to_l2_ctrl_buffer_out.a.bits, coupler_to_l2_ctrl.auto.buffer_out.a.bits
connect auto.coupler_to_l2_ctrl_buffer_out.a.valid, coupler_to_l2_ctrl.auto.buffer_out.a.valid
connect coupler_to_l2_ctrl.auto.buffer_out.a.ready, auto.coupler_to_l2_ctrl_buffer_out.a.ready
connect coupler_to_bus_named_pbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_pbus_bus_xing_out.d
connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.bits, coupler_to_bus_named_pbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.valid, coupler_to_bus_named_pbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_pbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_pbus_bus_xing_out.a.ready
connect coupler_to_clint.auto.fragmenter_anon_out.d, auto.coupler_to_clint_fragmenter_anon_out.d
connect auto.coupler_to_clint_fragmenter_anon_out.a.bits, coupler_to_clint.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_clint_fragmenter_anon_out.a.valid, coupler_to_clint.auto.fragmenter_anon_out.a.valid
connect coupler_to_clint.auto.fragmenter_anon_out.a.ready, auto.coupler_to_clint_fragmenter_anon_out.a.ready
connect coupler_to_plic.auto.fragmenter_anon_out.d, auto.coupler_to_plic_fragmenter_anon_out.d
connect auto.coupler_to_plic_fragmenter_anon_out.a.bits, coupler_to_plic.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_plic_fragmenter_anon_out.a.valid, coupler_to_plic.auto.fragmenter_anon_out.a.valid
connect coupler_to_plic.auto.fragmenter_anon_out.a.ready, auto.coupler_to_plic_fragmenter_anon_out.a.ready
connect coupler_to_debug.auto.fragmenter_anon_out.d, auto.coupler_to_debug_fragmenter_anon_out.d
connect auto.coupler_to_debug_fragmenter_anon_out.a.bits, coupler_to_debug.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_debug_fragmenter_anon_out.a.valid, coupler_to_debug.auto.fragmenter_anon_out.a.valid
connect coupler_to_debug.auto.fragmenter_anon_out.a.ready, auto.coupler_to_debug_fragmenter_anon_out.a.ready
connect coupler_to_bootrom.auto.fragmenter_anon_out.d, auto.coupler_to_bootrom_fragmenter_anon_out.d
connect auto.coupler_to_bootrom_fragmenter_anon_out.a.bits, coupler_to_bootrom.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_bootrom_fragmenter_anon_out.a.valid, coupler_to_bootrom.auto.fragmenter_anon_out.a.valid
connect coupler_to_bootrom.auto.fragmenter_anon_out.a.ready, auto.coupler_to_bootrom_fragmenter_anon_out.a.ready
connect coupler_to_prci_ctrl.auto.fixer_anon_out.d, auto.coupler_to_prci_ctrl_fixer_anon_out.d
connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.bits, coupler_to_prci_ctrl.auto.fixer_anon_out.a.bits
connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.valid, coupler_to_prci_ctrl.auto.fixer_anon_out.a.valid
connect coupler_to_prci_ctrl.auto.fixer_anon_out.a.ready, auto.coupler_to_prci_ctrl_fixer_anon_out.a.ready
regreset state : UInt<3>, childClock, childReset, UInt<3>(0h0)
connect nodeOut.a.valid, UInt<1>(0h0)
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
connect nodeOut.d.ready, UInt<1>(0h1)
node _T = eq(UInt<3>(0h0), state)
when _T :
when custom_boot :
connect state, UInt<3>(0h1)
else :
node _T_1 = eq(UInt<3>(0h1), state)
when _T_1 :
connect nodeOut.a.valid, UInt<1>(0h1)
node _nodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_1 = leq(UInt<2>(0h2), UInt<4>(0hc))
node _nodeOut_a_bits_legal_T_2 = and(_nodeOut_a_bits_legal_T, _nodeOut_a_bits_legal_T_1)
node _nodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_2)
node _nodeOut_a_bits_legal_T_4 = xor(UInt<13>(0h1000), UInt<14>(0h3000))
node _nodeOut_a_bits_legal_T_5 = cvt(_nodeOut_a_bits_legal_T_4)
node _nodeOut_a_bits_legal_T_6 = and(_nodeOut_a_bits_legal_T_5, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_7 = asSInt(_nodeOut_a_bits_legal_T_6)
node _nodeOut_a_bits_legal_T_8 = eq(_nodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_9 = and(_nodeOut_a_bits_legal_T_3, _nodeOut_a_bits_legal_T_8)
node _nodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_11 = leq(UInt<2>(0h2), UInt<3>(0h6))
node _nodeOut_a_bits_legal_T_12 = and(_nodeOut_a_bits_legal_T_10, _nodeOut_a_bits_legal_T_11)
node _nodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_12)
node _nodeOut_a_bits_legal_T_14 = xor(UInt<13>(0h1000), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_15 = cvt(_nodeOut_a_bits_legal_T_14)
node _nodeOut_a_bits_legal_T_16 = and(_nodeOut_a_bits_legal_T_15, asSInt(UInt<30>(0h1a112000)))
node _nodeOut_a_bits_legal_T_17 = asSInt(_nodeOut_a_bits_legal_T_16)
node _nodeOut_a_bits_legal_T_18 = eq(_nodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_19 = xor(UInt<13>(0h1000), UInt<21>(0h100000))
node _nodeOut_a_bits_legal_T_20 = cvt(_nodeOut_a_bits_legal_T_19)
node _nodeOut_a_bits_legal_T_21 = and(_nodeOut_a_bits_legal_T_20, asSInt(UInt<30>(0h1a103000)))
node _nodeOut_a_bits_legal_T_22 = asSInt(_nodeOut_a_bits_legal_T_21)
node _nodeOut_a_bits_legal_T_23 = eq(_nodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_24 = xor(UInt<13>(0h1000), UInt<26>(0h2000000))
node _nodeOut_a_bits_legal_T_25 = cvt(_nodeOut_a_bits_legal_T_24)
node _nodeOut_a_bits_legal_T_26 = and(_nodeOut_a_bits_legal_T_25, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_27 = asSInt(_nodeOut_a_bits_legal_T_26)
node _nodeOut_a_bits_legal_T_28 = eq(_nodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_29 = xor(UInt<13>(0h1000), UInt<26>(0h2010000))
node _nodeOut_a_bits_legal_T_30 = cvt(_nodeOut_a_bits_legal_T_29)
node _nodeOut_a_bits_legal_T_31 = and(_nodeOut_a_bits_legal_T_30, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_32 = asSInt(_nodeOut_a_bits_legal_T_31)
node _nodeOut_a_bits_legal_T_33 = eq(_nodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_34 = xor(UInt<13>(0h1000), UInt<28>(0h8000000))
node _nodeOut_a_bits_legal_T_35 = cvt(_nodeOut_a_bits_legal_T_34)
node _nodeOut_a_bits_legal_T_36 = and(_nodeOut_a_bits_legal_T_35, asSInt(UInt<30>(0h18000000)))
node _nodeOut_a_bits_legal_T_37 = asSInt(_nodeOut_a_bits_legal_T_36)
node _nodeOut_a_bits_legal_T_38 = eq(_nodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_39 = xor(UInt<13>(0h1000), UInt<29>(0h10000000))
node _nodeOut_a_bits_legal_T_40 = cvt(_nodeOut_a_bits_legal_T_39)
node _nodeOut_a_bits_legal_T_41 = and(_nodeOut_a_bits_legal_T_40, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_42 = asSInt(_nodeOut_a_bits_legal_T_41)
node _nodeOut_a_bits_legal_T_43 = eq(_nodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_44 = or(_nodeOut_a_bits_legal_T_18, _nodeOut_a_bits_legal_T_23)
node _nodeOut_a_bits_legal_T_45 = or(_nodeOut_a_bits_legal_T_44, _nodeOut_a_bits_legal_T_28)
node _nodeOut_a_bits_legal_T_46 = or(_nodeOut_a_bits_legal_T_45, _nodeOut_a_bits_legal_T_33)
node _nodeOut_a_bits_legal_T_47 = or(_nodeOut_a_bits_legal_T_46, _nodeOut_a_bits_legal_T_38)
node _nodeOut_a_bits_legal_T_48 = or(_nodeOut_a_bits_legal_T_47, _nodeOut_a_bits_legal_T_43)
node _nodeOut_a_bits_legal_T_49 = and(_nodeOut_a_bits_legal_T_13, _nodeOut_a_bits_legal_T_48)
node _nodeOut_a_bits_legal_T_50 = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_51 = xor(UInt<13>(0h1000), UInt<17>(0h10000))
node _nodeOut_a_bits_legal_T_52 = cvt(_nodeOut_a_bits_legal_T_51)
node _nodeOut_a_bits_legal_T_53 = and(_nodeOut_a_bits_legal_T_52, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_54 = asSInt(_nodeOut_a_bits_legal_T_53)
node _nodeOut_a_bits_legal_T_55 = eq(_nodeOut_a_bits_legal_T_54, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_56 = and(_nodeOut_a_bits_legal_T_50, _nodeOut_a_bits_legal_T_55)
node _nodeOut_a_bits_legal_T_57 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_9)
node _nodeOut_a_bits_legal_T_58 = or(_nodeOut_a_bits_legal_T_57, _nodeOut_a_bits_legal_T_49)
node nodeOut_a_bits_legal = or(_nodeOut_a_bits_legal_T_58, _nodeOut_a_bits_legal_T_56)
wire nodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_a_bits_a.opcode, UInt<1>(0h0)
connect nodeOut_a_bits_a.param, UInt<1>(0h0)
connect nodeOut_a_bits_a.size, UInt<2>(0h2)
connect nodeOut_a_bits_a.source, UInt<1>(0h0)
connect nodeOut_a_bits_a.address, UInt<13>(0h1000)
node _nodeOut_a_bits_a_mask_sizeOH_T = or(UInt<2>(0h2), UInt<3>(0h0))
node nodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_nodeOut_a_bits_a_mask_sizeOH_T, 1, 0)
node _nodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount)
node _nodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0)
node nodeOut_a_bits_a_mask_sizeOH = or(_nodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<2>(0h2), UInt<2>(0h3))
node nodeOut_a_bits_a_mask_sub_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 2, 2)
node nodeOut_a_bits_a_mask_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_0_2)
node nodeOut_a_bits_a_mask_sub_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T)
node nodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_1_2)
node nodeOut_a_bits_a_mask_sub_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_1)
node nodeOut_a_bits_a_mask_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 1, 1)
node nodeOut_a_bits_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_0_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, nodeOut_a_bits_a_mask_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_0_2)
node nodeOut_a_bits_a_mask_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T)
node nodeOut_a_bits_a_mask_sub_1_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_1_2)
node nodeOut_a_bits_a_mask_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T_1)
node nodeOut_a_bits_a_mask_sub_2_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, nodeOut_a_bits_a_mask_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_2_2)
node nodeOut_a_bits_a_mask_sub_2_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_2)
node nodeOut_a_bits_a_mask_sub_3_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_3_2)
node nodeOut_a_bits_a_mask_sub_3_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_3)
node nodeOut_a_bits_a_mask_size = bits(nodeOut_a_bits_a_mask_sizeOH, 0, 0)
node nodeOut_a_bits_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_eq = and(nodeOut_a_bits_a_mask_sub_0_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq)
node nodeOut_a_bits_a_mask_acc = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T)
node nodeOut_a_bits_a_mask_eq_1 = and(nodeOut_a_bits_a_mask_sub_0_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_1 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_1)
node nodeOut_a_bits_a_mask_acc_1 = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T_1)
node nodeOut_a_bits_a_mask_eq_2 = and(nodeOut_a_bits_a_mask_sub_1_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_2 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_2)
node nodeOut_a_bits_a_mask_acc_2 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_2)
node nodeOut_a_bits_a_mask_eq_3 = and(nodeOut_a_bits_a_mask_sub_1_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_3 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_3)
node nodeOut_a_bits_a_mask_acc_3 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_3)
node nodeOut_a_bits_a_mask_eq_4 = and(nodeOut_a_bits_a_mask_sub_2_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_4 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_4)
node nodeOut_a_bits_a_mask_acc_4 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_4)
node nodeOut_a_bits_a_mask_eq_5 = and(nodeOut_a_bits_a_mask_sub_2_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_5 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_5)
node nodeOut_a_bits_a_mask_acc_5 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_5)
node nodeOut_a_bits_a_mask_eq_6 = and(nodeOut_a_bits_a_mask_sub_3_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_6 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_6)
node nodeOut_a_bits_a_mask_acc_6 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_6)
node nodeOut_a_bits_a_mask_eq_7 = and(nodeOut_a_bits_a_mask_sub_3_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_7 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_7)
node nodeOut_a_bits_a_mask_acc_7 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_7)
node nodeOut_a_bits_a_mask_lo_lo = cat(nodeOut_a_bits_a_mask_acc_1, nodeOut_a_bits_a_mask_acc)
node nodeOut_a_bits_a_mask_lo_hi = cat(nodeOut_a_bits_a_mask_acc_3, nodeOut_a_bits_a_mask_acc_2)
node nodeOut_a_bits_a_mask_lo = cat(nodeOut_a_bits_a_mask_lo_hi, nodeOut_a_bits_a_mask_lo_lo)
node nodeOut_a_bits_a_mask_hi_lo = cat(nodeOut_a_bits_a_mask_acc_5, nodeOut_a_bits_a_mask_acc_4)
node nodeOut_a_bits_a_mask_hi_hi = cat(nodeOut_a_bits_a_mask_acc_7, nodeOut_a_bits_a_mask_acc_6)
node nodeOut_a_bits_a_mask_hi = cat(nodeOut_a_bits_a_mask_hi_hi, nodeOut_a_bits_a_mask_hi_lo)
node _nodeOut_a_bits_a_mask_T = cat(nodeOut_a_bits_a_mask_hi, nodeOut_a_bits_a_mask_lo)
connect nodeOut_a_bits_a.mask, _nodeOut_a_bits_a_mask_T
connect nodeOut_a_bits_a.data, UInt<32>(0h80000000)
connect nodeOut_a_bits_a.corrupt, UInt<1>(0h0)
connect nodeOut.a.bits, nodeOut_a_bits_a
node _T_2 = and(nodeOut.a.ready, nodeOut.a.valid)
when _T_2 :
connect state, UInt<3>(0h2)
else :
node _T_3 = eq(UInt<3>(0h2), state)
when _T_3 :
node _T_4 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_4 :
connect state, UInt<3>(0h3)
else :
node _T_5 = eq(UInt<3>(0h3), state)
when _T_5 :
connect nodeOut.a.valid, UInt<1>(0h1)
node _nodeOut_a_bits_legal_T_59 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_60 = leq(UInt<2>(0h2), UInt<4>(0hc))
node _nodeOut_a_bits_legal_T_61 = and(_nodeOut_a_bits_legal_T_59, _nodeOut_a_bits_legal_T_60)
node _nodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_61)
node _nodeOut_a_bits_legal_T_63 = xor(UInt<26>(0h2000000), UInt<14>(0h3000))
node _nodeOut_a_bits_legal_T_64 = cvt(_nodeOut_a_bits_legal_T_63)
node _nodeOut_a_bits_legal_T_65 = and(_nodeOut_a_bits_legal_T_64, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_66 = asSInt(_nodeOut_a_bits_legal_T_65)
node _nodeOut_a_bits_legal_T_67 = eq(_nodeOut_a_bits_legal_T_66, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_68 = and(_nodeOut_a_bits_legal_T_62, _nodeOut_a_bits_legal_T_67)
node _nodeOut_a_bits_legal_T_69 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_70 = leq(UInt<2>(0h2), UInt<3>(0h6))
node _nodeOut_a_bits_legal_T_71 = and(_nodeOut_a_bits_legal_T_69, _nodeOut_a_bits_legal_T_70)
node _nodeOut_a_bits_legal_T_72 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_71)
node _nodeOut_a_bits_legal_T_73 = xor(UInt<26>(0h2000000), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_74 = cvt(_nodeOut_a_bits_legal_T_73)
node _nodeOut_a_bits_legal_T_75 = and(_nodeOut_a_bits_legal_T_74, asSInt(UInt<30>(0h1a112000)))
node _nodeOut_a_bits_legal_T_76 = asSInt(_nodeOut_a_bits_legal_T_75)
node _nodeOut_a_bits_legal_T_77 = eq(_nodeOut_a_bits_legal_T_76, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_78 = xor(UInt<26>(0h2000000), UInt<21>(0h100000))
node _nodeOut_a_bits_legal_T_79 = cvt(_nodeOut_a_bits_legal_T_78)
node _nodeOut_a_bits_legal_T_80 = and(_nodeOut_a_bits_legal_T_79, asSInt(UInt<30>(0h1a103000)))
node _nodeOut_a_bits_legal_T_81 = asSInt(_nodeOut_a_bits_legal_T_80)
node _nodeOut_a_bits_legal_T_82 = eq(_nodeOut_a_bits_legal_T_81, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_83 = xor(UInt<26>(0h2000000), UInt<26>(0h2000000))
node _nodeOut_a_bits_legal_T_84 = cvt(_nodeOut_a_bits_legal_T_83)
node _nodeOut_a_bits_legal_T_85 = and(_nodeOut_a_bits_legal_T_84, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_86 = asSInt(_nodeOut_a_bits_legal_T_85)
node _nodeOut_a_bits_legal_T_87 = eq(_nodeOut_a_bits_legal_T_86, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_88 = xor(UInt<26>(0h2000000), UInt<26>(0h2010000))
node _nodeOut_a_bits_legal_T_89 = cvt(_nodeOut_a_bits_legal_T_88)
node _nodeOut_a_bits_legal_T_90 = and(_nodeOut_a_bits_legal_T_89, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_91 = asSInt(_nodeOut_a_bits_legal_T_90)
node _nodeOut_a_bits_legal_T_92 = eq(_nodeOut_a_bits_legal_T_91, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_93 = xor(UInt<26>(0h2000000), UInt<28>(0h8000000))
node _nodeOut_a_bits_legal_T_94 = cvt(_nodeOut_a_bits_legal_T_93)
node _nodeOut_a_bits_legal_T_95 = and(_nodeOut_a_bits_legal_T_94, asSInt(UInt<30>(0h18000000)))
node _nodeOut_a_bits_legal_T_96 = asSInt(_nodeOut_a_bits_legal_T_95)
node _nodeOut_a_bits_legal_T_97 = eq(_nodeOut_a_bits_legal_T_96, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_98 = xor(UInt<26>(0h2000000), UInt<29>(0h10000000))
node _nodeOut_a_bits_legal_T_99 = cvt(_nodeOut_a_bits_legal_T_98)
node _nodeOut_a_bits_legal_T_100 = and(_nodeOut_a_bits_legal_T_99, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_101 = asSInt(_nodeOut_a_bits_legal_T_100)
node _nodeOut_a_bits_legal_T_102 = eq(_nodeOut_a_bits_legal_T_101, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_103 = or(_nodeOut_a_bits_legal_T_77, _nodeOut_a_bits_legal_T_82)
node _nodeOut_a_bits_legal_T_104 = or(_nodeOut_a_bits_legal_T_103, _nodeOut_a_bits_legal_T_87)
node _nodeOut_a_bits_legal_T_105 = or(_nodeOut_a_bits_legal_T_104, _nodeOut_a_bits_legal_T_92)
node _nodeOut_a_bits_legal_T_106 = or(_nodeOut_a_bits_legal_T_105, _nodeOut_a_bits_legal_T_97)
node _nodeOut_a_bits_legal_T_107 = or(_nodeOut_a_bits_legal_T_106, _nodeOut_a_bits_legal_T_102)
node _nodeOut_a_bits_legal_T_108 = and(_nodeOut_a_bits_legal_T_72, _nodeOut_a_bits_legal_T_107)
node _nodeOut_a_bits_legal_T_109 = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_110 = xor(UInt<26>(0h2000000), UInt<17>(0h10000))
node _nodeOut_a_bits_legal_T_111 = cvt(_nodeOut_a_bits_legal_T_110)
node _nodeOut_a_bits_legal_T_112 = and(_nodeOut_a_bits_legal_T_111, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_113 = asSInt(_nodeOut_a_bits_legal_T_112)
node _nodeOut_a_bits_legal_T_114 = eq(_nodeOut_a_bits_legal_T_113, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_115 = and(_nodeOut_a_bits_legal_T_109, _nodeOut_a_bits_legal_T_114)
node _nodeOut_a_bits_legal_T_116 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_68)
node _nodeOut_a_bits_legal_T_117 = or(_nodeOut_a_bits_legal_T_116, _nodeOut_a_bits_legal_T_108)
node nodeOut_a_bits_legal_1 = or(_nodeOut_a_bits_legal_T_117, _nodeOut_a_bits_legal_T_115)
wire nodeOut_a_bits_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_a_bits_a_1.opcode, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.param, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.size, UInt<2>(0h2)
connect nodeOut_a_bits_a_1.source, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.address, UInt<26>(0h2000000)
node _nodeOut_a_bits_a_mask_sizeOH_T_3 = or(UInt<2>(0h2), UInt<3>(0h0))
node nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_3, 1, 0)
node _nodeOut_a_bits_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1)
node _nodeOut_a_bits_a_mask_sizeOH_T_5 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_4, 2, 0)
node nodeOut_a_bits_a_mask_sizeOH_1 = or(_nodeOut_a_bits_a_mask_sizeOH_T_5, UInt<1>(0h1))
node nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = geq(UInt<2>(0h2), UInt<2>(0h3))
node nodeOut_a_bits_a_mask_sub_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 2, 2)
node nodeOut_a_bits_a_mask_sub_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_0_2_1)
node nodeOut_a_bits_a_mask_sub_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_2)
node nodeOut_a_bits_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_1_2_1)
node nodeOut_a_bits_a_mask_sub_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_3)
node nodeOut_a_bits_a_mask_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 1, 1)
node nodeOut_a_bits_a_mask_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_0_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, nodeOut_a_bits_a_mask_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_acc_T_4 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_0_2_1)
node nodeOut_a_bits_a_mask_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_4)
node nodeOut_a_bits_a_mask_sub_1_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_5 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_1_2_1)
node nodeOut_a_bits_a_mask_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_5)
node nodeOut_a_bits_a_mask_sub_2_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, nodeOut_a_bits_a_mask_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_acc_T_6 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_2_2_1)
node nodeOut_a_bits_a_mask_sub_2_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_6)
node nodeOut_a_bits_a_mask_sub_3_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_7 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_3_2_1)
node nodeOut_a_bits_a_mask_sub_3_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_7)
node nodeOut_a_bits_a_mask_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 0, 0)
node nodeOut_a_bits_a_mask_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_eq_8 = and(nodeOut_a_bits_a_mask_sub_0_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_8 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_8)
node nodeOut_a_bits_a_mask_acc_8 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_8)
node nodeOut_a_bits_a_mask_eq_9 = and(nodeOut_a_bits_a_mask_sub_0_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_9 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_9)
node nodeOut_a_bits_a_mask_acc_9 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_9)
node nodeOut_a_bits_a_mask_eq_10 = and(nodeOut_a_bits_a_mask_sub_1_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_10 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_10)
node nodeOut_a_bits_a_mask_acc_10 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_10)
node nodeOut_a_bits_a_mask_eq_11 = and(nodeOut_a_bits_a_mask_sub_1_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_11 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_11)
node nodeOut_a_bits_a_mask_acc_11 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_11)
node nodeOut_a_bits_a_mask_eq_12 = and(nodeOut_a_bits_a_mask_sub_2_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_12 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_12)
node nodeOut_a_bits_a_mask_acc_12 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_12)
node nodeOut_a_bits_a_mask_eq_13 = and(nodeOut_a_bits_a_mask_sub_2_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_13 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_13)
node nodeOut_a_bits_a_mask_acc_13 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_13)
node nodeOut_a_bits_a_mask_eq_14 = and(nodeOut_a_bits_a_mask_sub_3_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_14 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_14)
node nodeOut_a_bits_a_mask_acc_14 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_14)
node nodeOut_a_bits_a_mask_eq_15 = and(nodeOut_a_bits_a_mask_sub_3_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_15 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_15)
node nodeOut_a_bits_a_mask_acc_15 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_15)
node nodeOut_a_bits_a_mask_lo_lo_1 = cat(nodeOut_a_bits_a_mask_acc_9, nodeOut_a_bits_a_mask_acc_8)
node nodeOut_a_bits_a_mask_lo_hi_1 = cat(nodeOut_a_bits_a_mask_acc_11, nodeOut_a_bits_a_mask_acc_10)
node nodeOut_a_bits_a_mask_lo_1 = cat(nodeOut_a_bits_a_mask_lo_hi_1, nodeOut_a_bits_a_mask_lo_lo_1)
node nodeOut_a_bits_a_mask_hi_lo_1 = cat(nodeOut_a_bits_a_mask_acc_13, nodeOut_a_bits_a_mask_acc_12)
node nodeOut_a_bits_a_mask_hi_hi_1 = cat(nodeOut_a_bits_a_mask_acc_15, nodeOut_a_bits_a_mask_acc_14)
node nodeOut_a_bits_a_mask_hi_1 = cat(nodeOut_a_bits_a_mask_hi_hi_1, nodeOut_a_bits_a_mask_hi_lo_1)
node _nodeOut_a_bits_a_mask_T_1 = cat(nodeOut_a_bits_a_mask_hi_1, nodeOut_a_bits_a_mask_lo_1)
connect nodeOut_a_bits_a_1.mask, _nodeOut_a_bits_a_mask_T_1
connect nodeOut_a_bits_a_1.data, UInt<1>(0h1)
connect nodeOut_a_bits_a_1.corrupt, UInt<1>(0h0)
connect nodeOut.a.bits, nodeOut_a_bits_a_1
node _T_6 = and(nodeOut.a.ready, nodeOut.a.valid)
when _T_6 :
connect state, UInt<3>(0h4)
else :
node _T_7 = eq(UInt<3>(0h4), state)
when _T_7 :
node _T_8 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_8 :
connect state, UInt<3>(0h5)
else :
node _T_9 = eq(UInt<3>(0h5), state)
when _T_9 :
node _T_10 = eq(custom_boot, UInt<1>(0h0))
when _T_10 :
connect state, UInt<3>(0h0)
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module ConstellationPeripheryBus( // @[ClockDomain.scala:14:9]
input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input custom_boot // @[CustomBootPin.scala:36:29]
);
wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29]
wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29]
wire [6:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29]
wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29]
wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29]
wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29]
wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [6:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [28:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _out_noc_auto_in_a_ready; // @[Buses.scala:132:49]
wire _out_noc_auto_in_d_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_in_d_bits_opcode; // @[Buses.scala:132:49]
wire [1:0] _out_noc_auto_in_d_bits_param; // @[Buses.scala:132:49]
wire [3:0] _out_noc_auto_in_d_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_in_d_bits_source; // @[Buses.scala:132:49]
wire _out_noc_auto_in_d_bits_sink; // @[Buses.scala:132:49]
wire _out_noc_auto_in_d_bits_denied; // @[Buses.scala:132:49]
wire [63:0] _out_noc_auto_in_d_bits_data; // @[Buses.scala:132:49]
wire _out_noc_auto_in_d_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_7_a_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_7_a_bits_opcode; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_7_a_bits_param; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_7_a_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_out_7_a_bits_source; // @[Buses.scala:132:49]
wire [20:0] _out_noc_auto_out_7_a_bits_address; // @[Buses.scala:132:49]
wire [7:0] _out_noc_auto_out_7_a_bits_mask; // @[Buses.scala:132:49]
wire [63:0] _out_noc_auto_out_7_a_bits_data; // @[Buses.scala:132:49]
wire _out_noc_auto_out_7_a_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_7_d_ready; // @[Buses.scala:132:49]
wire _out_noc_auto_out_6_a_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_6_a_bits_opcode; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_6_a_bits_param; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_6_a_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_out_6_a_bits_source; // @[Buses.scala:132:49]
wire [16:0] _out_noc_auto_out_6_a_bits_address; // @[Buses.scala:132:49]
wire [7:0] _out_noc_auto_out_6_a_bits_mask; // @[Buses.scala:132:49]
wire _out_noc_auto_out_6_a_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_6_d_ready; // @[Buses.scala:132:49]
wire _out_noc_auto_out_5_a_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_5_a_bits_opcode; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_5_a_bits_param; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_5_a_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_out_5_a_bits_source; // @[Buses.scala:132:49]
wire [11:0] _out_noc_auto_out_5_a_bits_address; // @[Buses.scala:132:49]
wire [7:0] _out_noc_auto_out_5_a_bits_mask; // @[Buses.scala:132:49]
wire [63:0] _out_noc_auto_out_5_a_bits_data; // @[Buses.scala:132:49]
wire _out_noc_auto_out_5_a_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_5_d_ready; // @[Buses.scala:132:49]
wire _out_noc_auto_out_4_a_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_4_a_bits_opcode; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_4_a_bits_param; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_4_a_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_out_4_a_bits_source; // @[Buses.scala:132:49]
wire [27:0] _out_noc_auto_out_4_a_bits_address; // @[Buses.scala:132:49]
wire [7:0] _out_noc_auto_out_4_a_bits_mask; // @[Buses.scala:132:49]
wire [63:0] _out_noc_auto_out_4_a_bits_data; // @[Buses.scala:132:49]
wire _out_noc_auto_out_4_a_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_4_d_ready; // @[Buses.scala:132:49]
wire _out_noc_auto_out_3_a_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_3_a_bits_opcode; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_3_a_bits_param; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_3_a_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_out_3_a_bits_source; // @[Buses.scala:132:49]
wire [25:0] _out_noc_auto_out_3_a_bits_address; // @[Buses.scala:132:49]
wire [7:0] _out_noc_auto_out_3_a_bits_mask; // @[Buses.scala:132:49]
wire [63:0] _out_noc_auto_out_3_a_bits_data; // @[Buses.scala:132:49]
wire _out_noc_auto_out_3_a_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_3_d_ready; // @[Buses.scala:132:49]
wire _out_noc_auto_out_1_a_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_1_a_bits_opcode; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_1_a_bits_param; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_1_a_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_out_1_a_bits_source; // @[Buses.scala:132:49]
wire [25:0] _out_noc_auto_out_1_a_bits_address; // @[Buses.scala:132:49]
wire [7:0] _out_noc_auto_out_1_a_bits_mask; // @[Buses.scala:132:49]
wire [63:0] _out_noc_auto_out_1_a_bits_data; // @[Buses.scala:132:49]
wire _out_noc_auto_out_1_a_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_1_d_ready; // @[Buses.scala:132:49]
wire _out_noc_auto_out_0_a_valid; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_0_a_bits_opcode; // @[Buses.scala:132:49]
wire [2:0] _out_noc_auto_out_0_a_bits_param; // @[Buses.scala:132:49]
wire [3:0] _out_noc_auto_out_0_a_bits_size; // @[Buses.scala:132:49]
wire [6:0] _out_noc_auto_out_0_a_bits_source; // @[Buses.scala:132:49]
wire [13:0] _out_noc_auto_out_0_a_bits_address; // @[Buses.scala:132:49]
wire [7:0] _out_noc_auto_out_0_a_bits_mask; // @[Buses.scala:132:49]
wire [63:0] _out_noc_auto_out_0_a_bits_data; // @[Buses.scala:132:49]
wire _out_noc_auto_out_0_a_bits_corrupt; // @[Buses.scala:132:49]
wire _out_noc_auto_out_0_d_ready; // @[Buses.scala:132:49]
wire _in_xbar_auto_anon_in_1_a_ready; // @[Buses.scala:138:29]
wire _in_xbar_auto_anon_in_1_d_valid; // @[Buses.scala:138:29]
wire _in_xbar_auto_anon_out_a_valid; // @[Buses.scala:138:29]
wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[Buses.scala:138:29]
wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[Buses.scala:138:29]
wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[Buses.scala:138:29]
wire [6:0] _in_xbar_auto_anon_out_a_bits_source; // @[Buses.scala:138:29]
wire [28:0] _in_xbar_auto_anon_out_a_bits_address; // @[Buses.scala:138:29]
wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[Buses.scala:138:29]
wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[Buses.scala:138:29]
wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[Buses.scala:138:29]
wire _in_xbar_auto_anon_out_d_ready; // @[Buses.scala:138:29]
wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114]
wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114]
reg [2:0] state; // @[CustomBootPin.scala:39:28]
wire _GEN = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24]
wire nodeOut_a_valid = (|state) & (_GEN | state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24]
wire _GEN_0 = _in_xbar_auto_anon_in_1_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35]
wire [2:0] _GEN_1 = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}]
wire [7:0][2:0] _GEN_2 = {{_GEN_1}, {_GEN_1}, {_GEN_1}, {_in_xbar_auto_anon_in_1_d_valid ? 3'h5 : state}, {_GEN_0 ? 3'h4 : state}, {_in_xbar_auto_anon_in_1_d_valid ? 3'h3 : state}, {_GEN_0 ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35]
always @(posedge _fixedClockNode_auto_anon_out_0_clock) begin // @[ClockGroup.scala:115:114]
if (_fixedClockNode_auto_anon_out_0_reset) // @[ClockGroup.scala:115:114]
state <= 3'h0; // @[CustomBootPin.scala:39:28]
else // @[ClockGroup.scala:115:114]
state <= _GEN_2[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_177 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_313
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_177( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_313 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_18 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 25)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_18(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_287 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_535
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_287( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_535 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FPToInt_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}}
reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
when io.in.valid :
connect in, io.in.bits
reg valid : UInt<1>, clock
connect valid, io.in.valid
inst dcmp of CompareRecFN_1
connect dcmp.io.a, in.in1
connect dcmp.io.b, in.in2
node _dcmp_io_signaling_T = bits(in.rm, 1, 1)
node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0))
connect dcmp.io.signaling, _dcmp_io_signaling_T_1
node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52)
node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9)
node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10)
node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3))
wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9)
node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T)
connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1
node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9)
node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1)
connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2
connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero
node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64)
connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T
node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp)
connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T
node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T)
node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0)
node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2)
connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3
node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402)))
node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0)
node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T)
node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1)
node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1)
node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist)
node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0)
node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0)
node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401))
node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1)
node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2)
node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf)
node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0))
node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5)
node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0)
node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T)
node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1)
node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut)
node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut)
node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31)
node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52)
node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0)
node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1)
node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 6)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 7)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3))
wire toint_ieee_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2
connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3
node toint_ieee_prevUnrecoded_unrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0)
node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T)
node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1)
node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 1)
node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist)
node toint_ieee_prevUnrecoded_unrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81))
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_1, 1)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node toint_ieee_prevUnrecoded_unrecoded_expOut = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5)
node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T)
node toint_ieee_prevUnrecoded_unrecoded_fractOut = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, toint_ieee_prevUnrecoded_unrecoded_denormFract, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1)
node toint_ieee_prevUnrecoded_unrecoded_hi = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, toint_ieee_prevUnrecoded_unrecoded_expOut)
node toint_ieee_prevUnrecoded_unrecoded = cat(toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut)
node _toint_ieee_prevUnrecoded_prevRecoded_T = bits(toint_ieee_prevRecoded, 15, 15)
node _toint_ieee_prevUnrecoded_prevRecoded_T_1 = bits(toint_ieee_prevRecoded, 23, 23)
node _toint_ieee_prevUnrecoded_prevRecoded_T_2 = bits(toint_ieee_prevRecoded, 14, 0)
node toint_ieee_prevUnrecoded_prevRecoded_hi = cat(_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1)
node toint_ieee_prevUnrecoded_prevRecoded = cat(toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevUnrecoded_prevRecoded, 15, 10)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3))
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevUnrecoded_prevRecoded, 16, 16)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3
node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12)))
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T)
node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist)
node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11))
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0))
node toint_ieee_prevUnrecoded_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5)
node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T)
node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1)
node toint_ieee_prevUnrecoded_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut)
node toint_ieee_prevUnrecoded_prevUnrecoded = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut)
node _toint_ieee_prevUnrecoded_T = shr(toint_ieee_prevUnrecoded_unrecoded, 16)
node _toint_ieee_prevUnrecoded_T_1 = bits(toint_ieee_prevRecoded, 31, 29)
node _toint_ieee_prevUnrecoded_T_2 = andr(_toint_ieee_prevUnrecoded_T_1)
node _toint_ieee_prevUnrecoded_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded, 15, 0)
node _toint_ieee_prevUnrecoded_T_4 = mux(_toint_ieee_prevUnrecoded_T_2, toint_ieee_prevUnrecoded_prevUnrecoded, _toint_ieee_prevUnrecoded_T_3)
node toint_ieee_prevUnrecoded = cat(_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4)
node _toint_ieee_T = shr(toint_ieee_unrecoded, 32)
node _toint_ieee_T_1 = bits(in.in1, 63, 61)
node _toint_ieee_T_2 = andr(_toint_ieee_T_1)
node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0)
node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3)
node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4)
node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 15, 0)
node _toint_ieee_T_7 = bits(_toint_ieee_T_6, 15, 15)
node _toint_ieee_T_8 = mux(_toint_ieee_T_7, UInt<16>(0hffff), UInt<16>(0h0))
node _toint_ieee_T_9 = cat(_toint_ieee_T_8, _toint_ieee_T_6)
node _toint_ieee_T_10 = cat(_toint_ieee_T_9, _toint_ieee_T_9)
node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52)
node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9)
node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10)
node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9)
node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2)
connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3
node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9)
node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4)
connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5
connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1
node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64)
connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1
node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1)
connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1
node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4)
node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0)
node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6)
connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7
node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402)))
node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0)
node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2)
node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1)
node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1)
node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1)
node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0)
node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0)
node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401))
node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1)
node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8)
node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf)
node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0))
node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11)
node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0)
node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2)
node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3)
node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1)
node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1)
node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31)
node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52)
node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0)
node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4)
node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7
node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82)))
node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0)
node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2)
node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1)
node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 1)
node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1)
node toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81))
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_7, 1)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0))
node toint_ieee_prevUnrecoded_unrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11)
node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2)
node toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_unrecoded_denormFract_1, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3)
node toint_ieee_prevUnrecoded_unrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1)
node toint_ieee_prevUnrecoded_unrecoded_1 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1)
node _toint_ieee_prevUnrecoded_prevRecoded_T_3 = bits(toint_ieee_prevRecoded_1, 15, 15)
node _toint_ieee_prevUnrecoded_prevRecoded_T_4 = bits(toint_ieee_prevRecoded_1, 23, 23)
node _toint_ieee_prevUnrecoded_prevRecoded_T_5 = bits(toint_ieee_prevRecoded_1, 14, 0)
node toint_ieee_prevUnrecoded_prevRecoded_hi_1 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4)
node toint_ieee_prevUnrecoded_prevRecoded_1 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 15, 10)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 16, 16)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7
node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12)))
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2)
node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1)
node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11))
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0))
node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11)
node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2)
node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3)
node toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1)
node toint_ieee_prevUnrecoded_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1)
node _toint_ieee_prevUnrecoded_T_5 = shr(toint_ieee_prevUnrecoded_unrecoded_1, 16)
node _toint_ieee_prevUnrecoded_T_6 = bits(toint_ieee_prevRecoded_1, 31, 29)
node _toint_ieee_prevUnrecoded_T_7 = andr(_toint_ieee_prevUnrecoded_T_6)
node _toint_ieee_prevUnrecoded_T_8 = bits(toint_ieee_prevUnrecoded_unrecoded_1, 15, 0)
node _toint_ieee_prevUnrecoded_T_9 = mux(_toint_ieee_prevUnrecoded_T_7, toint_ieee_prevUnrecoded_prevUnrecoded_1, _toint_ieee_prevUnrecoded_T_8)
node toint_ieee_prevUnrecoded_1 = cat(_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9)
node _toint_ieee_T_11 = shr(toint_ieee_unrecoded_1, 32)
node _toint_ieee_T_12 = bits(in.in1, 63, 61)
node _toint_ieee_T_13 = andr(_toint_ieee_T_12)
node _toint_ieee_T_14 = bits(toint_ieee_unrecoded_1, 31, 0)
node _toint_ieee_T_15 = mux(_toint_ieee_T_13, toint_ieee_prevUnrecoded_1, _toint_ieee_T_14)
node _toint_ieee_T_16 = cat(_toint_ieee_T_11, _toint_ieee_T_15)
node _toint_ieee_T_17 = bits(_toint_ieee_T_16, 31, 0)
node _toint_ieee_T_18 = cat(_toint_ieee_T_17, _toint_ieee_T_17)
node toint_ieee_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52)
node _toint_ieee_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 9)
node toint_ieee_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 10)
node toint_ieee_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire toint_ieee_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9)
node _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isNaN_T_4)
connect toint_ieee_unrecoded_rawIn_2.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_5
node _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9)
node _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isInf_T_7)
connect toint_ieee_unrecoded_rawIn_2.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_8
connect toint_ieee_unrecoded_rawIn_2.isZero, toint_ieee_unrecoded_rawIn_isZero_2
node _toint_ieee_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64)
connect toint_ieee_unrecoded_rawIn_2.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_2
node _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_unrecoded_rawIn_exp_2)
connect toint_ieee_unrecoded_rawIn_2.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_2
node _toint_ieee_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_unrecoded_rawIn_isZero_2, UInt<1>(0h0))
node _toint_ieee_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_8)
node _toint_ieee_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0)
node _toint_ieee_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10)
connect toint_ieee_unrecoded_rawIn_2.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_11
node toint_ieee_unrecoded_isSubnormal_2 = lt(toint_ieee_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402)))
node _toint_ieee_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 5, 0)
node _toint_ieee_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_4)
node toint_ieee_unrecoded_denormShiftDist_2 = tail(_toint_ieee_unrecoded_denormShiftDist_T_5, 1)
node _toint_ieee_unrecoded_denormFract_T_4 = shr(toint_ieee_unrecoded_rawIn_2.sig, 1)
node _toint_ieee_unrecoded_denormFract_T_5 = dshr(_toint_ieee_unrecoded_denormFract_T_4, toint_ieee_unrecoded_denormShiftDist_2)
node toint_ieee_unrecoded_denormFract_2 = bits(_toint_ieee_unrecoded_denormFract_T_5, 51, 0)
node _toint_ieee_unrecoded_expOut_T_12 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 10, 0)
node _toint_ieee_unrecoded_expOut_T_13 = sub(_toint_ieee_unrecoded_expOut_T_12, UInt<11>(0h401))
node _toint_ieee_unrecoded_expOut_T_14 = tail(_toint_ieee_unrecoded_expOut_T_13, 1)
node _toint_ieee_unrecoded_expOut_T_15 = mux(toint_ieee_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_14)
node _toint_ieee_unrecoded_expOut_T_16 = or(toint_ieee_unrecoded_rawIn_2.isNaN, toint_ieee_unrecoded_rawIn_2.isInf)
node _toint_ieee_unrecoded_expOut_T_17 = mux(_toint_ieee_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0))
node toint_ieee_unrecoded_expOut_2 = or(_toint_ieee_unrecoded_expOut_T_15, _toint_ieee_unrecoded_expOut_T_17)
node _toint_ieee_unrecoded_fractOut_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sig, 51, 0)
node _toint_ieee_unrecoded_fractOut_T_5 = mux(toint_ieee_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_4)
node toint_ieee_unrecoded_fractOut_2 = mux(toint_ieee_unrecoded_isSubnormal_2, toint_ieee_unrecoded_denormFract_2, _toint_ieee_unrecoded_fractOut_T_5)
node toint_ieee_unrecoded_hi_2 = cat(toint_ieee_unrecoded_rawIn_2.sign, toint_ieee_unrecoded_expOut_2)
node toint_ieee_unrecoded_2 = cat(toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2)
node _toint_ieee_prevRecoded_T_6 = bits(in.in1, 31, 31)
node _toint_ieee_prevRecoded_T_7 = bits(in.in1, 52, 52)
node _toint_ieee_prevRecoded_T_8 = bits(in.in1, 30, 0)
node toint_ieee_prevRecoded_hi_2 = cat(_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7)
node toint_ieee_prevRecoded_2 = cat(toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(toint_ieee_prevRecoded_2, 31, 23)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7)
node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevRecoded_2, 32, 32)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevRecoded_2, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10)
connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11
node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82)))
node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0)
node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4)
node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1)
node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 1)
node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2)
node toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81))
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_13, 1)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf)
node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0))
node toint_ieee_prevUnrecoded_unrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17)
node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0)
node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4)
node toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_unrecoded_denormFract_2, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5)
node toint_ieee_prevUnrecoded_unrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2)
node toint_ieee_prevUnrecoded_unrecoded_2 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2)
node _toint_ieee_prevUnrecoded_prevRecoded_T_6 = bits(toint_ieee_prevRecoded_2, 15, 15)
node _toint_ieee_prevUnrecoded_prevRecoded_T_7 = bits(toint_ieee_prevRecoded_2, 23, 23)
node _toint_ieee_prevUnrecoded_prevRecoded_T_8 = bits(toint_ieee_prevRecoded_2, 14, 0)
node toint_ieee_prevUnrecoded_prevRecoded_hi_2 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7)
node toint_ieee_prevUnrecoded_prevRecoded_2 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 15, 10)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4)
node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 16, 16)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0))
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10)
connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11
node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12)))
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4)
node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2)
node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11))
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13, 1)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf)
node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0))
node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17)
node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0)
node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4)
node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5)
node toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2)
node toint_ieee_prevUnrecoded_prevUnrecoded_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2)
node _toint_ieee_prevUnrecoded_T_10 = shr(toint_ieee_prevUnrecoded_unrecoded_2, 16)
node _toint_ieee_prevUnrecoded_T_11 = bits(toint_ieee_prevRecoded_2, 31, 29)
node _toint_ieee_prevUnrecoded_T_12 = andr(_toint_ieee_prevUnrecoded_T_11)
node _toint_ieee_prevUnrecoded_T_13 = bits(toint_ieee_prevUnrecoded_unrecoded_2, 15, 0)
node _toint_ieee_prevUnrecoded_T_14 = mux(_toint_ieee_prevUnrecoded_T_12, toint_ieee_prevUnrecoded_prevUnrecoded_2, _toint_ieee_prevUnrecoded_T_13)
node toint_ieee_prevUnrecoded_2 = cat(_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14)
node _toint_ieee_T_19 = shr(toint_ieee_unrecoded_2, 32)
node _toint_ieee_T_20 = bits(in.in1, 63, 61)
node _toint_ieee_T_21 = andr(_toint_ieee_T_20)
node _toint_ieee_T_22 = bits(toint_ieee_unrecoded_2, 31, 0)
node _toint_ieee_T_23 = mux(_toint_ieee_T_21, toint_ieee_prevUnrecoded_2, _toint_ieee_T_22)
node _toint_ieee_T_24 = cat(_toint_ieee_T_19, _toint_ieee_T_23)
node _toint_ieee_T_25 = bits(_toint_ieee_T_24, 63, 0)
node _toint_ieee_T_26 = eq(in.typeTagOut, UInt<1>(0h1))
node _toint_ieee_T_27 = mux(_toint_ieee_T_26, _toint_ieee_T_18, _toint_ieee_T_10)
node _toint_ieee_T_28 = eq(in.typeTagOut, UInt<2>(0h2))
node _toint_ieee_T_29 = mux(_toint_ieee_T_28, _toint_ieee_T_25, _toint_ieee_T_27)
node _toint_ieee_T_30 = eq(in.typeTagOut, UInt<2>(0h3))
node toint_ieee = mux(_toint_ieee_T_30, _toint_ieee_T_25, _toint_ieee_T_29)
wire toint : UInt
connect toint, toint_ieee
node _intType_T = bits(in.fmt, 0, 0)
wire intType : UInt<1>
connect intType, _intType_T
node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52)
node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9)
node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10)
node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9)
node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T)
connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9)
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1)
connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2
connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero
node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64)
connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T
node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp)
connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T
node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T)
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0)
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2)
connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3
node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402)))
node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0)
node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T)
node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1)
node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1)
node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist)
node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0)
node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0)
node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401))
node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1)
node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2)
node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf)
node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0))
node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5)
node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0)
node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T)
node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1)
node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut)
node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut)
node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31)
node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52)
node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0)
node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1)
node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 6)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 7)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3
node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T)
node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist)
node io_out_bits_store_prevUnrecoded_unrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81))
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node io_out_bits_store_prevUnrecoded_unrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5)
node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T)
node io_out_bits_store_prevUnrecoded_unrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_unrecoded_denormFract, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1)
node io_out_bits_store_prevUnrecoded_unrecoded_hi = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut)
node io_out_bits_store_prevUnrecoded_unrecoded = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T = bits(io_out_bits_store_prevRecoded, 15, 15)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = bits(io_out_bits_store_prevRecoded, 23, 23)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = bits(io_out_bits_store_prevRecoded, 14, 0)
node io_out_bits_store_prevUnrecoded_prevRecoded_hi = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1)
node io_out_bits_store_prevUnrecoded_prevRecoded = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 15, 10)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 16, 16)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3
node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12)))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0))
node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut)
node io_out_bits_store_prevUnrecoded_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut)
node _io_out_bits_store_prevUnrecoded_T = shr(io_out_bits_store_prevUnrecoded_unrecoded, 16)
node _io_out_bits_store_prevUnrecoded_T_1 = bits(io_out_bits_store_prevRecoded, 31, 29)
node _io_out_bits_store_prevUnrecoded_T_2 = andr(_io_out_bits_store_prevUnrecoded_T_1)
node _io_out_bits_store_prevUnrecoded_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded, 15, 0)
node _io_out_bits_store_prevUnrecoded_T_4 = mux(_io_out_bits_store_prevUnrecoded_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded, _io_out_bits_store_prevUnrecoded_T_3)
node io_out_bits_store_prevUnrecoded = cat(_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4)
node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32)
node _io_out_bits_store_T_1 = bits(in.in1, 63, 61)
node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1)
node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0)
node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3)
node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4)
node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 15, 0)
node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6)
node _io_out_bits_store_T_8 = cat(_io_out_bits_store_T_7, _io_out_bits_store_T_7)
node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52)
node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9)
node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10)
node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9)
node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2)
connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9)
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4)
connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5
connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1
node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64)
connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1
node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1)
connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4)
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0)
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6)
connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7
node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402)))
node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0)
node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2)
node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1)
node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1)
node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1)
node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0)
node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0)
node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401))
node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1)
node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8)
node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf)
node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0))
node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11)
node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0)
node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2)
node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3)
node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1)
node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1)
node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31)
node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52)
node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0)
node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4)
node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7
node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82)))
node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2)
node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1)
node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81))
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0))
node io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11)
node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2)
node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3)
node io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1)
node io_out_bits_store_prevUnrecoded_unrecoded_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = bits(io_out_bits_store_prevRecoded_1, 15, 15)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = bits(io_out_bits_store_prevRecoded_1, 23, 23)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = bits(io_out_bits_store_prevRecoded_1, 14, 0)
node io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4)
node io_out_bits_store_prevUnrecoded_prevRecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 15, 10)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3))
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 16, 16)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7
node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12)))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0))
node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1)
node _io_out_bits_store_prevUnrecoded_T_5 = shr(io_out_bits_store_prevUnrecoded_unrecoded_1, 16)
node _io_out_bits_store_prevUnrecoded_T_6 = bits(io_out_bits_store_prevRecoded_1, 31, 29)
node _io_out_bits_store_prevUnrecoded_T_7 = andr(_io_out_bits_store_prevUnrecoded_T_6)
node _io_out_bits_store_prevUnrecoded_T_8 = bits(io_out_bits_store_prevUnrecoded_unrecoded_1, 15, 0)
node _io_out_bits_store_prevUnrecoded_T_9 = mux(_io_out_bits_store_prevUnrecoded_T_7, io_out_bits_store_prevUnrecoded_prevUnrecoded_1, _io_out_bits_store_prevUnrecoded_T_8)
node io_out_bits_store_prevUnrecoded_1 = cat(_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9)
node _io_out_bits_store_T_9 = shr(io_out_bits_store_unrecoded_1, 32)
node _io_out_bits_store_T_10 = bits(in.in1, 63, 61)
node _io_out_bits_store_T_11 = andr(_io_out_bits_store_T_10)
node _io_out_bits_store_T_12 = bits(io_out_bits_store_unrecoded_1, 31, 0)
node _io_out_bits_store_T_13 = mux(_io_out_bits_store_T_11, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_12)
node _io_out_bits_store_T_14 = cat(_io_out_bits_store_T_9, _io_out_bits_store_T_13)
node _io_out_bits_store_T_15 = bits(_io_out_bits_store_T_14, 31, 0)
node _io_out_bits_store_T_16 = cat(_io_out_bits_store_T_15, _io_out_bits_store_T_15)
node io_out_bits_store_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52)
node _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 9)
node io_out_bits_store_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 10)
node io_out_bits_store_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire io_out_bits_store_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}
node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9)
node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4)
connect io_out_bits_store_unrecoded_rawIn_2.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9)
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7)
connect io_out_bits_store_unrecoded_rawIn_2.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8
connect io_out_bits_store_unrecoded_rawIn_2.isZero, io_out_bits_store_unrecoded_rawIn_isZero_2
node _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64)
connect io_out_bits_store_unrecoded_rawIn_2.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_2
node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_unrecoded_rawIn_exp_2)
connect io_out_bits_store_unrecoded_rawIn_2.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_unrecoded_rawIn_isZero_2, UInt<1>(0h0))
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_8)
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0)
node _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10)
connect io_out_bits_store_unrecoded_rawIn_2.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_11
node io_out_bits_store_unrecoded_isSubnormal_2 = lt(io_out_bits_store_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402)))
node _io_out_bits_store_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 5, 0)
node _io_out_bits_store_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_4)
node io_out_bits_store_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_5, 1)
node _io_out_bits_store_unrecoded_denormFract_T_4 = shr(io_out_bits_store_unrecoded_rawIn_2.sig, 1)
node _io_out_bits_store_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_unrecoded_denormFract_T_4, io_out_bits_store_unrecoded_denormShiftDist_2)
node io_out_bits_store_unrecoded_denormFract_2 = bits(_io_out_bits_store_unrecoded_denormFract_T_5, 51, 0)
node _io_out_bits_store_unrecoded_expOut_T_12 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 10, 0)
node _io_out_bits_store_unrecoded_expOut_T_13 = sub(_io_out_bits_store_unrecoded_expOut_T_12, UInt<11>(0h401))
node _io_out_bits_store_unrecoded_expOut_T_14 = tail(_io_out_bits_store_unrecoded_expOut_T_13, 1)
node _io_out_bits_store_unrecoded_expOut_T_15 = mux(io_out_bits_store_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_14)
node _io_out_bits_store_unrecoded_expOut_T_16 = or(io_out_bits_store_unrecoded_rawIn_2.isNaN, io_out_bits_store_unrecoded_rawIn_2.isInf)
node _io_out_bits_store_unrecoded_expOut_T_17 = mux(_io_out_bits_store_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0))
node io_out_bits_store_unrecoded_expOut_2 = or(_io_out_bits_store_unrecoded_expOut_T_15, _io_out_bits_store_unrecoded_expOut_T_17)
node _io_out_bits_store_unrecoded_fractOut_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sig, 51, 0)
node _io_out_bits_store_unrecoded_fractOut_T_5 = mux(io_out_bits_store_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_4)
node io_out_bits_store_unrecoded_fractOut_2 = mux(io_out_bits_store_unrecoded_isSubnormal_2, io_out_bits_store_unrecoded_denormFract_2, _io_out_bits_store_unrecoded_fractOut_T_5)
node io_out_bits_store_unrecoded_hi_2 = cat(io_out_bits_store_unrecoded_rawIn_2.sign, io_out_bits_store_unrecoded_expOut_2)
node io_out_bits_store_unrecoded_2 = cat(io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2)
node _io_out_bits_store_prevRecoded_T_6 = bits(in.in1, 31, 31)
node _io_out_bits_store_prevRecoded_T_7 = bits(in.in1, 52, 52)
node _io_out_bits_store_prevRecoded_T_8 = bits(in.in1, 30, 0)
node io_out_bits_store_prevRecoded_hi_2 = cat(_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7)
node io_out_bits_store_prevRecoded_2 = cat(io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevRecoded_2, 31, 23)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7)
node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevRecoded_2, 32, 32)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevRecoded_2, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10)
connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11
node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82)))
node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4)
node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2)
node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81))
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13, 1)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf)
node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0))
node io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17)
node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0)
node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4)
node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5)
node io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2)
node io_out_bits_store_prevUnrecoded_unrecoded_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = bits(io_out_bits_store_prevRecoded_2, 15, 15)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = bits(io_out_bits_store_prevRecoded_2, 23, 23)
node _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = bits(io_out_bits_store_prevRecoded_2, 14, 0)
node io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7)
node io_out_bits_store_prevUnrecoded_prevRecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 15, 10)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3))
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 16, 16)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10)
connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11
node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12)))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11))
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13, 1)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0))
node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0)
node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2)
node io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2)
node _io_out_bits_store_prevUnrecoded_T_10 = shr(io_out_bits_store_prevUnrecoded_unrecoded_2, 16)
node _io_out_bits_store_prevUnrecoded_T_11 = bits(io_out_bits_store_prevRecoded_2, 31, 29)
node _io_out_bits_store_prevUnrecoded_T_12 = andr(_io_out_bits_store_prevUnrecoded_T_11)
node _io_out_bits_store_prevUnrecoded_T_13 = bits(io_out_bits_store_prevUnrecoded_unrecoded_2, 15, 0)
node _io_out_bits_store_prevUnrecoded_T_14 = mux(_io_out_bits_store_prevUnrecoded_T_12, io_out_bits_store_prevUnrecoded_prevUnrecoded_2, _io_out_bits_store_prevUnrecoded_T_13)
node io_out_bits_store_prevUnrecoded_2 = cat(_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14)
node _io_out_bits_store_T_17 = shr(io_out_bits_store_unrecoded_2, 32)
node _io_out_bits_store_T_18 = bits(in.in1, 63, 61)
node _io_out_bits_store_T_19 = andr(_io_out_bits_store_T_18)
node _io_out_bits_store_T_20 = bits(io_out_bits_store_unrecoded_2, 31, 0)
node _io_out_bits_store_T_21 = mux(_io_out_bits_store_T_19, io_out_bits_store_prevUnrecoded_2, _io_out_bits_store_T_20)
node _io_out_bits_store_T_22 = cat(_io_out_bits_store_T_17, _io_out_bits_store_T_21)
node _io_out_bits_store_T_23 = bits(_io_out_bits_store_T_22, 63, 0)
node _io_out_bits_store_T_24 = eq(in.typeTagOut, UInt<1>(0h1))
node _io_out_bits_store_T_25 = mux(_io_out_bits_store_T_24, _io_out_bits_store_T_16, _io_out_bits_store_T_8)
node _io_out_bits_store_T_26 = eq(in.typeTagOut, UInt<2>(0h2))
node _io_out_bits_store_T_27 = mux(_io_out_bits_store_T_26, _io_out_bits_store_T_23, _io_out_bits_store_T_25)
node _io_out_bits_store_T_28 = eq(in.typeTagOut, UInt<2>(0h3))
node _io_out_bits_store_T_29 = mux(_io_out_bits_store_T_28, _io_out_bits_store_T_23, _io_out_bits_store_T_27)
connect io.out.bits.store, _io_out_bits_store_T_29
node _io_out_bits_toint_T = bits(toint, 31, 0)
node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31)
node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T)
node _io_out_bits_toint_T_4 = bits(toint, 63, 0)
node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1))
node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3)
connect io.out.bits.toint, _io_out_bits_toint_T_6
connect io.out.bits.exc, UInt<1>(0h0)
node _T = bits(in.rm, 0, 0)
when _T :
node classify_out_sign = bits(in.in1, 64, 64)
node classify_out_fractIn = bits(in.in1, 51, 0)
node classify_out_expIn = bits(in.in1, 63, 52)
node _classify_out_fractOut_T = shl(classify_out_fractIn, 11)
node classify_out_fractOut = shr(_classify_out_fractOut_T, 53)
node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9)
node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<6>(0h20))
node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1)
node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800))
node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1)
node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0))
node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6))
node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1)
node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 2, 0)
node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3)
node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 5, 0)
node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5)
node classify_out_hi = cat(classify_out_sign, classify_out_expOut)
node _classify_out_T = cat(classify_out_hi, classify_out_fractOut)
node classify_out_sign_1 = bits(_classify_out_T, 16, 16)
node classify_out_code = bits(_classify_out_T, 15, 13)
node classify_out_codeHi = bits(classify_out_code, 2, 1)
node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3))
node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 13, 10)
node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2))
node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1))
node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1))
node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn)
node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2)
node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1))
node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0))
node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1)
node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2))
node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3)
node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0))
node _classify_out_isInf_T = bits(classify_out_code, 0, 0)
node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0))
node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1)
node classify_out_isNaN = andr(classify_out_code)
node _classify_out_isSNaN_T = bits(_classify_out_T, 9, 9)
node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0))
node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1)
node _classify_out_isQNaN_T = bits(_classify_out_T, 9, 9)
node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T)
node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0))
node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1)
node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0))
node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3)
node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0))
node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5)
node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0))
node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7)
node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1)
node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1)
node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1)
node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1)
node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12)
node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9)
node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10)
node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo)
node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6)
node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN)
node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2)
node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo)
node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo)
node classify_out_sign_2 = bits(in.in1, 64, 64)
node classify_out_fractIn_1 = bits(in.in1, 51, 0)
node classify_out_expIn_1 = bits(in.in1, 63, 52)
node _classify_out_fractOut_T_1 = shl(classify_out_fractIn_1, 24)
node classify_out_fractOut_1 = shr(_classify_out_fractOut_T_1, 53)
node classify_out_expOut_expCode_1 = bits(classify_out_expIn_1, 11, 9)
node _classify_out_expOut_commonCase_T_3 = add(classify_out_expIn_1, UInt<9>(0h100))
node _classify_out_expOut_commonCase_T_4 = tail(_classify_out_expOut_commonCase_T_3, 1)
node _classify_out_expOut_commonCase_T_5 = sub(_classify_out_expOut_commonCase_T_4, UInt<12>(0h800))
node classify_out_expOut_commonCase_1 = tail(_classify_out_expOut_commonCase_T_5, 1)
node _classify_out_expOut_T_6 = eq(classify_out_expOut_expCode_1, UInt<1>(0h0))
node _classify_out_expOut_T_7 = geq(classify_out_expOut_expCode_1, UInt<3>(0h6))
node _classify_out_expOut_T_8 = or(_classify_out_expOut_T_6, _classify_out_expOut_T_7)
node _classify_out_expOut_T_9 = bits(classify_out_expOut_commonCase_1, 5, 0)
node _classify_out_expOut_T_10 = cat(classify_out_expOut_expCode_1, _classify_out_expOut_T_9)
node _classify_out_expOut_T_11 = bits(classify_out_expOut_commonCase_1, 8, 0)
node classify_out_expOut_1 = mux(_classify_out_expOut_T_8, _classify_out_expOut_T_10, _classify_out_expOut_T_11)
node classify_out_hi_2 = cat(classify_out_sign_2, classify_out_expOut_1)
node _classify_out_T_14 = cat(classify_out_hi_2, classify_out_fractOut_1)
node classify_out_sign_3 = bits(_classify_out_T_14, 32, 32)
node classify_out_code_1 = bits(_classify_out_T_14, 31, 29)
node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1)
node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3))
node _classify_out_isHighSubnormalIn_T_1 = bits(_classify_out_T_14, 29, 23)
node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2))
node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1))
node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1))
node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1)
node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5)
node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1))
node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0))
node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5)
node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2))
node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7)
node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0))
node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0)
node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0))
node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3)
node classify_out_isNaN_1 = andr(classify_out_code_1)
node _classify_out_isSNaN_T_2 = bits(_classify_out_T_14, 22, 22)
node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0))
node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3)
node _classify_out_isQNaN_T_1 = bits(_classify_out_T_14, 22, 22)
node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1)
node _classify_out_T_15 = eq(classify_out_sign_3, UInt<1>(0h0))
node _classify_out_T_16 = and(classify_out_isInf_1, _classify_out_T_15)
node _classify_out_T_17 = eq(classify_out_sign_3, UInt<1>(0h0))
node _classify_out_T_18 = and(classify_out_isNormal_1, _classify_out_T_17)
node _classify_out_T_19 = eq(classify_out_sign_3, UInt<1>(0h0))
node _classify_out_T_20 = and(classify_out_isSubnormal_1, _classify_out_T_19)
node _classify_out_T_21 = eq(classify_out_sign_3, UInt<1>(0h0))
node _classify_out_T_22 = and(classify_out_isZero_1, _classify_out_T_21)
node _classify_out_T_23 = and(classify_out_isZero_1, classify_out_sign_3)
node _classify_out_T_24 = and(classify_out_isSubnormal_1, classify_out_sign_3)
node _classify_out_T_25 = and(classify_out_isNormal_1, classify_out_sign_3)
node _classify_out_T_26 = and(classify_out_isInf_1, classify_out_sign_3)
node classify_out_lo_lo_1 = cat(_classify_out_T_25, _classify_out_T_26)
node classify_out_lo_hi_hi_1 = cat(_classify_out_T_22, _classify_out_T_23)
node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_24)
node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1)
node classify_out_hi_lo_1 = cat(_classify_out_T_18, _classify_out_T_20)
node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1)
node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_16)
node classify_out_hi_3 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1)
node _classify_out_T_27 = cat(classify_out_hi_3, classify_out_lo_1)
node classify_out_sign_4 = bits(in.in1, 64, 64)
node classify_out_code_2 = bits(in.in1, 63, 61)
node classify_out_codeHi_2 = bits(classify_out_code_2, 2, 1)
node classify_out_isSpecial_2 = eq(classify_out_codeHi_2, UInt<2>(0h3))
node _classify_out_isHighSubnormalIn_T_2 = bits(in.in1, 61, 52)
node classify_out_isHighSubnormalIn_2 = lt(_classify_out_isHighSubnormalIn_T_2, UInt<2>(0h2))
node _classify_out_isSubnormal_T_6 = eq(classify_out_code_2, UInt<1>(0h1))
node _classify_out_isSubnormal_T_7 = eq(classify_out_codeHi_2, UInt<1>(0h1))
node _classify_out_isSubnormal_T_8 = and(_classify_out_isSubnormal_T_7, classify_out_isHighSubnormalIn_2)
node classify_out_isSubnormal_2 = or(_classify_out_isSubnormal_T_6, _classify_out_isSubnormal_T_8)
node _classify_out_isNormal_T_8 = eq(classify_out_codeHi_2, UInt<1>(0h1))
node _classify_out_isNormal_T_9 = eq(classify_out_isHighSubnormalIn_2, UInt<1>(0h0))
node _classify_out_isNormal_T_10 = and(_classify_out_isNormal_T_8, _classify_out_isNormal_T_9)
node _classify_out_isNormal_T_11 = eq(classify_out_codeHi_2, UInt<2>(0h2))
node classify_out_isNormal_2 = or(_classify_out_isNormal_T_10, _classify_out_isNormal_T_11)
node classify_out_isZero_2 = eq(classify_out_code_2, UInt<1>(0h0))
node _classify_out_isInf_T_4 = bits(classify_out_code_2, 0, 0)
node _classify_out_isInf_T_5 = eq(_classify_out_isInf_T_4, UInt<1>(0h0))
node classify_out_isInf_2 = and(classify_out_isSpecial_2, _classify_out_isInf_T_5)
node classify_out_isNaN_2 = andr(classify_out_code_2)
node _classify_out_isSNaN_T_4 = bits(in.in1, 51, 51)
node _classify_out_isSNaN_T_5 = eq(_classify_out_isSNaN_T_4, UInt<1>(0h0))
node classify_out_isSNaN_2 = and(classify_out_isNaN_2, _classify_out_isSNaN_T_5)
node _classify_out_isQNaN_T_2 = bits(in.in1, 51, 51)
node classify_out_isQNaN_2 = and(classify_out_isNaN_2, _classify_out_isQNaN_T_2)
node _classify_out_T_28 = eq(classify_out_sign_4, UInt<1>(0h0))
node _classify_out_T_29 = and(classify_out_isInf_2, _classify_out_T_28)
node _classify_out_T_30 = eq(classify_out_sign_4, UInt<1>(0h0))
node _classify_out_T_31 = and(classify_out_isNormal_2, _classify_out_T_30)
node _classify_out_T_32 = eq(classify_out_sign_4, UInt<1>(0h0))
node _classify_out_T_33 = and(classify_out_isSubnormal_2, _classify_out_T_32)
node _classify_out_T_34 = eq(classify_out_sign_4, UInt<1>(0h0))
node _classify_out_T_35 = and(classify_out_isZero_2, _classify_out_T_34)
node _classify_out_T_36 = and(classify_out_isZero_2, classify_out_sign_4)
node _classify_out_T_37 = and(classify_out_isSubnormal_2, classify_out_sign_4)
node _classify_out_T_38 = and(classify_out_isNormal_2, classify_out_sign_4)
node _classify_out_T_39 = and(classify_out_isInf_2, classify_out_sign_4)
node classify_out_lo_lo_2 = cat(_classify_out_T_38, _classify_out_T_39)
node classify_out_lo_hi_hi_2 = cat(_classify_out_T_35, _classify_out_T_36)
node classify_out_lo_hi_2 = cat(classify_out_lo_hi_hi_2, _classify_out_T_37)
node classify_out_lo_2 = cat(classify_out_lo_hi_2, classify_out_lo_lo_2)
node classify_out_hi_lo_2 = cat(_classify_out_T_31, _classify_out_T_33)
node classify_out_hi_hi_hi_2 = cat(classify_out_isQNaN_2, classify_out_isSNaN_2)
node classify_out_hi_hi_2 = cat(classify_out_hi_hi_hi_2, _classify_out_T_29)
node classify_out_hi_4 = cat(classify_out_hi_hi_2, classify_out_hi_lo_2)
node _classify_out_T_40 = cat(classify_out_hi_4, classify_out_lo_2)
node _classify_out_T_41 = eq(in.typeTagOut, UInt<1>(0h1))
node _classify_out_T_42 = mux(_classify_out_T_41, _classify_out_T_27, _classify_out_T_13)
node _classify_out_T_43 = eq(in.typeTagOut, UInt<2>(0h2))
node _classify_out_T_44 = mux(_classify_out_T_43, _classify_out_T_40, _classify_out_T_42)
node _classify_out_T_45 = eq(in.typeTagOut, UInt<2>(0h3))
node classify_out = mux(_classify_out_T_45, _classify_out_T_40, _classify_out_T_44)
node _toint_T = shr(toint_ieee, 32)
node _toint_T_1 = shl(_toint_T, 32)
node _toint_T_2 = or(classify_out, _toint_T_1)
connect toint, _toint_T_2
connect intType, UInt<1>(0h0)
when in.wflags :
node _toint_T_3 = not(in.rm)
node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq)
node _toint_T_5 = and(_toint_T_3, _toint_T_4)
node _toint_T_6 = orr(_toint_T_5)
node _toint_T_7 = shr(toint_ieee, 32)
node _toint_T_8 = shl(_toint_T_7, 32)
node _toint_T_9 = or(_toint_T_6, _toint_T_8)
connect toint, _toint_T_9
connect io.out.bits.exc, dcmp.io.exceptionFlags
connect intType, UInt<1>(0h0)
node _T_1 = eq(in.ren2, UInt<1>(0h0))
when _T_1 :
node cvtType = bits(in.typ, 1, 1)
connect intType, cvtType
inst conv of RecFNToIN_e11_s53_i64_1
connect conv.clock, clock
connect conv.reset, reset
connect conv.io.in, in.in1
connect conv.io.roundingMode, in.rm
node _conv_io_signedOut_T = bits(in.typ, 0, 0)
node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T)
connect conv.io.signedOut, _conv_io_signedOut_T_1
connect toint, conv.io.out
node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1)
node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T)
node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0)
node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0))
node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2)
connect io.out.bits.exc, _io_out_bits_exc_T_3
node _T_2 = eq(cvtType, UInt<1>(0h0))
when _T_2 :
inst narrow of RecFNToIN_e11_s53_i32_1
connect narrow.clock, clock
connect narrow.reset, reset
connect narrow.io.in, in.in1
connect narrow.io.roundingMode, in.rm
node _narrow_io_signedOut_T = bits(in.typ, 0, 0)
node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T)
connect narrow.io.signedOut, _narrow_io_signedOut_T_1
node _excSign_T = bits(in.in1, 64, 64)
node _excSign_T_1 = bits(in.in1, 63, 61)
node _excSign_T_2 = andr(_excSign_T_1)
node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0))
node excSign = and(_excSign_T, _excSign_T_3)
node _excOut_T = eq(conv.io.signedOut, excSign)
node _excOut_T_1 = eq(excSign, UInt<1>(0h0))
node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0))
node excOut = cat(_excOut_T, _excOut_T_2)
node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2)
node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1)
node invalid = or(_invalid_T, _invalid_T_1)
when invalid :
node _toint_T_10 = shr(conv.io.out, 32)
node _toint_T_11 = cat(_toint_T_10, excOut)
connect toint, _toint_T_11
node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0))
node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0)
node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5)
node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0))
node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6)
connect io.out.bits.exc, _io_out_bits_exc_T_7
connect io.out.valid, valid
node _io_out_bits_lt_T = asSInt(dcmp.io.a)
node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0)))
node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b)
node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0)))
node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3)
node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4)
connect io.out.bits.lt, _io_out_bits_lt_T_5
connect io.out.bits.in, in | module FPToInt_1( // @[FPU.scala:453:7]
input clock, // @[FPU.scala:453:7]
input reset, // @[FPU.scala:453:7]
input io_in_valid, // @[FPU.scala:461:14]
input io_in_bits_ldst, // @[FPU.scala:461:14]
input io_in_bits_wen, // @[FPU.scala:461:14]
input io_in_bits_ren1, // @[FPU.scala:461:14]
input io_in_bits_ren2, // @[FPU.scala:461:14]
input io_in_bits_ren3, // @[FPU.scala:461:14]
input io_in_bits_swap12, // @[FPU.scala:461:14]
input io_in_bits_swap23, // @[FPU.scala:461:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14]
input io_in_bits_fromint, // @[FPU.scala:461:14]
input io_in_bits_toint, // @[FPU.scala:461:14]
input io_in_bits_fastpipe, // @[FPU.scala:461:14]
input io_in_bits_fma, // @[FPU.scala:461:14]
input io_in_bits_div, // @[FPU.scala:461:14]
input io_in_bits_sqrt, // @[FPU.scala:461:14]
input io_in_bits_wflags, // @[FPU.scala:461:14]
input io_in_bits_vec, // @[FPU.scala:461:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:461:14]
input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:461:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:461:14]
input [1:0] io_in_bits_fmt, // @[FPU.scala:461:14]
input [64:0] io_in_bits_in1, // @[FPU.scala:461:14]
input [64:0] io_in_bits_in2, // @[FPU.scala:461:14]
input [64:0] io_in_bits_in3, // @[FPU.scala:461:14]
output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14]
output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14]
output [64:0] io_out_bits_in_in2, // @[FPU.scala:461:14]
output io_out_bits_lt, // @[FPU.scala:461:14]
output [63:0] io_out_bits_store, // @[FPU.scala:461:14]
output [63:0] io_out_bits_toint, // @[FPU.scala:461:14]
output [4:0] io_out_bits_exc // @[FPU.scala:461:14]
);
wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30]
wire [63:0] _conv_io_out; // @[FPU.scala:498:24]
wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24]
wire _dcmp_io_lt; // @[FPU.scala:469:20]
wire _dcmp_io_eq; // @[FPU.scala:469:20]
wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7]
wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:453:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7]
wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:453:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7]
wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:453:7]
wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7]
wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7]
wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:453:7]
wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32]
wire [63:0] _io_out_bits_store_T_29; // @[package.scala:39:76]
wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76]
wire io_out_bits_in_ldst; // @[FPU.scala:453:7]
wire io_out_bits_in_wen; // @[FPU.scala:453:7]
wire io_out_bits_in_ren1; // @[FPU.scala:453:7]
wire io_out_bits_in_ren2; // @[FPU.scala:453:7]
wire io_out_bits_in_ren3; // @[FPU.scala:453:7]
wire io_out_bits_in_swap12; // @[FPU.scala:453:7]
wire io_out_bits_in_swap23; // @[FPU.scala:453:7]
wire [1:0] io_out_bits_in_typeTagIn; // @[FPU.scala:453:7]
wire [1:0] io_out_bits_in_typeTagOut; // @[FPU.scala:453:7]
wire io_out_bits_in_fromint; // @[FPU.scala:453:7]
wire io_out_bits_in_toint; // @[FPU.scala:453:7]
wire io_out_bits_in_fastpipe; // @[FPU.scala:453:7]
wire io_out_bits_in_fma; // @[FPU.scala:453:7]
wire io_out_bits_in_div; // @[FPU.scala:453:7]
wire io_out_bits_in_sqrt; // @[FPU.scala:453:7]
wire io_out_bits_in_wflags; // @[FPU.scala:453:7]
wire io_out_bits_in_vec; // @[FPU.scala:453:7]
wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7]
wire [1:0] io_out_bits_in_fmaCmd; // @[FPU.scala:453:7]
wire [1:0] io_out_bits_in_typ; // @[FPU.scala:453:7]
wire [1:0] io_out_bits_in_fmt; // @[FPU.scala:453:7]
wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7]
wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7]
wire [64:0] io_out_bits_in_in3; // @[FPU.scala:453:7]
wire io_out_bits_lt_0; // @[FPU.scala:453:7]
wire [63:0] io_out_bits_store_0; // @[FPU.scala:453:7]
wire [63:0] io_out_bits_toint_0; // @[FPU.scala:453:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:453:7]
wire io_out_valid; // @[FPU.scala:453:7]
reg in_ldst; // @[FPU.scala:466:21]
assign io_out_bits_in_ldst = in_ldst; // @[FPU.scala:453:7, :466:21]
reg in_wen; // @[FPU.scala:466:21]
assign io_out_bits_in_wen = in_wen; // @[FPU.scala:453:7, :466:21]
reg in_ren1; // @[FPU.scala:466:21]
assign io_out_bits_in_ren1 = in_ren1; // @[FPU.scala:453:7, :466:21]
reg in_ren2; // @[FPU.scala:466:21]
assign io_out_bits_in_ren2 = in_ren2; // @[FPU.scala:453:7, :466:21]
reg in_ren3; // @[FPU.scala:466:21]
assign io_out_bits_in_ren3 = in_ren3; // @[FPU.scala:453:7, :466:21]
reg in_swap12; // @[FPU.scala:466:21]
assign io_out_bits_in_swap12 = in_swap12; // @[FPU.scala:453:7, :466:21]
reg in_swap23; // @[FPU.scala:466:21]
assign io_out_bits_in_swap23 = in_swap23; // @[FPU.scala:453:7, :466:21]
reg [1:0] in_typeTagIn; // @[FPU.scala:466:21]
assign io_out_bits_in_typeTagIn = in_typeTagIn; // @[FPU.scala:453:7, :466:21]
reg [1:0] in_typeTagOut; // @[FPU.scala:466:21]
assign io_out_bits_in_typeTagOut = in_typeTagOut; // @[FPU.scala:453:7, :466:21]
reg in_fromint; // @[FPU.scala:466:21]
assign io_out_bits_in_fromint = in_fromint; // @[FPU.scala:453:7, :466:21]
reg in_toint; // @[FPU.scala:466:21]
assign io_out_bits_in_toint = in_toint; // @[FPU.scala:453:7, :466:21]
reg in_fastpipe; // @[FPU.scala:466:21]
assign io_out_bits_in_fastpipe = in_fastpipe; // @[FPU.scala:453:7, :466:21]
reg in_fma; // @[FPU.scala:466:21]
assign io_out_bits_in_fma = in_fma; // @[FPU.scala:453:7, :466:21]
reg in_div; // @[FPU.scala:466:21]
assign io_out_bits_in_div = in_div; // @[FPU.scala:453:7, :466:21]
reg in_sqrt; // @[FPU.scala:466:21]
assign io_out_bits_in_sqrt = in_sqrt; // @[FPU.scala:453:7, :466:21]
reg in_wflags; // @[FPU.scala:466:21]
assign io_out_bits_in_wflags = in_wflags; // @[FPU.scala:453:7, :466:21]
reg in_vec; // @[FPU.scala:466:21]
assign io_out_bits_in_vec = in_vec; // @[FPU.scala:453:7, :466:21]
reg [2:0] in_rm; // @[FPU.scala:466:21]
assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21]
reg [1:0] in_fmaCmd; // @[FPU.scala:466:21]
assign io_out_bits_in_fmaCmd = in_fmaCmd; // @[FPU.scala:453:7, :466:21]
reg [1:0] in_typ; // @[FPU.scala:466:21]
assign io_out_bits_in_typ = in_typ; // @[FPU.scala:453:7, :466:21]
reg [1:0] in_fmt; // @[FPU.scala:466:21]
assign io_out_bits_in_fmt = in_fmt; // @[FPU.scala:453:7, :466:21]
reg [64:0] in_in1; // @[FPU.scala:466:21]
assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21]
wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46]
reg [64:0] in_in2; // @[FPU.scala:466:21]
assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21]
wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72]
reg [64:0] in_in3; // @[FPU.scala:466:21]
assign io_out_bits_in_in3 = in_in3; // @[FPU.scala:453:7, :466:21]
reg valid; // @[FPU.scala:467:22]
assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22]
wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30]
wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}]
wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21]
wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21]
wire [11:0] toint_ieee_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21]
wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21]
wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21]
wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21]
wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21]
wire [11:0] classify_out_expIn_1 = in_in1[63:52]; // @[FPU.scala:276:18, :466:21]
wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21]
wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21]
wire _toint_ieee_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21]
wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21]
wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21]
wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21]
wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21]
wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:274:17, :466:21]
wire classify_out_sign_4 = in_in1[64]; // @[FPU.scala:253:17, :466:21]
wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31]
assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21]
wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21]
wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21]
wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21]
wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21]
wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21]
wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21]
wire [51:0] classify_out_fractIn_1 = in_in1[51:0]; // @[FPU.scala:275:20, :466:21]
assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN | toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 | _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21]
wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21]
wire _toint_ieee_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21]
wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21]
wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21]
wire _io_out_bits_store_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21]
wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21]
wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21]
wire _toint_ieee_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21]
wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21]
wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21]
wire _io_out_bits_store_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21]
wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21]
wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21]
wire [30:0] _toint_ieee_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21]
wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21]
wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21]
wire [30:0] _io_out_bits_store_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21]
wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28]
wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? toint_ieee_prevUnrecoded_unrecoded_denormFract : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi = {toint_ieee_prevUnrecoded_unrecoded_rawIn_sign, toint_ieee_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] toint_ieee_prevUnrecoded_unrecoded = {toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _toint_ieee_prevUnrecoded_prevRecoded_T = toint_ieee_prevRecoded[15]; // @[FPU.scala:441:28, :442:10]
wire _toint_ieee_prevUnrecoded_prevRecoded_T_1 = toint_ieee_prevRecoded[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_2 = toint_ieee_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi = {_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] toint_ieee_prevUnrecoded_prevRecoded = {toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = toint_ieee_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28]
wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded = {toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _toint_ieee_prevUnrecoded_T = toint_ieee_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21]
wire [2:0] _toint_ieee_prevUnrecoded_T_1 = toint_ieee_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28]
wire _toint_ieee_prevUnrecoded_T_2 = &_toint_ieee_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}]
wire [15:0] _toint_ieee_prevUnrecoded_T_3 = toint_ieee_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81]
wire [15:0] _toint_ieee_prevUnrecoded_T_4 = _toint_ieee_prevUnrecoded_T_2 ? toint_ieee_prevUnrecoded_prevUnrecoded : _toint_ieee_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] toint_ieee_prevUnrecoded = {_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21]
wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21]
wire [2:0] _toint_ieee_T_12 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21]
wire [2:0] _toint_ieee_T_20 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21]
wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21]
wire [2:0] _io_out_bits_store_T_10 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21]
wire [2:0] _io_out_bits_store_T_18 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21]
wire [2:0] classify_out_code_2 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21]
wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21]
wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}]
wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81]
wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{10,44,81}]
wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}]
wire [15:0] _toint_ieee_T_6 = _toint_ieee_T_5[15:0]; // @[FPU.scala:446:10, :475:107]
wire _toint_ieee_T_7 = _toint_ieee_T_6[15]; // @[package.scala:132:38]
wire [15:0] _toint_ieee_T_8 = {16{_toint_ieee_T_7}}; // @[package.scala:132:{20,38}]
wire [31:0] _toint_ieee_T_9 = {_toint_ieee_T_8, _toint_ieee_T_6}; // @[package.scala:132:{15,20}]
wire [63:0] _toint_ieee_T_10 = {2{_toint_ieee_T_9}}; // @[package.scala:132:15]
wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN | toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 | _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10]
wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28]
wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_1 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_1 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] toint_ieee_prevUnrecoded_unrecoded_1 = {toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _toint_ieee_prevUnrecoded_prevRecoded_T_3 = toint_ieee_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10]
wire _toint_ieee_prevUnrecoded_prevRecoded_T_4 = toint_ieee_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_5 = toint_ieee_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_1 = {_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_1 = {toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10]
wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28]
wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _toint_ieee_prevUnrecoded_T_5 = toint_ieee_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21]
wire [2:0] _toint_ieee_prevUnrecoded_T_6 = toint_ieee_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28]
wire _toint_ieee_prevUnrecoded_T_7 = &_toint_ieee_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}]
wire [15:0] _toint_ieee_prevUnrecoded_T_8 = toint_ieee_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81]
wire [15:0] _toint_ieee_prevUnrecoded_T_9 = _toint_ieee_prevUnrecoded_T_7 ? toint_ieee_prevUnrecoded_prevUnrecoded_1 : _toint_ieee_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] toint_ieee_prevUnrecoded_1 = {_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21]
wire _toint_ieee_T_13 = &_toint_ieee_T_12; // @[FPU.scala:249:{25,56}]
wire [31:0] _toint_ieee_T_14 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81]
wire [31:0] _toint_ieee_T_15 = _toint_ieee_T_13 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_14; // @[FPU.scala:249:56, :446:{10,44,81}]
wire [63:0] _toint_ieee_T_16 = {_toint_ieee_T_11, _toint_ieee_T_15}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _toint_ieee_T_17 = _toint_ieee_T_16[31:0]; // @[FPU.scala:446:10, :476:109]
wire [63:0] _toint_ieee_T_18 = {2{_toint_ieee_T_17}}; // @[FPU.scala:476:{63,109}]
wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_unrecoded_rawIn_isZero_2 = _toint_ieee_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_unrecoded_rawIn_2_isZero = toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] toint_ieee_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] toint_ieee_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_unrecoded_rawIn_2_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_unrecoded_rawIn_2_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign toint_ieee_unrecoded_rawIn_2_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_unrecoded_rawIn_2_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
assign _toint_ieee_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_unrecoded_rawIn_2_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_4 = toint_ieee_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] toint_ieee_unrecoded_denormShiftDist_2 = _toint_ieee_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _toint_ieee_unrecoded_denormFract_T_4 = toint_ieee_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _toint_ieee_unrecoded_denormFract_T_5 = _toint_ieee_unrecoded_denormFract_T_4 >> toint_ieee_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] toint_ieee_unrecoded_denormFract_2 = _toint_ieee_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _toint_ieee_unrecoded_expOut_T_12 = toint_ieee_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _toint_ieee_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _toint_ieee_unrecoded_expOut_T_14 = _toint_ieee_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _toint_ieee_unrecoded_expOut_T_15 = toint_ieee_unrecoded_isSubnormal_2 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_unrecoded_expOut_T_16 = toint_ieee_unrecoded_rawIn_2_isNaN | toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _toint_ieee_unrecoded_expOut_T_17 = {11{_toint_ieee_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] toint_ieee_unrecoded_expOut_2 = _toint_ieee_unrecoded_expOut_T_15 | _toint_ieee_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _toint_ieee_unrecoded_fractOut_T_4 = toint_ieee_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _toint_ieee_unrecoded_fractOut_T_5 = toint_ieee_unrecoded_rawIn_2_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] toint_ieee_unrecoded_fractOut_2 = toint_ieee_unrecoded_isSubnormal_2 ? toint_ieee_unrecoded_denormFract_2 : _toint_ieee_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] toint_ieee_unrecoded_hi_2 = {toint_ieee_unrecoded_rawIn_2_sign, toint_ieee_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] toint_ieee_unrecoded_2 = {toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [1:0] toint_ieee_prevRecoded_hi_2 = {_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] toint_ieee_prevRecoded_2 = {toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10]
wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = toint_ieee_prevRecoded_2[31:23]; // @[FPU.scala:441:28]
wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = toint_ieee_prevRecoded_2[32]; // @[FPU.scala:441:28]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = toint_ieee_prevRecoded_2[22:0]; // @[FPU.scala:441:28]
assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_2 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] toint_ieee_prevUnrecoded_unrecoded_2 = {toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _toint_ieee_prevUnrecoded_prevRecoded_T_6 = toint_ieee_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10]
wire _toint_ieee_prevUnrecoded_prevRecoded_T_7 = toint_ieee_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_8 = toint_ieee_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_2 = {_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_2 = {toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10]
wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = toint_ieee_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28]
wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = toint_ieee_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = toint_ieee_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28]
assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _toint_ieee_prevUnrecoded_T_10 = toint_ieee_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21]
wire [2:0] _toint_ieee_prevUnrecoded_T_11 = toint_ieee_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28]
wire _toint_ieee_prevUnrecoded_T_12 = &_toint_ieee_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}]
wire [15:0] _toint_ieee_prevUnrecoded_T_13 = toint_ieee_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81]
wire [15:0] _toint_ieee_prevUnrecoded_T_14 = _toint_ieee_prevUnrecoded_T_12 ? toint_ieee_prevUnrecoded_prevUnrecoded_2 : _toint_ieee_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] toint_ieee_prevUnrecoded_2 = {_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _toint_ieee_T_19 = toint_ieee_unrecoded_2[63:32]; // @[FPU.scala:446:21]
wire _toint_ieee_T_21 = &_toint_ieee_T_20; // @[FPU.scala:249:{25,56}]
wire [31:0] _toint_ieee_T_22 = toint_ieee_unrecoded_2[31:0]; // @[FPU.scala:446:81]
wire [31:0] _toint_ieee_T_23 = _toint_ieee_T_21 ? toint_ieee_prevUnrecoded_2 : _toint_ieee_T_22; // @[FPU.scala:249:56, :446:{10,44,81}]
wire [63:0] _toint_ieee_T_24 = {_toint_ieee_T_19, _toint_ieee_T_23}; // @[FPU.scala:446:{10,21,44}]
wire [63:0] _toint_ieee_T_25 = _toint_ieee_T_24; // @[FPU.scala:446:10, :476:109]
wire _GEN = in_typeTagOut == 2'h1; // @[package.scala:39:86]
wire _toint_ieee_T_26; // @[package.scala:39:86]
assign _toint_ieee_T_26 = _GEN; // @[package.scala:39:86]
wire _io_out_bits_store_T_24; // @[package.scala:39:86]
assign _io_out_bits_store_T_24 = _GEN; // @[package.scala:39:86]
wire _classify_out_T_41; // @[package.scala:39:86]
assign _classify_out_T_41 = _GEN; // @[package.scala:39:86]
wire [63:0] _toint_ieee_T_27 = _toint_ieee_T_26 ? _toint_ieee_T_18 : _toint_ieee_T_10; // @[package.scala:39:{76,86}]
wire _GEN_0 = in_typeTagOut == 2'h2; // @[package.scala:39:86]
wire _toint_ieee_T_28; // @[package.scala:39:86]
assign _toint_ieee_T_28 = _GEN_0; // @[package.scala:39:86]
wire _io_out_bits_store_T_26; // @[package.scala:39:86]
assign _io_out_bits_store_T_26 = _GEN_0; // @[package.scala:39:86]
wire _classify_out_T_43; // @[package.scala:39:86]
assign _classify_out_T_43 = _GEN_0; // @[package.scala:39:86]
wire [63:0] _toint_ieee_T_29 = _toint_ieee_T_28 ? _toint_ieee_T_25 : _toint_ieee_T_27; // @[package.scala:39:{76,86}]
wire _toint_ieee_T_30 = &in_typeTagOut; // @[package.scala:39:86]
wire [63:0] toint_ieee = _toint_ieee_T_30 ? _toint_ieee_T_25 : _toint_ieee_T_29; // @[package.scala:39:{76,86}]
wire [63:0] toint; // @[FPU.scala:478:26]
wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59]
wire _intType_T = in_fmt[0]; // @[FPU.scala:466:21, :479:35]
wire intType; // @[FPU.scala:479:28]
wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86]
wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN | io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 | _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28]
wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded = {io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _io_out_bits_store_prevUnrecoded_prevRecoded_T = io_out_bits_store_prevRecoded[15]; // @[FPU.scala:441:28, :442:10]
wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = io_out_bits_store_prevRecoded[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = io_out_bits_store_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi = {_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded = {io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10]
wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = io_out_bits_store_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28]
wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _io_out_bits_store_prevUnrecoded_T = io_out_bits_store_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21]
wire [2:0] _io_out_bits_store_prevUnrecoded_T_1 = io_out_bits_store_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28]
wire _io_out_bits_store_prevUnrecoded_T_2 = &_io_out_bits_store_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_3 = io_out_bits_store_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_4 = _io_out_bits_store_prevUnrecoded_T_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded : _io_out_bits_store_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] io_out_bits_store_prevUnrecoded = {_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21]
wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}]
wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81]
wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{10,44,81}]
wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}]
wire [15:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[15:0]; // @[FPU.scala:446:10, :480:82]
wire [31:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}]
wire [63:0] _io_out_bits_store_T_8 = {2{_io_out_bits_store_T_7}}; // @[FPU.scala:480:49]
wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN | io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 | _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10]
wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28]
wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_1 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = io_out_bits_store_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10]
wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = io_out_bits_store_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = io_out_bits_store_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_1 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10]
wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28]
wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21]
wire [2:0] _io_out_bits_store_prevUnrecoded_T_6 = io_out_bits_store_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28]
wire _io_out_bits_store_prevUnrecoded_T_7 = &_io_out_bits_store_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_9 = _io_out_bits_store_prevUnrecoded_T_7 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_1 : _io_out_bits_store_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] io_out_bits_store_prevUnrecoded_1 = {_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _io_out_bits_store_T_9 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21]
wire _io_out_bits_store_T_11 = &_io_out_bits_store_T_10; // @[FPU.scala:249:{25,56}]
wire [31:0] _io_out_bits_store_T_12 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81]
wire [31:0] _io_out_bits_store_T_13 = _io_out_bits_store_T_11 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_12; // @[FPU.scala:249:56, :446:{10,44,81}]
wire [63:0] _io_out_bits_store_T_14 = {_io_out_bits_store_T_9, _io_out_bits_store_T_13}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _io_out_bits_store_T_15 = _io_out_bits_store_T_14[31:0]; // @[FPU.scala:446:10, :480:82]
wire [63:0] _io_out_bits_store_T_16 = {2{_io_out_bits_store_T_15}}; // @[FPU.scala:480:{49,82}]
wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_unrecoded_rawIn_isZero_2 = _io_out_bits_store_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_unrecoded_rawIn_2_isZero = io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] io_out_bits_store_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] io_out_bits_store_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_unrecoded_rawIn_2_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_unrecoded_rawIn_2_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign io_out_bits_store_unrecoded_rawIn_2_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_unrecoded_rawIn_2_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_unrecoded_rawIn_2_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_4 = io_out_bits_store_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_2 = _io_out_bits_store_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35]
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_5 = _io_out_bits_store_unrecoded_denormFract_T_4 >> io_out_bits_store_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [51:0] io_out_bits_store_unrecoded_denormFract_2 = _io_out_bits_store_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_12 = io_out_bits_store_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _io_out_bits_store_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_14 = _io_out_bits_store_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_15 = io_out_bits_store_unrecoded_isSubnormal_2 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_unrecoded_expOut_T_16 = io_out_bits_store_unrecoded_rawIn_2_isNaN | io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _io_out_bits_store_unrecoded_expOut_T_17 = {11{_io_out_bits_store_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [10:0] io_out_bits_store_unrecoded_expOut_2 = _io_out_bits_store_unrecoded_expOut_T_15 | _io_out_bits_store_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_5 = io_out_bits_store_unrecoded_rawIn_2_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [51:0] io_out_bits_store_unrecoded_fractOut_2 = io_out_bits_store_unrecoded_isSubnormal_2 ? io_out_bits_store_unrecoded_denormFract_2 : _io_out_bits_store_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [11:0] io_out_bits_store_unrecoded_hi_2 = {io_out_bits_store_unrecoded_rawIn_2_sign, io_out_bits_store_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
wire [63:0] io_out_bits_store_unrecoded_2 = {io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [1:0] io_out_bits_store_prevRecoded_hi_2 = {_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [32:0] io_out_bits_store_prevRecoded_2 = {io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10]
wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = io_out_bits_store_prevRecoded_2[31:23]; // @[FPU.scala:441:28]
wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevRecoded_2[32]; // @[FPU.scala:441:28]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevRecoded_2[22:0]; // @[FPU.scala:441:28]
assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_2 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = io_out_bits_store_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10]
wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = io_out_bits_store_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10]
wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = io_out_bits_store_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10]
wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10]
wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_2 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10]
wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28]
wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28]
assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23]
wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}]
wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35]
wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23]
wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21]
wire [2:0] _io_out_bits_store_prevUnrecoded_T_11 = io_out_bits_store_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28]
wire _io_out_bits_store_prevUnrecoded_T_12 = &_io_out_bits_store_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_13 = io_out_bits_store_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81]
wire [15:0] _io_out_bits_store_prevUnrecoded_T_14 = _io_out_bits_store_prevUnrecoded_T_12 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_2 : _io_out_bits_store_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}]
wire [31:0] io_out_bits_store_prevUnrecoded_2 = {_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}]
wire [31:0] _io_out_bits_store_T_17 = io_out_bits_store_unrecoded_2[63:32]; // @[FPU.scala:446:21]
wire _io_out_bits_store_T_19 = &_io_out_bits_store_T_18; // @[FPU.scala:249:{25,56}]
wire [31:0] _io_out_bits_store_T_20 = io_out_bits_store_unrecoded_2[31:0]; // @[FPU.scala:446:81]
wire [31:0] _io_out_bits_store_T_21 = _io_out_bits_store_T_19 ? io_out_bits_store_prevUnrecoded_2 : _io_out_bits_store_T_20; // @[FPU.scala:249:56, :446:{10,44,81}]
wire [63:0] _io_out_bits_store_T_22 = {_io_out_bits_store_T_17, _io_out_bits_store_T_21}; // @[FPU.scala:446:{10,21,44}]
wire [63:0] _io_out_bits_store_T_23 = _io_out_bits_store_T_22; // @[FPU.scala:446:10, :480:82]
wire [63:0] _io_out_bits_store_T_25 = _io_out_bits_store_T_24 ? _io_out_bits_store_T_16 : _io_out_bits_store_T_8; // @[package.scala:39:{76,86}]
wire [63:0] _io_out_bits_store_T_27 = _io_out_bits_store_T_26 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_25; // @[package.scala:39:{76,86}]
wire _io_out_bits_store_T_28 = &in_typeTagOut; // @[package.scala:39:86]
assign _io_out_bits_store_T_29 = _io_out_bits_store_T_28 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_27; // @[package.scala:39:{76,86}]
assign io_out_bits_store_0 = _io_out_bits_store_T_29; // @[package.scala:39:76]
wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59]
wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38]
wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}]
wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}]
assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15]
assign io_out_bits_toint_0 = _io_out_bits_toint_T_6; // @[package.scala:39:76]
wire [62:0] _classify_out_fractOut_T = {classify_out_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] classify_out_fractOut = _classify_out_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _classify_out_expOut_T_2 = _classify_out_expOut_T | _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8]
wire classify_out_sign_1 = _classify_out_T[16]; // @[FPU.scala:253:17, :283:8]
wire [2:0] classify_out_code = _classify_out_T[15:13]; // @[FPU.scala:254:17, :283:8]
wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22]
wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28]
wire [3:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[13:10]; // @[FPU.scala:258:30, :283:8]
wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 4'h2; // @[FPU.scala:258:{30,55}]
wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28]
wire _GEN_1 = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46]
wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46]
assign _classify_out_isSubnormal_T_1 = _GEN_1; // @[FPU.scala:259:46]
wire _classify_out_isNormal_T; // @[FPU.scala:260:27]
assign _classify_out_isNormal_T = _GEN_1; // @[FPU.scala:259:46, :260:27]
wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}]
wire classify_out_isSubnormal = _classify_out_isSubnormal_T | _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}]
wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38]
wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}]
wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67]
wire classify_out_isNormal = _classify_out_isNormal_T_2 | _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}]
wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23]
wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35]
wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}]
wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}]
wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22]
wire _classify_out_isSNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :283:8]
wire _classify_out_isQNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :265:28, :283:8]
wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}]
wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}]
wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}]
wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34]
wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}]
wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}]
wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}]
wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24]
wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}]
wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41]
wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}]
wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55]
wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21]
wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39]
wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54]
wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}]
wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}]
wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21]
wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8]
wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21]
wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8]
wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}]
wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8]
wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8]
wire [75:0] _classify_out_fractOut_T_1 = {classify_out_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] classify_out_fractOut_1 = _classify_out_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] classify_out_expOut_expCode_1 = classify_out_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _classify_out_expOut_commonCase_T_3 = {1'h0, classify_out_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _classify_out_expOut_commonCase_T_4 = _classify_out_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31]
wire [12:0] _classify_out_expOut_commonCase_T_5 = {1'h0, _classify_out_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] classify_out_expOut_commonCase_1 = _classify_out_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50]
wire _classify_out_expOut_T_6 = classify_out_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _classify_out_expOut_T_7 = classify_out_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _classify_out_expOut_T_8 = _classify_out_expOut_T_6 | _classify_out_expOut_T_7; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _classify_out_expOut_T_9 = classify_out_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _classify_out_expOut_T_10 = {classify_out_expOut_expCode_1, _classify_out_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _classify_out_expOut_T_11 = classify_out_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] classify_out_expOut_1 = _classify_out_expOut_T_8 ? _classify_out_expOut_T_10 : _classify_out_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] classify_out_hi_2 = {classify_out_sign_2, classify_out_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] _classify_out_T_14 = {classify_out_hi_2, classify_out_fractOut_1}; // @[FPU.scala:277:38, :283:8]
wire classify_out_sign_3 = _classify_out_T_14[32]; // @[FPU.scala:253:17, :283:8]
wire [2:0] classify_out_code_1 = _classify_out_T_14[31:29]; // @[FPU.scala:254:17, :283:8]
wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22]
wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28]
wire [6:0] _classify_out_isHighSubnormalIn_T_1 = _classify_out_T_14[29:23]; // @[FPU.scala:258:30, :283:8]
wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 7'h2; // @[FPU.scala:258:{30,55}]
wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28]
wire _GEN_2 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46]
wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46]
assign _classify_out_isSubnormal_T_4 = _GEN_2; // @[FPU.scala:259:46]
wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27]
assign _classify_out_isNormal_T_4 = _GEN_2; // @[FPU.scala:259:46, :260:27]
wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}]
wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 | _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}]
wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38]
wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}]
wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67]
wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 | _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}]
wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23]
wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35]
wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}]
wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}]
wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22]
wire _classify_out_isSNaN_T_2 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :283:8]
wire _classify_out_isQNaN_T_1 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :265:28, :283:8]
wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}]
wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}]
wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}]
wire _classify_out_T_15 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34]
wire _classify_out_T_16 = classify_out_isInf_1 & _classify_out_T_15; // @[FPU.scala:262:27, :267:{31,34}]
wire _classify_out_T_17 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:{34,53}]
wire _classify_out_T_18 = classify_out_isNormal_1 & _classify_out_T_17; // @[FPU.scala:260:57, :267:{50,53}]
wire _classify_out_T_19 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:24]
wire _classify_out_T_20 = classify_out_isSubnormal_1 & _classify_out_T_19; // @[FPU.scala:259:36, :268:{21,24}]
wire _classify_out_T_21 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:41]
wire _classify_out_T_22 = classify_out_isZero_1 & _classify_out_T_21; // @[FPU.scala:261:23, :268:{38,41}]
wire _classify_out_T_23 = classify_out_isZero_1 & classify_out_sign_3; // @[FPU.scala:253:17, :261:23, :268:55]
wire _classify_out_T_24 = classify_out_isSubnormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :259:36, :269:21]
wire _classify_out_T_25 = classify_out_isNormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :260:57, :269:39]
wire _classify_out_T_26 = classify_out_isInf_1 & classify_out_sign_3; // @[FPU.scala:253:17, :262:27, :269:54]
wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_25, _classify_out_T_26}; // @[FPU.scala:267:8, :269:{39,54}]
wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_22, _classify_out_T_23}; // @[FPU.scala:267:8, :268:{38,55}]
wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_24}; // @[FPU.scala:267:8, :269:21]
wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8]
wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_18, _classify_out_T_20}; // @[FPU.scala:267:{8,50}, :268:21]
wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8]
wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_16}; // @[FPU.scala:267:{8,31}]
wire [4:0] classify_out_hi_3 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8]
wire [9:0] _classify_out_T_27 = {classify_out_hi_3, classify_out_lo_1}; // @[FPU.scala:267:8]
wire [1:0] classify_out_codeHi_2 = classify_out_code_2[2:1]; // @[FPU.scala:254:17, :255:22]
wire classify_out_isSpecial_2 = &classify_out_codeHi_2; // @[FPU.scala:255:22, :256:28]
wire [9:0] _classify_out_isHighSubnormalIn_T_2 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21]
wire classify_out_isHighSubnormalIn_2 = _classify_out_isHighSubnormalIn_T_2 < 10'h2; // @[FPU.scala:258:{30,55}]
wire _classify_out_isSubnormal_T_6 = classify_out_code_2 == 3'h1; // @[FPU.scala:254:17, :259:28]
wire _GEN_3 = classify_out_codeHi_2 == 2'h1; // @[FPU.scala:255:22, :259:46]
wire _classify_out_isSubnormal_T_7; // @[FPU.scala:259:46]
assign _classify_out_isSubnormal_T_7 = _GEN_3; // @[FPU.scala:259:46]
wire _classify_out_isNormal_T_8; // @[FPU.scala:260:27]
assign _classify_out_isNormal_T_8 = _GEN_3; // @[FPU.scala:259:46, :260:27]
wire _classify_out_isSubnormal_T_8 = _classify_out_isSubnormal_T_7 & classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :259:{46,54}]
wire classify_out_isSubnormal_2 = _classify_out_isSubnormal_T_6 | _classify_out_isSubnormal_T_8; // @[FPU.scala:259:{28,36,54}]
wire _classify_out_isNormal_T_9 = ~classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :260:38]
wire _classify_out_isNormal_T_10 = _classify_out_isNormal_T_8 & _classify_out_isNormal_T_9; // @[FPU.scala:260:{27,35,38}]
wire _classify_out_isNormal_T_11 = classify_out_codeHi_2 == 2'h2; // @[FPU.scala:255:22, :260:67]
wire classify_out_isNormal_2 = _classify_out_isNormal_T_10 | _classify_out_isNormal_T_11; // @[FPU.scala:260:{35,57,67}]
wire classify_out_isZero_2 = classify_out_code_2 == 3'h0; // @[FPU.scala:254:17, :261:23]
wire _classify_out_isInf_T_4 = classify_out_code_2[0]; // @[FPU.scala:254:17, :262:35]
wire _classify_out_isInf_T_5 = ~_classify_out_isInf_T_4; // @[FPU.scala:262:{30,35}]
wire classify_out_isInf_2 = classify_out_isSpecial_2 & _classify_out_isInf_T_5; // @[FPU.scala:256:28, :262:{27,30}]
wire classify_out_isNaN_2 = &classify_out_code_2; // @[FPU.scala:254:17, :263:22]
wire _classify_out_isSNaN_T_4 = in_in1[51]; // @[FPU.scala:264:29, :466:21]
wire _classify_out_isQNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21]
wire _classify_out_isSNaN_T_5 = ~_classify_out_isSNaN_T_4; // @[FPU.scala:264:{27,29}]
wire classify_out_isSNaN_2 = classify_out_isNaN_2 & _classify_out_isSNaN_T_5; // @[FPU.scala:263:22, :264:{24,27}]
wire classify_out_isQNaN_2 = classify_out_isNaN_2 & _classify_out_isQNaN_T_2; // @[FPU.scala:263:22, :265:{24,28}]
wire _classify_out_T_28 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34]
wire _classify_out_T_29 = classify_out_isInf_2 & _classify_out_T_28; // @[FPU.scala:262:27, :267:{31,34}]
wire _classify_out_T_30 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:{34,53}]
wire _classify_out_T_31 = classify_out_isNormal_2 & _classify_out_T_30; // @[FPU.scala:260:57, :267:{50,53}]
wire _classify_out_T_32 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:24]
wire _classify_out_T_33 = classify_out_isSubnormal_2 & _classify_out_T_32; // @[FPU.scala:259:36, :268:{21,24}]
wire _classify_out_T_34 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:41]
wire _classify_out_T_35 = classify_out_isZero_2 & _classify_out_T_34; // @[FPU.scala:261:23, :268:{38,41}]
wire _classify_out_T_36 = classify_out_isZero_2 & classify_out_sign_4; // @[FPU.scala:253:17, :261:23, :268:55]
wire _classify_out_T_37 = classify_out_isSubnormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :259:36, :269:21]
wire _classify_out_T_38 = classify_out_isNormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :260:57, :269:39]
wire _classify_out_T_39 = classify_out_isInf_2 & classify_out_sign_4; // @[FPU.scala:253:17, :262:27, :269:54]
wire [1:0] classify_out_lo_lo_2 = {_classify_out_T_38, _classify_out_T_39}; // @[FPU.scala:267:8, :269:{39,54}]
wire [1:0] classify_out_lo_hi_hi_2 = {_classify_out_T_35, _classify_out_T_36}; // @[FPU.scala:267:8, :268:{38,55}]
wire [2:0] classify_out_lo_hi_2 = {classify_out_lo_hi_hi_2, _classify_out_T_37}; // @[FPU.scala:267:8, :269:21]
wire [4:0] classify_out_lo_2 = {classify_out_lo_hi_2, classify_out_lo_lo_2}; // @[FPU.scala:267:8]
wire [1:0] classify_out_hi_lo_2 = {_classify_out_T_31, _classify_out_T_33}; // @[FPU.scala:267:{8,50}, :268:21]
wire [1:0] classify_out_hi_hi_hi_2 = {classify_out_isQNaN_2, classify_out_isSNaN_2}; // @[FPU.scala:264:24, :265:24, :267:8]
wire [2:0] classify_out_hi_hi_2 = {classify_out_hi_hi_hi_2, _classify_out_T_29}; // @[FPU.scala:267:{8,31}]
wire [4:0] classify_out_hi_4 = {classify_out_hi_hi_2, classify_out_hi_lo_2}; // @[FPU.scala:267:8]
wire [9:0] _classify_out_T_40 = {classify_out_hi_4, classify_out_lo_2}; // @[FPU.scala:267:8]
wire [9:0] _classify_out_T_42 = _classify_out_T_41 ? _classify_out_T_27 : _classify_out_T_13; // @[package.scala:39:{76,86}]
wire [9:0] _classify_out_T_44 = _classify_out_T_43 ? _classify_out_T_40 : _classify_out_T_42; // @[package.scala:39:{76,86}]
wire _classify_out_T_45 = &in_typeTagOut; // @[package.scala:39:86]
wire [9:0] classify_out = _classify_out_T_45 ? _classify_out_T_40 : _classify_out_T_44; // @[package.scala:39:{76,86}]
wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76]
wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76]
wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}]
wire [63:0] _toint_T_2 = {54'h0, classify_out} | _toint_T_1; // @[package.scala:39:76]
wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15]
wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27]
wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}]
wire _toint_T_6 = |_toint_T_5; // @[FPU.scala:491:{22,53}]
wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}]
wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} | _toint_T_8; // @[FPU.scala:491:{53,57,82}]
wire cvtType = in_typ[1]; // @[package.scala:163:13]
assign intType = in_wflags ? ~in_ren2 & cvtType : ~(in_rm[0]) & _intType_T; // @[package.scala:163:13]
wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35]
wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41]
wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}]
wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55]
wire _io_out_bits_exc_T_1 = |_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}]
wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102]
wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90]
wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}]
wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}]
wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}]
wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}]
wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62]
wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}]
wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46]
wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69]
wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}]
wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}]
wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50]
wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84]
wire invalid = _invalid_T | _invalid_T_1; // @[FPU.scala:515:{50,54,84}]
wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53]
wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}]
assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13]
wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53]
wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}]
wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33]
wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}]
assign io_out_bits_exc_0 = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13]
wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}]
wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}]
wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}]
assign _io_out_bits_lt_T_5 = _dcmp_io_lt | _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}]
assign io_out_bits_lt_0 = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32]
always @(posedge clock) begin // @[FPU.scala:453:7]
if (io_in_valid_0) begin // @[FPU.scala:453:7]
in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21]
in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21]
in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21]
in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21]
in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21]
in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21]
in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21]
in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21]
in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21]
in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21]
in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21]
in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21]
in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21]
in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21]
in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21]
in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21]
in_vec <= io_in_bits_vec_0; // @[FPU.scala:453:7, :466:21]
in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21]
in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:453:7, :466:21]
in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21]
in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:453:7, :466:21]
in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21]
in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21]
in_in3 <= io_in_bits_in3_0; // @[FPU.scala:453:7, :466:21]
end
valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22]
always @(posedge)
CompareRecFN_1 dcmp ( // @[FPU.scala:469:20]
.io_a (in_in1), // @[FPU.scala:466:21]
.io_b (in_in2), // @[FPU.scala:466:21]
.io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24]
.io_lt (_dcmp_io_lt),
.io_eq (_dcmp_io_eq),
.io_exceptionFlags (_dcmp_io_exceptionFlags)
); // @[FPU.scala:469:20]
RecFNToIN_e11_s53_i64_1 conv ( // @[FPU.scala:498:24]
.clock (clock),
.reset (reset),
.io_in (in_in1), // @[FPU.scala:466:21]
.io_roundingMode (in_rm), // @[FPU.scala:466:21]
.io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28]
.io_out (_conv_io_out),
.io_intExceptionFlags (_conv_io_intExceptionFlags)
); // @[FPU.scala:498:24]
RecFNToIN_e11_s53_i32_1 narrow ( // @[FPU.scala:508:30]
.clock (clock),
.reset (reset),
.io_in (in_in1), // @[FPU.scala:466:21]
.io_roundingMode (in_rm), // @[FPU.scala:466:21]
.io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34]
.io_intExceptionFlags (_narrow_io_intExceptionFlags)
); // @[FPU.scala:508:30]
assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7]
assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7]
assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7]
assign io_out_bits_lt = io_out_bits_lt_0; // @[FPU.scala:453:7]
assign io_out_bits_store = io_out_bits_store_0; // @[FPU.scala:453:7]
assign io_out_bits_toint = io_out_bits_toint_0; // @[FPU.scala:453:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:453:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_pbus_to_bootaddressreg :
input clock : Clock
input reset : Reset
output auto : { fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst fragmenter of TLFragmenter_BootAddrReg
connect fragmenter.clock, clock
connect fragmenter.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect fragmenter.auto.anon_in, tlOut
connect tlIn, auto.tl_in
connect fragmenter.auto.anon_out.d, auto.fragmenter_anon_out.d
connect auto.fragmenter_anon_out.a.bits, fragmenter.auto.anon_out.a.bits
connect auto.fragmenter_anon_out.a.valid, fragmenter.auto.anon_out.a.valid
connect fragmenter.auto.anon_out.a.ready, auto.fragmenter_anon_out.a.ready
extmodule plusarg_reader_14 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_15 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLInterconnectCoupler_pbus_to_bootaddressreg( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [12:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [12:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
TLFragmenter_BootAddrReg fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (auto_tl_in_a_ready),
.auto_anon_in_a_valid (auto_tl_in_a_valid),
.auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode),
.auto_anon_in_a_bits_param (auto_tl_in_a_bits_param),
.auto_anon_in_a_bits_size (auto_tl_in_a_bits_size),
.auto_anon_in_a_bits_source (auto_tl_in_a_bits_source),
.auto_anon_in_a_bits_address (auto_tl_in_a_bits_address),
.auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask),
.auto_anon_in_a_bits_data (auto_tl_in_a_bits_data),
.auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt),
.auto_anon_in_d_ready (auto_tl_in_d_ready),
.auto_anon_in_d_valid (auto_tl_in_d_valid),
.auto_anon_in_d_bits_opcode (auto_tl_in_d_bits_opcode),
.auto_anon_in_d_bits_size (auto_tl_in_d_bits_size),
.auto_anon_in_d_bits_source (auto_tl_in_d_bits_source),
.auto_anon_in_d_bits_data (auto_tl_in_d_bits_data),
.auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready),
.auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready),
.auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid),
.auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode),
.auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size),
.auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source),
.auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data)
); // @[Fragmenter.scala:345:34]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ErrorDeviceWrapper :
input clock : Clock
input reset : Reset
output auto : { flip buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst error of TLError
connect error.clock, clock
connect error.reset, reset
inst buffer of TLBuffer_a14d64s8k1z4u
connect buffer.clock, clock
connect buffer.reset, reset
connect error.auto.in, buffer.auto.out
connect buffer.auto.in, auto.buffer_in
extmodule plusarg_reader_100 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_101 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module ErrorDeviceWrapper( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [13:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _error_auto_in_a_ready; // @[CanHaveBuiltInDevices.scala:40:29]
wire _error_auto_in_d_valid; // @[CanHaveBuiltInDevices.scala:40:29]
wire [2:0] _error_auto_in_d_bits_opcode; // @[CanHaveBuiltInDevices.scala:40:29]
wire [3:0] _error_auto_in_d_bits_size; // @[CanHaveBuiltInDevices.scala:40:29]
wire [7:0] _error_auto_in_d_bits_source; // @[CanHaveBuiltInDevices.scala:40:29]
wire _error_auto_in_d_bits_corrupt; // @[CanHaveBuiltInDevices.scala:40:29]
TLError error ( // @[CanHaveBuiltInDevices.scala:40:29]
.clock (clock),
.reset (reset),
.auto_in_a_ready (_error_auto_in_a_ready),
.auto_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_in_d_valid (_error_auto_in_d_valid),
.auto_in_d_bits_opcode (_error_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_error_auto_in_d_bits_size),
.auto_in_d_bits_source (_error_auto_in_d_bits_source),
.auto_in_d_bits_corrupt (_error_auto_in_d_bits_corrupt)
); // @[CanHaveBuiltInDevices.scala:40:29]
TLBuffer_a14d64s8k1z4u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (auto_buffer_in_a_ready),
.auto_in_a_valid (auto_buffer_in_a_valid),
.auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode),
.auto_in_a_bits_param (auto_buffer_in_a_bits_param),
.auto_in_a_bits_size (auto_buffer_in_a_bits_size),
.auto_in_a_bits_source (auto_buffer_in_a_bits_source),
.auto_in_a_bits_address (auto_buffer_in_a_bits_address),
.auto_in_a_bits_mask (auto_buffer_in_a_bits_mask),
.auto_in_a_bits_data (auto_buffer_in_a_bits_data),
.auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt),
.auto_in_d_ready (auto_buffer_in_d_ready),
.auto_in_d_valid (auto_buffer_in_d_valid),
.auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode),
.auto_in_d_bits_param (auto_buffer_in_d_bits_param),
.auto_in_d_bits_size (auto_buffer_in_d_bits_size),
.auto_in_d_bits_source (auto_buffer_in_d_bits_source),
.auto_in_d_bits_sink (auto_buffer_in_d_bits_sink),
.auto_in_d_bits_denied (auto_buffer_in_d_bits_denied),
.auto_in_d_bits_data (auto_buffer_in_d_bits_data),
.auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt),
.auto_out_a_ready (_error_auto_in_a_ready), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_error_auto_in_d_valid), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_opcode (_error_auto_in_d_bits_opcode), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_size (_error_auto_in_d_bits_size), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_source (_error_auto_in_d_bits_source), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_corrupt (_error_auto_in_d_bits_corrupt) // @[CanHaveBuiltInDevices.scala:40:29]
); // @[Buffer.scala:75:28]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s5k3z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_13
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s5k3z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s5k3z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_28 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_29 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a32d64s5k3z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_13 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s5k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s5k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_24 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_24
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_89
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_24( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_24 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_89 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_14 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_14( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_52 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_52
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_52
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult
connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_72
connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFN_e8_s24_52( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_52 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_52 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_72 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}}
wire _in_flight_WIRE : UInt<1>[3]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = or(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_17 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_24 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_25 = and(_T_23, _T_24)
node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_31 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_32 = and(_T_30, _T_31)
node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_36 = and(_T_34, _T_35)
node _T_37 = or(_T_22, _T_29)
node _T_38 = or(_T_37, _T_36)
node _T_39 = or(_T_15, _T_38)
node _T_40 = asUInt(reset)
node _T_41 = eq(_T_40, UInt<1>(0h0))
when _T_41 :
node _T_42 = eq(_T_39, UInt<1>(0h0))
when _T_42 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_39, UInt<1>(0h1), "") : assert_3 | module NoCMonitor( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie4_is8_oe8_os24_3 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<6>, sig : UInt<9>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hf0)))
node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0)
node sAdjustedExp = cvt(_sAdjustedExp_T_1)
node adjustedSig = shl(io.in.sig, 18)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _common_expOut_T = bits(sAdjustedExp, 8, 0)
node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0))
node _common_expOut_T_2 = tail(_common_expOut_T_1, 1)
connect common_expOut, _common_expOut_T_2
node _common_fractOut_T = bits(adjustedSig, 25, 3)
node _common_fractOut_T_1 = bits(adjustedSig, 24, 2)
node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
connect common_overflow, UInt<1>(0h0)
connect common_totalUnderflow, UInt<1>(0h0)
connect common_underflow, UInt<1>(0h0)
connect common_inexact, UInt<1>(0h0)
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie4_is8_oe8_os24_3( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [5:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [8:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [5:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :237:{22,33,36}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire [9:0] _sAdjustedExp_T = {{4{io_in_sExp_0[5]}}, io_in_sExp_0} + 10'hF0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [26:0] adjustedSig = {io_in_sig_0, 18'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [8:0] _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:136:55]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:138:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire [8:0] _common_expOut_T = sAdjustedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:38]
wire [9:0] _common_expOut_T_1 = {1'h0, _common_expOut_T}; // @[RoundAnyRawFNToRecFN.scala:136:{38,55}]
assign _common_expOut_T_2 = _common_expOut_T_1[8:0]; // @[RoundAnyRawFNToRecFN.scala:136:55]
assign common_expOut = _common_expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :136:55]
wire [22:0] _common_fractOut_T = adjustedSig[25:3]; // @[RoundAnyRawFNToRecFN.scala:114:22, :139:28]
wire [22:0] _common_fractOut_T_1 = adjustedSig[24:2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :140:28]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:138:16, :140:28]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_42 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_59
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_42( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_59 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RenameBusyTable :
input clock : Clock
input reset : Reset
output io : { flip ren_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[3], busy_resps : { prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>}[3], flip rebusy_reqs : UInt<1>[3], flip wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip child_rebusys : UInt<3>, debug : { busytable : UInt<100>}}
wire wakeups_0 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}
reg wakeups_wu_valid_REG : UInt<1>, clock
connect wakeups_wu_valid_REG, io.wakeups[0].valid
reg wakeups_wu_valid_REG_1 : UInt, clock
connect wakeups_wu_valid_REG_1, io.wakeups[0].bits.speculative_mask
node _wakeups_wu_valid_T = and(wakeups_wu_valid_REG_1, io.child_rebusys)
node _wakeups_wu_valid_T_1 = eq(_wakeups_wu_valid_T, UInt<1>(0h0))
node _wakeups_wu_valid_T_2 = and(wakeups_wu_valid_REG, _wakeups_wu_valid_T_1)
connect wakeups_0.valid, _wakeups_wu_valid_T_2
reg wakeups_wu_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}, clock
connect wakeups_wu_bits_REG, io.wakeups[0].bits
connect wakeups_0.bits, wakeups_wu_bits_REG
wire wakeups_1 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}
reg wakeups_wu_valid_REG_2 : UInt<1>, clock
connect wakeups_wu_valid_REG_2, io.wakeups[1].valid
reg wakeups_wu_valid_REG_3 : UInt, clock
connect wakeups_wu_valid_REG_3, io.wakeups[1].bits.speculative_mask
node _wakeups_wu_valid_T_3 = and(wakeups_wu_valid_REG_3, io.child_rebusys)
node _wakeups_wu_valid_T_4 = eq(_wakeups_wu_valid_T_3, UInt<1>(0h0))
node _wakeups_wu_valid_T_5 = and(wakeups_wu_valid_REG_2, _wakeups_wu_valid_T_4)
connect wakeups_1.valid, _wakeups_wu_valid_T_5
reg wakeups_wu_bits_REG_1 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}, clock
connect wakeups_wu_bits_REG_1, io.wakeups[1].bits
connect wakeups_1.bits, wakeups_wu_bits_REG_1
wire wakeups_2 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}
reg wakeups_wu_valid_REG_4 : UInt<1>, clock
connect wakeups_wu_valid_REG_4, io.wakeups[2].valid
reg wakeups_wu_valid_REG_5 : UInt, clock
connect wakeups_wu_valid_REG_5, io.wakeups[2].bits.speculative_mask
node _wakeups_wu_valid_T_6 = and(wakeups_wu_valid_REG_5, io.child_rebusys)
node _wakeups_wu_valid_T_7 = eq(_wakeups_wu_valid_T_6, UInt<1>(0h0))
node _wakeups_wu_valid_T_8 = and(wakeups_wu_valid_REG_4, _wakeups_wu_valid_T_7)
connect wakeups_2.valid, _wakeups_wu_valid_T_8
reg wakeups_wu_bits_REG_2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}, clock
connect wakeups_wu_bits_REG_2, io.wakeups[2].bits
connect wakeups_2.bits, wakeups_wu_bits_REG_2
wire wakeups_3 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}
reg wakeups_wu_valid_REG_6 : UInt<1>, clock
connect wakeups_wu_valid_REG_6, io.wakeups[3].valid
reg wakeups_wu_valid_REG_7 : UInt, clock
connect wakeups_wu_valid_REG_7, io.wakeups[3].bits.speculative_mask
node _wakeups_wu_valid_T_9 = and(wakeups_wu_valid_REG_7, io.child_rebusys)
node _wakeups_wu_valid_T_10 = eq(_wakeups_wu_valid_T_9, UInt<1>(0h0))
node _wakeups_wu_valid_T_11 = and(wakeups_wu_valid_REG_6, _wakeups_wu_valid_T_10)
connect wakeups_3.valid, _wakeups_wu_valid_T_11
reg wakeups_wu_bits_REG_3 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}, clock
connect wakeups_wu_bits_REG_3, io.wakeups[3].bits
connect wakeups_3.bits, wakeups_wu_bits_REG_3
wire wakeups_4 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}
reg wakeups_wu_valid_REG_8 : UInt<1>, clock
connect wakeups_wu_valid_REG_8, io.wakeups[4].valid
reg wakeups_wu_valid_REG_9 : UInt, clock
connect wakeups_wu_valid_REG_9, io.wakeups[4].bits.speculative_mask
node _wakeups_wu_valid_T_12 = and(wakeups_wu_valid_REG_9, io.child_rebusys)
node _wakeups_wu_valid_T_13 = eq(_wakeups_wu_valid_T_12, UInt<1>(0h0))
node _wakeups_wu_valid_T_14 = and(wakeups_wu_valid_REG_8, _wakeups_wu_valid_T_13)
connect wakeups_4.valid, _wakeups_wu_valid_T_14
reg wakeups_wu_bits_REG_4 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}, clock
connect wakeups_wu_bits_REG_4, io.wakeups[4].bits
connect wakeups_4.bits, wakeups_wu_bits_REG_4
regreset busy_table : UInt<100>, clock, reset, UInt<100>(0h0)
node _busy_table_wb_T = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst)
node _busy_table_wb_T_1 = eq(wakeups_0.bits.rebusy, UInt<1>(0h0))
node _busy_table_wb_T_2 = and(wakeups_0.valid, _busy_table_wb_T_1)
node _busy_table_wb_T_3 = mux(_busy_table_wb_T_2, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_wb_T_4 = and(_busy_table_wb_T, _busy_table_wb_T_3)
node _busy_table_wb_T_5 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst)
node _busy_table_wb_T_6 = eq(wakeups_1.bits.rebusy, UInt<1>(0h0))
node _busy_table_wb_T_7 = and(wakeups_1.valid, _busy_table_wb_T_6)
node _busy_table_wb_T_8 = mux(_busy_table_wb_T_7, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_wb_T_9 = and(_busy_table_wb_T_5, _busy_table_wb_T_8)
node _busy_table_wb_T_10 = dshl(UInt<1>(0h1), wakeups_2.bits.uop.pdst)
node _busy_table_wb_T_11 = eq(wakeups_2.bits.rebusy, UInt<1>(0h0))
node _busy_table_wb_T_12 = and(wakeups_2.valid, _busy_table_wb_T_11)
node _busy_table_wb_T_13 = mux(_busy_table_wb_T_12, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_wb_T_14 = and(_busy_table_wb_T_10, _busy_table_wb_T_13)
node _busy_table_wb_T_15 = dshl(UInt<1>(0h1), wakeups_3.bits.uop.pdst)
node _busy_table_wb_T_16 = eq(wakeups_3.bits.rebusy, UInt<1>(0h0))
node _busy_table_wb_T_17 = and(wakeups_3.valid, _busy_table_wb_T_16)
node _busy_table_wb_T_18 = mux(_busy_table_wb_T_17, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_wb_T_19 = and(_busy_table_wb_T_15, _busy_table_wb_T_18)
node _busy_table_wb_T_20 = dshl(UInt<1>(0h1), wakeups_4.bits.uop.pdst)
node _busy_table_wb_T_21 = eq(wakeups_4.bits.rebusy, UInt<1>(0h0))
node _busy_table_wb_T_22 = and(wakeups_4.valid, _busy_table_wb_T_21)
node _busy_table_wb_T_23 = mux(_busy_table_wb_T_22, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_wb_T_24 = and(_busy_table_wb_T_20, _busy_table_wb_T_23)
node _busy_table_wb_T_25 = or(_busy_table_wb_T_4, _busy_table_wb_T_9)
node _busy_table_wb_T_26 = or(_busy_table_wb_T_25, _busy_table_wb_T_14)
node _busy_table_wb_T_27 = or(_busy_table_wb_T_26, _busy_table_wb_T_19)
node _busy_table_wb_T_28 = or(_busy_table_wb_T_27, _busy_table_wb_T_24)
node _busy_table_wb_T_29 = not(_busy_table_wb_T_28)
node busy_table_wb = and(busy_table, _busy_table_wb_T_29)
node _busy_table_next_T = dshl(UInt<1>(0h1), io.ren_uops[0].pdst)
node _busy_table_next_T_1 = mux(io.rebusy_reqs[0], UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_2 = and(_busy_table_next_T, _busy_table_next_T_1)
node _busy_table_next_T_3 = dshl(UInt<1>(0h1), io.ren_uops[1].pdst)
node _busy_table_next_T_4 = mux(io.rebusy_reqs[1], UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_5 = and(_busy_table_next_T_3, _busy_table_next_T_4)
node _busy_table_next_T_6 = dshl(UInt<1>(0h1), io.ren_uops[2].pdst)
node _busy_table_next_T_7 = mux(io.rebusy_reqs[2], UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_8 = and(_busy_table_next_T_6, _busy_table_next_T_7)
node _busy_table_next_T_9 = or(_busy_table_next_T_2, _busy_table_next_T_5)
node _busy_table_next_T_10 = or(_busy_table_next_T_9, _busy_table_next_T_8)
node _busy_table_next_T_11 = or(busy_table_wb, _busy_table_next_T_10)
node _busy_table_next_T_12 = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst)
node _busy_table_next_T_13 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _busy_table_next_T_14 = mux(_busy_table_next_T_13, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_15 = and(_busy_table_next_T_12, _busy_table_next_T_14)
node _busy_table_next_T_16 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst)
node _busy_table_next_T_17 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _busy_table_next_T_18 = mux(_busy_table_next_T_17, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_19 = and(_busy_table_next_T_16, _busy_table_next_T_18)
node _busy_table_next_T_20 = dshl(UInt<1>(0h1), wakeups_2.bits.uop.pdst)
node _busy_table_next_T_21 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _busy_table_next_T_22 = mux(_busy_table_next_T_21, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_23 = and(_busy_table_next_T_20, _busy_table_next_T_22)
node _busy_table_next_T_24 = dshl(UInt<1>(0h1), wakeups_3.bits.uop.pdst)
node _busy_table_next_T_25 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _busy_table_next_T_26 = mux(_busy_table_next_T_25, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_27 = and(_busy_table_next_T_24, _busy_table_next_T_26)
node _busy_table_next_T_28 = dshl(UInt<1>(0h1), wakeups_4.bits.uop.pdst)
node _busy_table_next_T_29 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _busy_table_next_T_30 = mux(_busy_table_next_T_29, UInt<100>(0hfffffffffffffffffffffffff), UInt<100>(0h0))
node _busy_table_next_T_31 = and(_busy_table_next_T_28, _busy_table_next_T_30)
node _busy_table_next_T_32 = or(_busy_table_next_T_15, _busy_table_next_T_19)
node _busy_table_next_T_33 = or(_busy_table_next_T_32, _busy_table_next_T_23)
node _busy_table_next_T_34 = or(_busy_table_next_T_33, _busy_table_next_T_27)
node _busy_table_next_T_35 = or(_busy_table_next_T_34, _busy_table_next_T_31)
node busy_table_next = or(_busy_table_next_T_11, _busy_table_next_T_35)
connect busy_table, busy_table_next
node _prs1_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs1)
node prs1_match_0 = and(wakeups_0.valid, _prs1_match_T)
node _prs1_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs1)
node prs1_match_1 = and(wakeups_1.valid, _prs1_match_T_1)
node _prs1_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs1)
node prs1_match_2 = and(wakeups_2.valid, _prs1_match_T_2)
node _prs1_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs1)
node prs1_match_3 = and(wakeups_3.valid, _prs1_match_T_3)
node _prs1_match_T_4 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[0].prs1)
node prs1_match_4 = and(wakeups_4.valid, _prs1_match_T_4)
node _prs2_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs2)
node prs2_match_0 = and(wakeups_0.valid, _prs2_match_T)
node _prs2_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs2)
node prs2_match_1 = and(wakeups_1.valid, _prs2_match_T_1)
node _prs2_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs2)
node prs2_match_2 = and(wakeups_2.valid, _prs2_match_T_2)
node _prs2_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs2)
node prs2_match_3 = and(wakeups_3.valid, _prs2_match_T_3)
node _prs2_match_T_4 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[0].prs2)
node prs2_match_4 = and(wakeups_4.valid, _prs2_match_T_4)
node _prs3_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs3)
node prs3_match_0 = and(wakeups_0.valid, _prs3_match_T)
node _prs3_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs3)
node prs3_match_1 = and(wakeups_1.valid, _prs3_match_T_1)
node _prs3_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs3)
node prs3_match_2 = and(wakeups_2.valid, _prs3_match_T_2)
node _prs3_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs3)
node prs3_match_3 = and(wakeups_3.valid, _prs3_match_T_3)
node _prs3_match_T_4 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[0].prs3)
node prs3_match_4 = and(wakeups_4.valid, _prs3_match_T_4)
node _io_busy_resps_0_prs1_busy_T = dshr(busy_table, io.ren_uops[0].prs1)
node _io_busy_resps_0_prs1_busy_T_1 = bits(_io_busy_resps_0_prs1_busy_T, 0, 0)
connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_T_1
node _io_busy_resps_0_prs2_busy_T = dshr(busy_table, io.ren_uops[0].prs2)
node _io_busy_resps_0_prs2_busy_T_1 = bits(_io_busy_resps_0_prs2_busy_T, 0, 0)
connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_T_1
node _io_busy_resps_0_prs3_busy_T = dshr(busy_table, io.ren_uops[0].prs3)
node _io_busy_resps_0_prs3_busy_T_1 = bits(_io_busy_resps_0_prs3_busy_T, 0, 0)
connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_T_1
node _T = or(prs1_match_0, prs1_match_1)
node _T_1 = or(_T, prs1_match_2)
node _T_2 = or(_T_1, prs1_match_3)
node _T_3 = or(_T_2, prs1_match_4)
when _T_3 :
node _io_busy_resps_0_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_0_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_0_prs1_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_0_prs1_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_0_prs1_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_0_prs1_busy_T_7 = mux(prs1_match_0, _io_busy_resps_0_prs1_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_0_prs1_busy_T_8 = mux(prs1_match_1, _io_busy_resps_0_prs1_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_0_prs1_busy_T_9 = mux(prs1_match_2, _io_busy_resps_0_prs1_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_0_prs1_busy_T_10 = mux(prs1_match_3, _io_busy_resps_0_prs1_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_0_prs1_busy_T_11 = mux(prs1_match_4, _io_busy_resps_0_prs1_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_0_prs1_busy_T_12 = or(_io_busy_resps_0_prs1_busy_T_7, _io_busy_resps_0_prs1_busy_T_8)
node _io_busy_resps_0_prs1_busy_T_13 = or(_io_busy_resps_0_prs1_busy_T_12, _io_busy_resps_0_prs1_busy_T_9)
node _io_busy_resps_0_prs1_busy_T_14 = or(_io_busy_resps_0_prs1_busy_T_13, _io_busy_resps_0_prs1_busy_T_10)
node _io_busy_resps_0_prs1_busy_T_15 = or(_io_busy_resps_0_prs1_busy_T_14, _io_busy_resps_0_prs1_busy_T_11)
wire _io_busy_resps_0_prs1_busy_WIRE : UInt<1>
connect _io_busy_resps_0_prs1_busy_WIRE, _io_busy_resps_0_prs1_busy_T_15
connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_WIRE
node _T_4 = or(prs2_match_0, prs2_match_1)
node _T_5 = or(_T_4, prs2_match_2)
node _T_6 = or(_T_5, prs2_match_3)
node _T_7 = or(_T_6, prs2_match_4)
when _T_7 :
node _io_busy_resps_0_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_0_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_0_prs2_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_0_prs2_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_0_prs2_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_0_prs2_busy_T_7 = mux(prs2_match_0, _io_busy_resps_0_prs2_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_0_prs2_busy_T_8 = mux(prs2_match_1, _io_busy_resps_0_prs2_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_0_prs2_busy_T_9 = mux(prs2_match_2, _io_busy_resps_0_prs2_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_0_prs2_busy_T_10 = mux(prs2_match_3, _io_busy_resps_0_prs2_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_0_prs2_busy_T_11 = mux(prs2_match_4, _io_busy_resps_0_prs2_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_0_prs2_busy_T_12 = or(_io_busy_resps_0_prs2_busy_T_7, _io_busy_resps_0_prs2_busy_T_8)
node _io_busy_resps_0_prs2_busy_T_13 = or(_io_busy_resps_0_prs2_busy_T_12, _io_busy_resps_0_prs2_busy_T_9)
node _io_busy_resps_0_prs2_busy_T_14 = or(_io_busy_resps_0_prs2_busy_T_13, _io_busy_resps_0_prs2_busy_T_10)
node _io_busy_resps_0_prs2_busy_T_15 = or(_io_busy_resps_0_prs2_busy_T_14, _io_busy_resps_0_prs2_busy_T_11)
wire _io_busy_resps_0_prs2_busy_WIRE : UInt<1>
connect _io_busy_resps_0_prs2_busy_WIRE, _io_busy_resps_0_prs2_busy_T_15
connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_WIRE
node _T_8 = or(prs3_match_0, prs3_match_1)
node _T_9 = or(_T_8, prs3_match_2)
node _T_10 = or(_T_9, prs3_match_3)
node _T_11 = or(_T_10, prs3_match_4)
when _T_11 :
node _io_busy_resps_0_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_0_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_0_prs3_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_0_prs3_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_0_prs3_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_0_prs3_busy_T_7 = mux(prs3_match_0, _io_busy_resps_0_prs3_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_0_prs3_busy_T_8 = mux(prs3_match_1, _io_busy_resps_0_prs3_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_0_prs3_busy_T_9 = mux(prs3_match_2, _io_busy_resps_0_prs3_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_0_prs3_busy_T_10 = mux(prs3_match_3, _io_busy_resps_0_prs3_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_0_prs3_busy_T_11 = mux(prs3_match_4, _io_busy_resps_0_prs3_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_0_prs3_busy_T_12 = or(_io_busy_resps_0_prs3_busy_T_7, _io_busy_resps_0_prs3_busy_T_8)
node _io_busy_resps_0_prs3_busy_T_13 = or(_io_busy_resps_0_prs3_busy_T_12, _io_busy_resps_0_prs3_busy_T_9)
node _io_busy_resps_0_prs3_busy_T_14 = or(_io_busy_resps_0_prs3_busy_T_13, _io_busy_resps_0_prs3_busy_T_10)
node _io_busy_resps_0_prs3_busy_T_15 = or(_io_busy_resps_0_prs3_busy_T_14, _io_busy_resps_0_prs3_busy_T_11)
wire _io_busy_resps_0_prs3_busy_WIRE : UInt<1>
connect _io_busy_resps_0_prs3_busy_WIRE, _io_busy_resps_0_prs3_busy_T_15
connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_WIRE
connect io.busy_resps[0].prs3_busy, UInt<1>(0h0)
node _prs1_match_T_5 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs1)
node prs1_match_0_1 = and(wakeups_0.valid, _prs1_match_T_5)
node _prs1_match_T_6 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs1)
node prs1_match_1_1 = and(wakeups_1.valid, _prs1_match_T_6)
node _prs1_match_T_7 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs1)
node prs1_match_2_1 = and(wakeups_2.valid, _prs1_match_T_7)
node _prs1_match_T_8 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs1)
node prs1_match_3_1 = and(wakeups_3.valid, _prs1_match_T_8)
node _prs1_match_T_9 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[1].prs1)
node prs1_match_4_1 = and(wakeups_4.valid, _prs1_match_T_9)
node _prs2_match_T_5 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs2)
node prs2_match_0_1 = and(wakeups_0.valid, _prs2_match_T_5)
node _prs2_match_T_6 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs2)
node prs2_match_1_1 = and(wakeups_1.valid, _prs2_match_T_6)
node _prs2_match_T_7 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs2)
node prs2_match_2_1 = and(wakeups_2.valid, _prs2_match_T_7)
node _prs2_match_T_8 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs2)
node prs2_match_3_1 = and(wakeups_3.valid, _prs2_match_T_8)
node _prs2_match_T_9 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[1].prs2)
node prs2_match_4_1 = and(wakeups_4.valid, _prs2_match_T_9)
node _prs3_match_T_5 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs3)
node prs3_match_0_1 = and(wakeups_0.valid, _prs3_match_T_5)
node _prs3_match_T_6 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs3)
node prs3_match_1_1 = and(wakeups_1.valid, _prs3_match_T_6)
node _prs3_match_T_7 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs3)
node prs3_match_2_1 = and(wakeups_2.valid, _prs3_match_T_7)
node _prs3_match_T_8 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs3)
node prs3_match_3_1 = and(wakeups_3.valid, _prs3_match_T_8)
node _prs3_match_T_9 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[1].prs3)
node prs3_match_4_1 = and(wakeups_4.valid, _prs3_match_T_9)
node _io_busy_resps_1_prs1_busy_T = dshr(busy_table, io.ren_uops[1].prs1)
node _io_busy_resps_1_prs1_busy_T_1 = bits(_io_busy_resps_1_prs1_busy_T, 0, 0)
connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_T_1
node _io_busy_resps_1_prs2_busy_T = dshr(busy_table, io.ren_uops[1].prs2)
node _io_busy_resps_1_prs2_busy_T_1 = bits(_io_busy_resps_1_prs2_busy_T, 0, 0)
connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_T_1
node _io_busy_resps_1_prs3_busy_T = dshr(busy_table, io.ren_uops[1].prs3)
node _io_busy_resps_1_prs3_busy_T_1 = bits(_io_busy_resps_1_prs3_busy_T, 0, 0)
connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_T_1
node _T_12 = or(prs1_match_0_1, prs1_match_1_1)
node _T_13 = or(_T_12, prs1_match_2_1)
node _T_14 = or(_T_13, prs1_match_3_1)
node _T_15 = or(_T_14, prs1_match_4_1)
when _T_15 :
node _io_busy_resps_1_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_1_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_1_prs1_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_1_prs1_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_1_prs1_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_1_prs1_busy_T_7 = mux(prs1_match_0_1, _io_busy_resps_1_prs1_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_1_prs1_busy_T_8 = mux(prs1_match_1_1, _io_busy_resps_1_prs1_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_1_prs1_busy_T_9 = mux(prs1_match_2_1, _io_busy_resps_1_prs1_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_1_prs1_busy_T_10 = mux(prs1_match_3_1, _io_busy_resps_1_prs1_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_1_prs1_busy_T_11 = mux(prs1_match_4_1, _io_busy_resps_1_prs1_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_1_prs1_busy_T_12 = or(_io_busy_resps_1_prs1_busy_T_7, _io_busy_resps_1_prs1_busy_T_8)
node _io_busy_resps_1_prs1_busy_T_13 = or(_io_busy_resps_1_prs1_busy_T_12, _io_busy_resps_1_prs1_busy_T_9)
node _io_busy_resps_1_prs1_busy_T_14 = or(_io_busy_resps_1_prs1_busy_T_13, _io_busy_resps_1_prs1_busy_T_10)
node _io_busy_resps_1_prs1_busy_T_15 = or(_io_busy_resps_1_prs1_busy_T_14, _io_busy_resps_1_prs1_busy_T_11)
wire _io_busy_resps_1_prs1_busy_WIRE : UInt<1>
connect _io_busy_resps_1_prs1_busy_WIRE, _io_busy_resps_1_prs1_busy_T_15
connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_WIRE
node _T_16 = or(prs2_match_0_1, prs2_match_1_1)
node _T_17 = or(_T_16, prs2_match_2_1)
node _T_18 = or(_T_17, prs2_match_3_1)
node _T_19 = or(_T_18, prs2_match_4_1)
when _T_19 :
node _io_busy_resps_1_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_1_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_1_prs2_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_1_prs2_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_1_prs2_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_1_prs2_busy_T_7 = mux(prs2_match_0_1, _io_busy_resps_1_prs2_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_1_prs2_busy_T_8 = mux(prs2_match_1_1, _io_busy_resps_1_prs2_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_1_prs2_busy_T_9 = mux(prs2_match_2_1, _io_busy_resps_1_prs2_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_1_prs2_busy_T_10 = mux(prs2_match_3_1, _io_busy_resps_1_prs2_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_1_prs2_busy_T_11 = mux(prs2_match_4_1, _io_busy_resps_1_prs2_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_1_prs2_busy_T_12 = or(_io_busy_resps_1_prs2_busy_T_7, _io_busy_resps_1_prs2_busy_T_8)
node _io_busy_resps_1_prs2_busy_T_13 = or(_io_busy_resps_1_prs2_busy_T_12, _io_busy_resps_1_prs2_busy_T_9)
node _io_busy_resps_1_prs2_busy_T_14 = or(_io_busy_resps_1_prs2_busy_T_13, _io_busy_resps_1_prs2_busy_T_10)
node _io_busy_resps_1_prs2_busy_T_15 = or(_io_busy_resps_1_prs2_busy_T_14, _io_busy_resps_1_prs2_busy_T_11)
wire _io_busy_resps_1_prs2_busy_WIRE : UInt<1>
connect _io_busy_resps_1_prs2_busy_WIRE, _io_busy_resps_1_prs2_busy_T_15
connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_WIRE
node _T_20 = or(prs3_match_0_1, prs3_match_1_1)
node _T_21 = or(_T_20, prs3_match_2_1)
node _T_22 = or(_T_21, prs3_match_3_1)
node _T_23 = or(_T_22, prs3_match_4_1)
when _T_23 :
node _io_busy_resps_1_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_1_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_1_prs3_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_1_prs3_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_1_prs3_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_1_prs3_busy_T_7 = mux(prs3_match_0_1, _io_busy_resps_1_prs3_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_1_prs3_busy_T_8 = mux(prs3_match_1_1, _io_busy_resps_1_prs3_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_1_prs3_busy_T_9 = mux(prs3_match_2_1, _io_busy_resps_1_prs3_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_1_prs3_busy_T_10 = mux(prs3_match_3_1, _io_busy_resps_1_prs3_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_1_prs3_busy_T_11 = mux(prs3_match_4_1, _io_busy_resps_1_prs3_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_1_prs3_busy_T_12 = or(_io_busy_resps_1_prs3_busy_T_7, _io_busy_resps_1_prs3_busy_T_8)
node _io_busy_resps_1_prs3_busy_T_13 = or(_io_busy_resps_1_prs3_busy_T_12, _io_busy_resps_1_prs3_busy_T_9)
node _io_busy_resps_1_prs3_busy_T_14 = or(_io_busy_resps_1_prs3_busy_T_13, _io_busy_resps_1_prs3_busy_T_10)
node _io_busy_resps_1_prs3_busy_T_15 = or(_io_busy_resps_1_prs3_busy_T_14, _io_busy_resps_1_prs3_busy_T_11)
wire _io_busy_resps_1_prs3_busy_WIRE : UInt<1>
connect _io_busy_resps_1_prs3_busy_WIRE, _io_busy_resps_1_prs3_busy_T_15
connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_WIRE
connect io.busy_resps[1].prs3_busy, UInt<1>(0h0)
node _prs1_match_T_10 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[2].prs1)
node prs1_match_0_2 = and(wakeups_0.valid, _prs1_match_T_10)
node _prs1_match_T_11 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[2].prs1)
node prs1_match_1_2 = and(wakeups_1.valid, _prs1_match_T_11)
node _prs1_match_T_12 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[2].prs1)
node prs1_match_2_2 = and(wakeups_2.valid, _prs1_match_T_12)
node _prs1_match_T_13 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[2].prs1)
node prs1_match_3_2 = and(wakeups_3.valid, _prs1_match_T_13)
node _prs1_match_T_14 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[2].prs1)
node prs1_match_4_2 = and(wakeups_4.valid, _prs1_match_T_14)
node _prs2_match_T_10 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[2].prs2)
node prs2_match_0_2 = and(wakeups_0.valid, _prs2_match_T_10)
node _prs2_match_T_11 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[2].prs2)
node prs2_match_1_2 = and(wakeups_1.valid, _prs2_match_T_11)
node _prs2_match_T_12 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[2].prs2)
node prs2_match_2_2 = and(wakeups_2.valid, _prs2_match_T_12)
node _prs2_match_T_13 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[2].prs2)
node prs2_match_3_2 = and(wakeups_3.valid, _prs2_match_T_13)
node _prs2_match_T_14 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[2].prs2)
node prs2_match_4_2 = and(wakeups_4.valid, _prs2_match_T_14)
node _prs3_match_T_10 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[2].prs3)
node prs3_match_0_2 = and(wakeups_0.valid, _prs3_match_T_10)
node _prs3_match_T_11 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[2].prs3)
node prs3_match_1_2 = and(wakeups_1.valid, _prs3_match_T_11)
node _prs3_match_T_12 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[2].prs3)
node prs3_match_2_2 = and(wakeups_2.valid, _prs3_match_T_12)
node _prs3_match_T_13 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[2].prs3)
node prs3_match_3_2 = and(wakeups_3.valid, _prs3_match_T_13)
node _prs3_match_T_14 = eq(wakeups_4.bits.uop.pdst, io.ren_uops[2].prs3)
node prs3_match_4_2 = and(wakeups_4.valid, _prs3_match_T_14)
node _io_busy_resps_2_prs1_busy_T = dshr(busy_table, io.ren_uops[2].prs1)
node _io_busy_resps_2_prs1_busy_T_1 = bits(_io_busy_resps_2_prs1_busy_T, 0, 0)
connect io.busy_resps[2].prs1_busy, _io_busy_resps_2_prs1_busy_T_1
node _io_busy_resps_2_prs2_busy_T = dshr(busy_table, io.ren_uops[2].prs2)
node _io_busy_resps_2_prs2_busy_T_1 = bits(_io_busy_resps_2_prs2_busy_T, 0, 0)
connect io.busy_resps[2].prs2_busy, _io_busy_resps_2_prs2_busy_T_1
node _io_busy_resps_2_prs3_busy_T = dshr(busy_table, io.ren_uops[2].prs3)
node _io_busy_resps_2_prs3_busy_T_1 = bits(_io_busy_resps_2_prs3_busy_T, 0, 0)
connect io.busy_resps[2].prs3_busy, _io_busy_resps_2_prs3_busy_T_1
node _T_24 = or(prs1_match_0_2, prs1_match_1_2)
node _T_25 = or(_T_24, prs1_match_2_2)
node _T_26 = or(_T_25, prs1_match_3_2)
node _T_27 = or(_T_26, prs1_match_4_2)
when _T_27 :
node _io_busy_resps_2_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_2_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_2_prs1_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_2_prs1_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_2_prs1_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_2_prs1_busy_T_7 = mux(prs1_match_0_2, _io_busy_resps_2_prs1_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_2_prs1_busy_T_8 = mux(prs1_match_1_2, _io_busy_resps_2_prs1_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_2_prs1_busy_T_9 = mux(prs1_match_2_2, _io_busy_resps_2_prs1_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_2_prs1_busy_T_10 = mux(prs1_match_3_2, _io_busy_resps_2_prs1_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_2_prs1_busy_T_11 = mux(prs1_match_4_2, _io_busy_resps_2_prs1_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_2_prs1_busy_T_12 = or(_io_busy_resps_2_prs1_busy_T_7, _io_busy_resps_2_prs1_busy_T_8)
node _io_busy_resps_2_prs1_busy_T_13 = or(_io_busy_resps_2_prs1_busy_T_12, _io_busy_resps_2_prs1_busy_T_9)
node _io_busy_resps_2_prs1_busy_T_14 = or(_io_busy_resps_2_prs1_busy_T_13, _io_busy_resps_2_prs1_busy_T_10)
node _io_busy_resps_2_prs1_busy_T_15 = or(_io_busy_resps_2_prs1_busy_T_14, _io_busy_resps_2_prs1_busy_T_11)
wire _io_busy_resps_2_prs1_busy_WIRE : UInt<1>
connect _io_busy_resps_2_prs1_busy_WIRE, _io_busy_resps_2_prs1_busy_T_15
connect io.busy_resps[2].prs1_busy, _io_busy_resps_2_prs1_busy_WIRE
node _T_28 = or(prs2_match_0_2, prs2_match_1_2)
node _T_29 = or(_T_28, prs2_match_2_2)
node _T_30 = or(_T_29, prs2_match_3_2)
node _T_31 = or(_T_30, prs2_match_4_2)
when _T_31 :
node _io_busy_resps_2_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_2_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_2_prs2_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_2_prs2_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_2_prs2_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_2_prs2_busy_T_7 = mux(prs2_match_0_2, _io_busy_resps_2_prs2_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_2_prs2_busy_T_8 = mux(prs2_match_1_2, _io_busy_resps_2_prs2_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_2_prs2_busy_T_9 = mux(prs2_match_2_2, _io_busy_resps_2_prs2_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_2_prs2_busy_T_10 = mux(prs2_match_3_2, _io_busy_resps_2_prs2_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_2_prs2_busy_T_11 = mux(prs2_match_4_2, _io_busy_resps_2_prs2_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_2_prs2_busy_T_12 = or(_io_busy_resps_2_prs2_busy_T_7, _io_busy_resps_2_prs2_busy_T_8)
node _io_busy_resps_2_prs2_busy_T_13 = or(_io_busy_resps_2_prs2_busy_T_12, _io_busy_resps_2_prs2_busy_T_9)
node _io_busy_resps_2_prs2_busy_T_14 = or(_io_busy_resps_2_prs2_busy_T_13, _io_busy_resps_2_prs2_busy_T_10)
node _io_busy_resps_2_prs2_busy_T_15 = or(_io_busy_resps_2_prs2_busy_T_14, _io_busy_resps_2_prs2_busy_T_11)
wire _io_busy_resps_2_prs2_busy_WIRE : UInt<1>
connect _io_busy_resps_2_prs2_busy_WIRE, _io_busy_resps_2_prs2_busy_T_15
connect io.busy_resps[2].prs2_busy, _io_busy_resps_2_prs2_busy_WIRE
node _T_32 = or(prs3_match_0_2, prs3_match_1_2)
node _T_33 = or(_T_32, prs3_match_2_2)
node _T_34 = or(_T_33, prs3_match_3_2)
node _T_35 = or(_T_34, prs3_match_4_2)
when _T_35 :
node _io_busy_resps_2_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy)
node _io_busy_resps_2_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy)
node _io_busy_resps_2_prs3_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy)
node _io_busy_resps_2_prs3_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy)
node _io_busy_resps_2_prs3_busy_T_6 = and(wakeups_4.valid, wakeups_4.bits.rebusy)
node _io_busy_resps_2_prs3_busy_T_7 = mux(prs3_match_0_2, _io_busy_resps_2_prs3_busy_T_2, UInt<1>(0h0))
node _io_busy_resps_2_prs3_busy_T_8 = mux(prs3_match_1_2, _io_busy_resps_2_prs3_busy_T_3, UInt<1>(0h0))
node _io_busy_resps_2_prs3_busy_T_9 = mux(prs3_match_2_2, _io_busy_resps_2_prs3_busy_T_4, UInt<1>(0h0))
node _io_busy_resps_2_prs3_busy_T_10 = mux(prs3_match_3_2, _io_busy_resps_2_prs3_busy_T_5, UInt<1>(0h0))
node _io_busy_resps_2_prs3_busy_T_11 = mux(prs3_match_4_2, _io_busy_resps_2_prs3_busy_T_6, UInt<1>(0h0))
node _io_busy_resps_2_prs3_busy_T_12 = or(_io_busy_resps_2_prs3_busy_T_7, _io_busy_resps_2_prs3_busy_T_8)
node _io_busy_resps_2_prs3_busy_T_13 = or(_io_busy_resps_2_prs3_busy_T_12, _io_busy_resps_2_prs3_busy_T_9)
node _io_busy_resps_2_prs3_busy_T_14 = or(_io_busy_resps_2_prs3_busy_T_13, _io_busy_resps_2_prs3_busy_T_10)
node _io_busy_resps_2_prs3_busy_T_15 = or(_io_busy_resps_2_prs3_busy_T_14, _io_busy_resps_2_prs3_busy_T_11)
wire _io_busy_resps_2_prs3_busy_WIRE : UInt<1>
connect _io_busy_resps_2_prs3_busy_WIRE, _io_busy_resps_2_prs3_busy_T_15
connect io.busy_resps[2].prs3_busy, _io_busy_resps_2_prs3_busy_WIRE
connect io.busy_resps[2].prs3_busy, UInt<1>(0h0)
connect io.debug.busytable, busy_table | module RenameBusyTable( // @[rename-busytable.scala:27:7]
input clock, // @[rename-busytable.scala:27:7]
input reset, // @[rename-busytable.scala:27:7]
input [31:0] io_ren_uops_0_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_ren_uops_0_debug_inst, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_ren_uops_0_debug_pc, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iq_type_0, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iq_type_1, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iq_type_2, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iq_type_3, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_0, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_1, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_2, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_3, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_4, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_5, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_6, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_7, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_8, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fu_code_9, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iw_issued, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iw_issued_partial_agen, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_ren_uops_0_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_ren_uops_0_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_ren_uops_0_br_type, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_sfb, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_fence, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_fencei, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_sfence, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_amo, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_eret, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_rocc, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_0_ftq_idx, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_0_pc_lob, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_taken, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_0_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_ren_uops_0_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_op2_sel, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_0_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_0_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_0_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_0_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_0_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_0_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_0_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_0_ppred, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_prs1_busy, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_prs2_busy, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_0_stale_pdst, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_ren_uops_0_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_0_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_mem_size, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_mem_signed, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_uses_ldq, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_uses_stq, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_is_unique, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_csr_cmd, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_0_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_0_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_0_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_0_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_frs3_en, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_0_fcn_op, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_0_fp_typ, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_0_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_0_debug_tsrc, // @[rename-busytable.scala:36:14]
input [31:0] io_ren_uops_1_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_ren_uops_1_debug_inst, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_ren_uops_1_debug_pc, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iq_type_0, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iq_type_1, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iq_type_2, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iq_type_3, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_0, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_1, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_2, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_3, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_4, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_5, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_6, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_7, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_8, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fu_code_9, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iw_issued, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iw_issued_partial_agen, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_ren_uops_1_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_ren_uops_1_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_ren_uops_1_br_type, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_sfb, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_fence, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_fencei, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_sfence, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_amo, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_eret, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_rocc, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_1_ftq_idx, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_1_pc_lob, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_taken, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_1_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_ren_uops_1_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_op2_sel, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_1_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_1_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_1_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_1_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_1_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_1_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_1_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_1_ppred, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_prs1_busy, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_prs2_busy, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_1_stale_pdst, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_ren_uops_1_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_1_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_mem_size, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_mem_signed, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_uses_ldq, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_uses_stq, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_is_unique, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_csr_cmd, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_1_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_1_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_1_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_1_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_frs3_en, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_1_fcn_op, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_1_fp_typ, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_1_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_1_debug_tsrc, // @[rename-busytable.scala:36:14]
input [31:0] io_ren_uops_2_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_ren_uops_2_debug_inst, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_ren_uops_2_debug_pc, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iq_type_0, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iq_type_1, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iq_type_2, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iq_type_3, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_0, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_1, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_2, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_3, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_4, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_5, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_6, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_7, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_8, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fu_code_9, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iw_issued, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iw_issued_partial_agen, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_ren_uops_2_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_ren_uops_2_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_ren_uops_2_br_type, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_sfb, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_fence, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_fencei, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_sfence, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_amo, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_eret, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_rocc, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_2_ftq_idx, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_2_pc_lob, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_taken, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_2_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_ren_uops_2_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_op2_sel, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_2_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_2_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_2_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_2_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_2_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_2_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_2_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_2_ppred, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_prs1_busy, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_prs2_busy, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_ren_uops_2_stale_pdst, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_ren_uops_2_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_2_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_mem_size, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_mem_signed, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_uses_ldq, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_uses_stq, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_is_unique, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_csr_cmd, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_2_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_2_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_2_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_ren_uops_2_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_frs3_en, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_ren_uops_2_fcn_op, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_ren_uops_2_fp_typ, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_ren_uops_2_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_ren_uops_2_debug_tsrc, // @[rename-busytable.scala:36:14]
output io_busy_resps_0_prs1_busy, // @[rename-busytable.scala:36:14]
output io_busy_resps_0_prs2_busy, // @[rename-busytable.scala:36:14]
output io_busy_resps_1_prs1_busy, // @[rename-busytable.scala:36:14]
output io_busy_resps_1_prs2_busy, // @[rename-busytable.scala:36:14]
output io_busy_resps_2_prs1_busy, // @[rename-busytable.scala:36:14]
output io_busy_resps_2_prs2_busy, // @[rename-busytable.scala:36:14]
input io_rebusy_reqs_0, // @[rename-busytable.scala:36:14]
input io_rebusy_reqs_1, // @[rename-busytable.scala:36:14]
input io_rebusy_reqs_2, // @[rename-busytable.scala:36:14]
input io_wakeups_0_valid, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iw_issued, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_wakeups_0_bits_uop_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_0_bits_uop_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_0_bits_uop_br_type, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_sfb, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_fence, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_fencei, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_sfence, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_amo, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_eret, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_rocc, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_taken, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_0_bits_uop_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_op2_sel, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_0_bits_uop_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_0_bits_uop_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_0_bits_uop_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_0_bits_uop_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_0_bits_uop_ppred, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_mem_signed, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_uses_stq, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_is_unique, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_frs3_en, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_0_bits_uop_fcn_op, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_0_bits_uop_fp_typ, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_bypassable, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_0_bits_speculative_mask, // @[rename-busytable.scala:36:14]
input io_wakeups_0_bits_rebusy, // @[rename-busytable.scala:36:14]
input io_wakeups_1_valid, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iw_issued, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_wakeups_1_bits_uop_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_1_bits_uop_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_1_bits_uop_br_type, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_sfb, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_fence, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_fencei, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_sfence, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_amo, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_eret, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_rocc, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_taken, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_1_bits_uop_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_op2_sel, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_1_bits_uop_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_1_bits_uop_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_1_bits_uop_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_1_bits_uop_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_1_bits_uop_ppred, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_mem_signed, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_uses_stq, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_is_unique, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_frs3_en, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_1_bits_uop_fcn_op, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_1_bits_uop_fp_typ, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_1_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14]
input io_wakeups_2_valid, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_2_bits_uop_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_2_bits_uop_debug_inst, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_wakeups_2_bits_uop_debug_pc, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iw_issued, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_wakeups_2_bits_uop_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_2_bits_uop_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_2_bits_uop_br_type, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_sfb, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_fence, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_fencei, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_sfence, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_amo, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_eret, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_rocc, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_2_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_2_bits_uop_pc_lob, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_taken, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_2_bits_uop_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_wakeups_2_bits_uop_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_op2_sel, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_2_bits_uop_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_2_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_2_bits_uop_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_2_bits_uop_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_2_bits_uop_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_2_bits_uop_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_2_bits_uop_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_2_bits_uop_ppred, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_2_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_wakeups_2_bits_uop_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_2_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_mem_size, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_mem_signed, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_uses_stq, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_is_unique, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_2_bits_uop_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_2_bits_uop_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_2_bits_uop_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_2_bits_uop_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_frs3_en, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_2_bits_uop_fcn_op, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_2_bits_uop_fp_typ, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_wakeups_2_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_2_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14]
input io_wakeups_3_valid, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_3_bits_uop_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_3_bits_uop_debug_inst, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_wakeups_3_bits_uop_debug_pc, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iw_issued, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_wakeups_3_bits_uop_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_3_bits_uop_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_3_bits_uop_br_type, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_sfb, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_fence, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_fencei, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_sfence, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_amo, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_eret, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_rocc, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_3_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_3_bits_uop_pc_lob, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_taken, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_3_bits_uop_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_wakeups_3_bits_uop_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_op2_sel, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_3_bits_uop_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_3_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_3_bits_uop_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_3_bits_uop_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_3_bits_uop_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_3_bits_uop_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_3_bits_uop_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_3_bits_uop_ppred, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_3_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_wakeups_3_bits_uop_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_3_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_mem_size, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_mem_signed, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_uses_stq, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_is_unique, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_3_bits_uop_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_3_bits_uop_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_3_bits_uop_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_3_bits_uop_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_frs3_en, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_3_bits_uop_fcn_op, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_3_bits_uop_fp_typ, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_wakeups_3_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_3_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14]
input io_wakeups_4_valid, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_4_bits_uop_inst, // @[rename-busytable.scala:36:14]
input [31:0] io_wakeups_4_bits_uop_debug_inst, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_rvc, // @[rename-busytable.scala:36:14]
input [39:0] io_wakeups_4_bits_uop_debug_pc, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iw_issued, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14]
input [15:0] io_wakeups_4_bits_uop_br_mask, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_4_bits_uop_br_tag, // @[rename-busytable.scala:36:14]
input [3:0] io_wakeups_4_bits_uop_br_type, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_sfb, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_fence, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_fencei, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_sfence, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_amo, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_eret, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_rocc, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_mov, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_4_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_edge_inst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_4_bits_uop_pc_lob, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_taken, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_imm_rename, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_imm_sel, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_4_bits_uop_pimm, // @[rename-busytable.scala:36:14]
input [19:0] io_wakeups_4_bits_uop_imm_packed, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_op1_sel, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_op2_sel, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_4_bits_uop_rob_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_4_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_4_bits_uop_stq_idx, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_4_bits_uop_pdst, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_4_bits_uop_prs1, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_4_bits_uop_prs2, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_4_bits_uop_prs3, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_4_bits_uop_ppred, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14]
input [6:0] io_wakeups_4_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_exception, // @[rename-busytable.scala:36:14]
input [63:0] io_wakeups_4_bits_uop_exc_cause, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_4_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_mem_size, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_mem_signed, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_uses_stq, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_is_unique, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_4_bits_uop_ldst, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_4_bits_uop_lrs1, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_4_bits_uop_lrs2, // @[rename-busytable.scala:36:14]
input [5:0] io_wakeups_4_bits_uop_lrs3, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_frs3_en, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14]
input [4:0] io_wakeups_4_bits_uop_fcn_op, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_fp_val, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_fp_rm, // @[rename-busytable.scala:36:14]
input [1:0] io_wakeups_4_bits_uop_fp_typ, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14]
input io_wakeups_4_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_wakeups_4_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14]
input [2:0] io_child_rebusys // @[rename-busytable.scala:36:14]
);
wire wakeups_4_valid; // @[rename-busytable.scala:47:18]
wire wakeups_3_valid; // @[rename-busytable.scala:47:18]
wire wakeups_2_valid; // @[rename-busytable.scala:47:18]
wire wakeups_1_valid; // @[rename-busytable.scala:47:18]
wire [31:0] io_ren_uops_0_inst_0 = io_ren_uops_0_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_ren_uops_0_debug_inst_0 = io_ren_uops_0_debug_inst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_rvc_0 = io_ren_uops_0_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_ren_uops_0_debug_pc_0 = io_ren_uops_0_debug_pc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iq_type_0_0 = io_ren_uops_0_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iq_type_1_0 = io_ren_uops_0_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iq_type_2_0 = io_ren_uops_0_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iq_type_3_0 = io_ren_uops_0_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_0_0 = io_ren_uops_0_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_1_0 = io_ren_uops_0_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_2_0 = io_ren_uops_0_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_3_0 = io_ren_uops_0_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_4_0 = io_ren_uops_0_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_5_0 = io_ren_uops_0_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_6_0 = io_ren_uops_0_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_7_0 = io_ren_uops_0_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_8_0 = io_ren_uops_0_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fu_code_9_0 = io_ren_uops_0_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_issued_0 = io_ren_uops_0_iw_issued; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_issued_partial_agen_0 = io_ren_uops_0_iw_issued_partial_agen; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_issued_partial_dgen_0 = io_ren_uops_0_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_iw_p1_speculative_child_0 = io_ren_uops_0_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_iw_p2_speculative_child_0 = io_ren_uops_0_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_p1_bypass_hint_0 = io_ren_uops_0_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_p2_bypass_hint_0 = io_ren_uops_0_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_p3_bypass_hint_0 = io_ren_uops_0_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_dis_col_sel_0 = io_ren_uops_0_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_ren_uops_0_br_mask_0 = io_ren_uops_0_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_0_br_tag_0 = io_ren_uops_0_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_0_br_type_0 = io_ren_uops_0_br_type; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_sfb_0 = io_ren_uops_0_is_sfb; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_fence_0 = io_ren_uops_0_is_fence; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_fencei_0 = io_ren_uops_0_is_fencei; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_sfence_0 = io_ren_uops_0_is_sfence; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_amo_0 = io_ren_uops_0_is_amo; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_eret_0 = io_ren_uops_0_is_eret; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_sys_pc2epc_0 = io_ren_uops_0_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_rocc_0 = io_ren_uops_0_is_rocc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_mov_0 = io_ren_uops_0_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_ftq_idx_0 = io_ren_uops_0_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_edge_inst_0 = io_ren_uops_0_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_pc_lob_0 = io_ren_uops_0_pc_lob; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_taken_0 = io_ren_uops_0_taken; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_imm_rename_0 = io_ren_uops_0_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_imm_sel_0 = io_ren_uops_0_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_pimm_0 = io_ren_uops_0_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_ren_uops_0_imm_packed_0 = io_ren_uops_0_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_op1_sel_0 = io_ren_uops_0_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_op2_sel_0 = io_ren_uops_0_op2_sel; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_ldst_0 = io_ren_uops_0_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_wen_0 = io_ren_uops_0_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_ren1_0 = io_ren_uops_0_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_ren2_0 = io_ren_uops_0_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_ren3_0 = io_ren_uops_0_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_swap12_0 = io_ren_uops_0_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_swap23_0 = io_ren_uops_0_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_fp_ctrl_typeTagIn_0 = io_ren_uops_0_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_fp_ctrl_typeTagOut_0 = io_ren_uops_0_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_fromint_0 = io_ren_uops_0_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_toint_0 = io_ren_uops_0_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_fastpipe_0 = io_ren_uops_0_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_fma_0 = io_ren_uops_0_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_div_0 = io_ren_uops_0_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_sqrt_0 = io_ren_uops_0_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_wflags_0 = io_ren_uops_0_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_ctrl_vec_0 = io_ren_uops_0_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_0_rob_idx_0 = io_ren_uops_0_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_ldq_idx_0 = io_ren_uops_0_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_stq_idx_0 = io_ren_uops_0_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_rxq_idx_0 = io_ren_uops_0_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_0_pdst_0 = io_ren_uops_0_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_0_prs1_0 = io_ren_uops_0_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_0_prs2_0 = io_ren_uops_0_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_0_prs3_0 = io_ren_uops_0_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_ppred_0 = io_ren_uops_0_ppred; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_prs1_busy_0 = io_ren_uops_0_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_prs2_busy_0 = io_ren_uops_0_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ppred_busy_0 = io_ren_uops_0_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_0_stale_pdst_0 = io_ren_uops_0_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_exception_0 = io_ren_uops_0_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_ren_uops_0_exc_cause_0 = io_ren_uops_0_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_mem_cmd_0 = io_ren_uops_0_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_mem_size_0 = io_ren_uops_0_mem_size; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_mem_signed_0 = io_ren_uops_0_mem_signed; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_uses_ldq_0 = io_ren_uops_0_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_uses_stq_0 = io_ren_uops_0_uses_stq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_unique_0 = io_ren_uops_0_is_unique; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_flush_on_commit_0 = io_ren_uops_0_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_csr_cmd_0 = io_ren_uops_0_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ldst_is_rs1_0 = io_ren_uops_0_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_ldst_0 = io_ren_uops_0_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_lrs1_0 = io_ren_uops_0_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_lrs2_0 = io_ren_uops_0_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_lrs3_0 = io_ren_uops_0_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_dst_rtype_0 = io_ren_uops_0_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_lrs1_rtype_0 = io_ren_uops_0_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_lrs2_rtype_0 = io_ren_uops_0_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_frs3_en_0 = io_ren_uops_0_frs3_en; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fcn_dw_0 = io_ren_uops_0_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_fcn_op_0 = io_ren_uops_0_fcn_op; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_val_0 = io_ren_uops_0_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_fp_rm_0 = io_ren_uops_0_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_fp_typ_0 = io_ren_uops_0_fp_typ; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_xcpt_pf_if_0 = io_ren_uops_0_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_xcpt_ae_if_0 = io_ren_uops_0_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_xcpt_ma_if_0 = io_ren_uops_0_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_bp_debug_if_0 = io_ren_uops_0_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_bp_xcpt_if_0 = io_ren_uops_0_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_debug_fsrc_0 = io_ren_uops_0_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_debug_tsrc_0 = io_ren_uops_0_debug_tsrc; // @[rename-busytable.scala:27:7]
wire [31:0] io_ren_uops_1_inst_0 = io_ren_uops_1_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_ren_uops_1_debug_inst_0 = io_ren_uops_1_debug_inst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_rvc_0 = io_ren_uops_1_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_ren_uops_1_debug_pc_0 = io_ren_uops_1_debug_pc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iq_type_0_0 = io_ren_uops_1_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iq_type_1_0 = io_ren_uops_1_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iq_type_2_0 = io_ren_uops_1_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iq_type_3_0 = io_ren_uops_1_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_0_0 = io_ren_uops_1_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_1_0 = io_ren_uops_1_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_2_0 = io_ren_uops_1_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_3_0 = io_ren_uops_1_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_4_0 = io_ren_uops_1_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_5_0 = io_ren_uops_1_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_6_0 = io_ren_uops_1_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_7_0 = io_ren_uops_1_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_8_0 = io_ren_uops_1_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fu_code_9_0 = io_ren_uops_1_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iw_issued_0 = io_ren_uops_1_iw_issued; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iw_issued_partial_agen_0 = io_ren_uops_1_iw_issued_partial_agen; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iw_issued_partial_dgen_0 = io_ren_uops_1_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_iw_p1_speculative_child_0 = io_ren_uops_1_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_iw_p2_speculative_child_0 = io_ren_uops_1_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iw_p1_bypass_hint_0 = io_ren_uops_1_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iw_p2_bypass_hint_0 = io_ren_uops_1_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_iw_p3_bypass_hint_0 = io_ren_uops_1_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_dis_col_sel_0 = io_ren_uops_1_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_ren_uops_1_br_mask_0 = io_ren_uops_1_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_1_br_tag_0 = io_ren_uops_1_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_1_br_type_0 = io_ren_uops_1_br_type; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_sfb_0 = io_ren_uops_1_is_sfb; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_fence_0 = io_ren_uops_1_is_fence; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_fencei_0 = io_ren_uops_1_is_fencei; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_sfence_0 = io_ren_uops_1_is_sfence; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_amo_0 = io_ren_uops_1_is_amo; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_eret_0 = io_ren_uops_1_is_eret; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_sys_pc2epc_0 = io_ren_uops_1_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_rocc_0 = io_ren_uops_1_is_rocc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_mov_0 = io_ren_uops_1_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_1_ftq_idx_0 = io_ren_uops_1_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_edge_inst_0 = io_ren_uops_1_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_1_pc_lob_0 = io_ren_uops_1_pc_lob; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_taken_0 = io_ren_uops_1_taken; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_imm_rename_0 = io_ren_uops_1_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_imm_sel_0 = io_ren_uops_1_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_1_pimm_0 = io_ren_uops_1_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_ren_uops_1_imm_packed_0 = io_ren_uops_1_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_op1_sel_0 = io_ren_uops_1_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_op2_sel_0 = io_ren_uops_1_op2_sel; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_ldst_0 = io_ren_uops_1_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_wen_0 = io_ren_uops_1_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_ren1_0 = io_ren_uops_1_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_ren2_0 = io_ren_uops_1_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_ren3_0 = io_ren_uops_1_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_swap12_0 = io_ren_uops_1_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_swap23_0 = io_ren_uops_1_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_fp_ctrl_typeTagIn_0 = io_ren_uops_1_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_fp_ctrl_typeTagOut_0 = io_ren_uops_1_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_fromint_0 = io_ren_uops_1_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_toint_0 = io_ren_uops_1_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_fastpipe_0 = io_ren_uops_1_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_fma_0 = io_ren_uops_1_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_div_0 = io_ren_uops_1_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_sqrt_0 = io_ren_uops_1_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_wflags_0 = io_ren_uops_1_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_ctrl_vec_0 = io_ren_uops_1_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_1_rob_idx_0 = io_ren_uops_1_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_1_ldq_idx_0 = io_ren_uops_1_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_1_stq_idx_0 = io_ren_uops_1_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_rxq_idx_0 = io_ren_uops_1_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_1_pdst_0 = io_ren_uops_1_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_1_prs1_0 = io_ren_uops_1_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_1_prs2_0 = io_ren_uops_1_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_1_prs3_0 = io_ren_uops_1_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_1_ppred_0 = io_ren_uops_1_ppred; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_prs1_busy_0 = io_ren_uops_1_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_prs2_busy_0 = io_ren_uops_1_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_ppred_busy_0 = io_ren_uops_1_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_1_stale_pdst_0 = io_ren_uops_1_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_exception_0 = io_ren_uops_1_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_ren_uops_1_exc_cause_0 = io_ren_uops_1_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_1_mem_cmd_0 = io_ren_uops_1_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_mem_size_0 = io_ren_uops_1_mem_size; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_mem_signed_0 = io_ren_uops_1_mem_signed; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_uses_ldq_0 = io_ren_uops_1_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_uses_stq_0 = io_ren_uops_1_uses_stq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_is_unique_0 = io_ren_uops_1_is_unique; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_flush_on_commit_0 = io_ren_uops_1_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_csr_cmd_0 = io_ren_uops_1_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_ldst_is_rs1_0 = io_ren_uops_1_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_1_ldst_0 = io_ren_uops_1_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_1_lrs1_0 = io_ren_uops_1_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_1_lrs2_0 = io_ren_uops_1_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_1_lrs3_0 = io_ren_uops_1_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_dst_rtype_0 = io_ren_uops_1_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_lrs1_rtype_0 = io_ren_uops_1_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_lrs2_rtype_0 = io_ren_uops_1_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_frs3_en_0 = io_ren_uops_1_frs3_en; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fcn_dw_0 = io_ren_uops_1_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_1_fcn_op_0 = io_ren_uops_1_fcn_op; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_fp_val_0 = io_ren_uops_1_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_fp_rm_0 = io_ren_uops_1_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_1_fp_typ_0 = io_ren_uops_1_fp_typ; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_xcpt_pf_if_0 = io_ren_uops_1_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_xcpt_ae_if_0 = io_ren_uops_1_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_xcpt_ma_if_0 = io_ren_uops_1_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_bp_debug_if_0 = io_ren_uops_1_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_bp_xcpt_if_0 = io_ren_uops_1_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_debug_fsrc_0 = io_ren_uops_1_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_1_debug_tsrc_0 = io_ren_uops_1_debug_tsrc; // @[rename-busytable.scala:27:7]
wire [31:0] io_ren_uops_2_inst_0 = io_ren_uops_2_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_ren_uops_2_debug_inst_0 = io_ren_uops_2_debug_inst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_rvc_0 = io_ren_uops_2_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_ren_uops_2_debug_pc_0 = io_ren_uops_2_debug_pc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iq_type_0_0 = io_ren_uops_2_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iq_type_1_0 = io_ren_uops_2_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iq_type_2_0 = io_ren_uops_2_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iq_type_3_0 = io_ren_uops_2_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_0_0 = io_ren_uops_2_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_1_0 = io_ren_uops_2_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_2_0 = io_ren_uops_2_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_3_0 = io_ren_uops_2_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_4_0 = io_ren_uops_2_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_5_0 = io_ren_uops_2_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_6_0 = io_ren_uops_2_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_7_0 = io_ren_uops_2_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_8_0 = io_ren_uops_2_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fu_code_9_0 = io_ren_uops_2_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iw_issued_0 = io_ren_uops_2_iw_issued; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iw_issued_partial_agen_0 = io_ren_uops_2_iw_issued_partial_agen; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iw_issued_partial_dgen_0 = io_ren_uops_2_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_iw_p1_speculative_child_0 = io_ren_uops_2_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_iw_p2_speculative_child_0 = io_ren_uops_2_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iw_p1_bypass_hint_0 = io_ren_uops_2_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iw_p2_bypass_hint_0 = io_ren_uops_2_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_iw_p3_bypass_hint_0 = io_ren_uops_2_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_dis_col_sel_0 = io_ren_uops_2_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_ren_uops_2_br_mask_0 = io_ren_uops_2_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_2_br_tag_0 = io_ren_uops_2_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_2_br_type_0 = io_ren_uops_2_br_type; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_sfb_0 = io_ren_uops_2_is_sfb; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_fence_0 = io_ren_uops_2_is_fence; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_fencei_0 = io_ren_uops_2_is_fencei; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_sfence_0 = io_ren_uops_2_is_sfence; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_amo_0 = io_ren_uops_2_is_amo; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_eret_0 = io_ren_uops_2_is_eret; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_sys_pc2epc_0 = io_ren_uops_2_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_rocc_0 = io_ren_uops_2_is_rocc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_mov_0 = io_ren_uops_2_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_2_ftq_idx_0 = io_ren_uops_2_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_edge_inst_0 = io_ren_uops_2_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_2_pc_lob_0 = io_ren_uops_2_pc_lob; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_taken_0 = io_ren_uops_2_taken; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_imm_rename_0 = io_ren_uops_2_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_imm_sel_0 = io_ren_uops_2_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_2_pimm_0 = io_ren_uops_2_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_ren_uops_2_imm_packed_0 = io_ren_uops_2_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_op1_sel_0 = io_ren_uops_2_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_op2_sel_0 = io_ren_uops_2_op2_sel; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_ldst_0 = io_ren_uops_2_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_wen_0 = io_ren_uops_2_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_ren1_0 = io_ren_uops_2_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_ren2_0 = io_ren_uops_2_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_ren3_0 = io_ren_uops_2_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_swap12_0 = io_ren_uops_2_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_swap23_0 = io_ren_uops_2_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_fp_ctrl_typeTagIn_0 = io_ren_uops_2_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_fp_ctrl_typeTagOut_0 = io_ren_uops_2_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_fromint_0 = io_ren_uops_2_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_toint_0 = io_ren_uops_2_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_fastpipe_0 = io_ren_uops_2_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_fma_0 = io_ren_uops_2_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_div_0 = io_ren_uops_2_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_sqrt_0 = io_ren_uops_2_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_wflags_0 = io_ren_uops_2_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_ctrl_vec_0 = io_ren_uops_2_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_2_rob_idx_0 = io_ren_uops_2_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_2_ldq_idx_0 = io_ren_uops_2_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_2_stq_idx_0 = io_ren_uops_2_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_rxq_idx_0 = io_ren_uops_2_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_2_pdst_0 = io_ren_uops_2_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_2_prs1_0 = io_ren_uops_2_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_2_prs2_0 = io_ren_uops_2_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_2_prs3_0 = io_ren_uops_2_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_2_ppred_0 = io_ren_uops_2_ppred; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_prs1_busy_0 = io_ren_uops_2_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_prs2_busy_0 = io_ren_uops_2_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_ppred_busy_0 = io_ren_uops_2_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_ren_uops_2_stale_pdst_0 = io_ren_uops_2_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_exception_0 = io_ren_uops_2_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_ren_uops_2_exc_cause_0 = io_ren_uops_2_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_2_mem_cmd_0 = io_ren_uops_2_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_mem_size_0 = io_ren_uops_2_mem_size; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_mem_signed_0 = io_ren_uops_2_mem_signed; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_uses_ldq_0 = io_ren_uops_2_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_uses_stq_0 = io_ren_uops_2_uses_stq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_is_unique_0 = io_ren_uops_2_is_unique; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_flush_on_commit_0 = io_ren_uops_2_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_csr_cmd_0 = io_ren_uops_2_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_ldst_is_rs1_0 = io_ren_uops_2_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_2_ldst_0 = io_ren_uops_2_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_2_lrs1_0 = io_ren_uops_2_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_2_lrs2_0 = io_ren_uops_2_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_2_lrs3_0 = io_ren_uops_2_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_dst_rtype_0 = io_ren_uops_2_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_lrs1_rtype_0 = io_ren_uops_2_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_lrs2_rtype_0 = io_ren_uops_2_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_frs3_en_0 = io_ren_uops_2_frs3_en; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fcn_dw_0 = io_ren_uops_2_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_2_fcn_op_0 = io_ren_uops_2_fcn_op; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_fp_val_0 = io_ren_uops_2_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_fp_rm_0 = io_ren_uops_2_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_2_fp_typ_0 = io_ren_uops_2_fp_typ; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_xcpt_pf_if_0 = io_ren_uops_2_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_xcpt_ae_if_0 = io_ren_uops_2_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_xcpt_ma_if_0 = io_ren_uops_2_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_bp_debug_if_0 = io_ren_uops_2_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_bp_xcpt_if_0 = io_ren_uops_2_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_debug_fsrc_0 = io_ren_uops_2_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_2_debug_tsrc_0 = io_ren_uops_2_debug_tsrc; // @[rename-busytable.scala:27:7]
wire io_rebusy_reqs_0_0 = io_rebusy_reqs_0; // @[rename-busytable.scala:27:7]
wire io_rebusy_reqs_1_0 = io_rebusy_reqs_1; // @[rename-busytable.scala:27:7]
wire io_rebusy_reqs_2_0 = io_rebusy_reqs_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_0_0 = io_wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_1_0 = io_wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_2_0 = io_wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iq_type_3_0 = io_wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_0_0 = io_wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_1_0 = io_wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_2_0 = io_wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_3_0 = io_wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_4_0 = io_wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_5_0 = io_wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_6_0 = io_wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_7_0 = io_wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_8_0 = io_wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fu_code_9_0 = io_wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iw_issued_0 = io_wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iw_issued_partial_agen_0 = io_wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_iw_p1_speculative_child_0 = io_wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_iw_p2_speculative_child_0 = io_wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_dis_col_sel_0 = io_wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_0_bits_uop_br_type_0 = io_wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_sfence_0 = io_wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_eret_0 = io_wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_rocc_0 = io_wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_mov_0 = io_wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_imm_rename_0 = io_wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_imm_sel_0 = io_wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_pimm_0 = io_wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_op1_sel_0 = io_wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_op2_sel_0 = io_wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ldst_0 = io_wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_wen_0 = io_wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren1_0 = io_wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren2_0 = io_wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_ren3_0 = io_wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_swap12_0 = io_wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_swap23_0 = io_wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fromint_0 = io_wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_toint_0 = io_wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_fma_0 = io_wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_div_0 = io_wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_wflags_0 = io_wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_ctrl_vec_0 = io_wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_csr_cmd_0 = io_wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fcn_dw_0 = io_wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_0_bits_uop_fcn_op_0 = io_wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_fp_rm_0 = io_wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_0_bits_uop_fp_typ_0 = io_wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_bypassable_0 = io_wakeups_0_bits_bypassable; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_0_bits_speculative_mask_0 = io_wakeups_0_bits_speculative_mask; // @[rename-busytable.scala:27:7]
wire io_wakeups_0_bits_rebusy_0 = io_wakeups_0_bits_rebusy; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_0_0 = io_wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_1_0 = io_wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_2_0 = io_wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iq_type_3_0 = io_wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_0_0 = io_wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_1_0 = io_wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_2_0 = io_wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_3_0 = io_wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_4_0 = io_wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_5_0 = io_wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_6_0 = io_wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_7_0 = io_wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_8_0 = io_wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fu_code_9_0 = io_wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iw_issued_0 = io_wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iw_issued_partial_agen_0 = io_wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_iw_p1_speculative_child_0 = io_wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_iw_p2_speculative_child_0 = io_wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_dis_col_sel_0 = io_wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_1_bits_uop_br_type_0 = io_wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_sfence_0 = io_wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_eret_0 = io_wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_rocc_0 = io_wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_mov_0 = io_wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_imm_rename_0 = io_wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_imm_sel_0 = io_wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_pimm_0 = io_wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_op1_sel_0 = io_wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_op2_sel_0 = io_wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ldst_0 = io_wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_wen_0 = io_wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren1_0 = io_wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren2_0 = io_wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_ren3_0 = io_wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_swap12_0 = io_wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_swap23_0 = io_wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fromint_0 = io_wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_toint_0 = io_wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_fma_0 = io_wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_div_0 = io_wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_wflags_0 = io_wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_ctrl_vec_0 = io_wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_csr_cmd_0 = io_wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fcn_dw_0 = io_wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_1_bits_uop_fcn_op_0 = io_wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_fp_rm_0 = io_wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_1_bits_uop_fp_typ_0 = io_wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_valid_0 = io_wakeups_2_valid; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_2_bits_uop_inst_0 = io_wakeups_2_bits_uop_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_2_bits_uop_debug_inst_0 = io_wakeups_2_bits_uop_debug_inst; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_rvc_0 = io_wakeups_2_bits_uop_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_wakeups_2_bits_uop_debug_pc_0 = io_wakeups_2_bits_uop_debug_pc; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iq_type_0_0 = io_wakeups_2_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iq_type_1_0 = io_wakeups_2_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iq_type_2_0 = io_wakeups_2_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iq_type_3_0 = io_wakeups_2_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_0_0 = io_wakeups_2_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_1_0 = io_wakeups_2_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_2_0 = io_wakeups_2_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_3_0 = io_wakeups_2_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_4_0 = io_wakeups_2_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_5_0 = io_wakeups_2_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_6_0 = io_wakeups_2_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_7_0 = io_wakeups_2_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_8_0 = io_wakeups_2_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fu_code_9_0 = io_wakeups_2_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iw_issued_0 = io_wakeups_2_bits_uop_iw_issued; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_iw_p1_speculative_child_0 = io_wakeups_2_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_iw_p2_speculative_child_0 = io_wakeups_2_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_dis_col_sel_0 = io_wakeups_2_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_wakeups_2_bits_uop_br_mask_0 = io_wakeups_2_bits_uop_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_2_bits_uop_br_tag_0 = io_wakeups_2_bits_uop_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_2_bits_uop_br_type_0 = io_wakeups_2_bits_uop_br_type; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_sfb_0 = io_wakeups_2_bits_uop_is_sfb; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_fence_0 = io_wakeups_2_bits_uop_is_fence; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_fencei_0 = io_wakeups_2_bits_uop_is_fencei; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_sfence_0 = io_wakeups_2_bits_uop_is_sfence; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_amo_0 = io_wakeups_2_bits_uop_is_amo; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_eret_0 = io_wakeups_2_bits_uop_is_eret; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_sys_pc2epc_0 = io_wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_rocc_0 = io_wakeups_2_bits_uop_is_rocc; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_mov_0 = io_wakeups_2_bits_uop_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_2_bits_uop_ftq_idx_0 = io_wakeups_2_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_edge_inst_0 = io_wakeups_2_bits_uop_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_2_bits_uop_pc_lob_0 = io_wakeups_2_bits_uop_pc_lob; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_taken_0 = io_wakeups_2_bits_uop_taken; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_imm_rename_0 = io_wakeups_2_bits_uop_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_imm_sel_0 = io_wakeups_2_bits_uop_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_2_bits_uop_pimm_0 = io_wakeups_2_bits_uop_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_wakeups_2_bits_uop_imm_packed_0 = io_wakeups_2_bits_uop_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_op1_sel_0 = io_wakeups_2_bits_uop_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_op2_sel_0 = io_wakeups_2_bits_uop_op2_sel; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ldst_0 = io_wakeups_2_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_wen_0 = io_wakeups_2_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ren1_0 = io_wakeups_2_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ren2_0 = io_wakeups_2_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_ren3_0 = io_wakeups_2_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_swap12_0 = io_wakeups_2_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_swap23_0 = io_wakeups_2_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_fromint_0 = io_wakeups_2_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_toint_0 = io_wakeups_2_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_fma_0 = io_wakeups_2_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_div_0 = io_wakeups_2_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_2_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_wflags_0 = io_wakeups_2_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_ctrl_vec_0 = io_wakeups_2_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_2_bits_uop_rob_idx_0 = io_wakeups_2_bits_uop_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_2_bits_uop_ldq_idx_0 = io_wakeups_2_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_2_bits_uop_stq_idx_0 = io_wakeups_2_bits_uop_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_rxq_idx_0 = io_wakeups_2_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_2_bits_uop_pdst_0 = io_wakeups_2_bits_uop_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_2_bits_uop_prs1_0 = io_wakeups_2_bits_uop_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_2_bits_uop_prs2_0 = io_wakeups_2_bits_uop_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_2_bits_uop_prs3_0 = io_wakeups_2_bits_uop_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_2_bits_uop_ppred_0 = io_wakeups_2_bits_uop_ppred; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_prs1_busy_0 = io_wakeups_2_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_prs2_busy_0 = io_wakeups_2_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_prs3_busy_0 = io_wakeups_2_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_ppred_busy_0 = io_wakeups_2_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_2_bits_uop_stale_pdst_0 = io_wakeups_2_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_exception_0 = io_wakeups_2_bits_uop_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_wakeups_2_bits_uop_exc_cause_0 = io_wakeups_2_bits_uop_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_2_bits_uop_mem_cmd_0 = io_wakeups_2_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_mem_size_0 = io_wakeups_2_bits_uop_mem_size; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_mem_signed_0 = io_wakeups_2_bits_uop_mem_signed; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_uses_ldq_0 = io_wakeups_2_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_uses_stq_0 = io_wakeups_2_bits_uop_uses_stq; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_is_unique_0 = io_wakeups_2_bits_uop_is_unique; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_flush_on_commit_0 = io_wakeups_2_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_csr_cmd_0 = io_wakeups_2_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_ldst_is_rs1_0 = io_wakeups_2_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_2_bits_uop_ldst_0 = io_wakeups_2_bits_uop_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_2_bits_uop_lrs1_0 = io_wakeups_2_bits_uop_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_2_bits_uop_lrs2_0 = io_wakeups_2_bits_uop_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_2_bits_uop_lrs3_0 = io_wakeups_2_bits_uop_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_dst_rtype_0 = io_wakeups_2_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_lrs1_rtype_0 = io_wakeups_2_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_lrs2_rtype_0 = io_wakeups_2_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_frs3_en_0 = io_wakeups_2_bits_uop_frs3_en; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fcn_dw_0 = io_wakeups_2_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_2_bits_uop_fcn_op_0 = io_wakeups_2_bits_uop_fcn_op; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_fp_val_0 = io_wakeups_2_bits_uop_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_fp_rm_0 = io_wakeups_2_bits_uop_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_2_bits_uop_fp_typ_0 = io_wakeups_2_bits_uop_fp_typ; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_xcpt_pf_if_0 = io_wakeups_2_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_xcpt_ae_if_0 = io_wakeups_2_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_xcpt_ma_if_0 = io_wakeups_2_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_bp_debug_if_0 = io_wakeups_2_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_bp_xcpt_if_0 = io_wakeups_2_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_debug_fsrc_0 = io_wakeups_2_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_2_bits_uop_debug_tsrc_0 = io_wakeups_2_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_valid_0 = io_wakeups_3_valid; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_3_bits_uop_inst_0 = io_wakeups_3_bits_uop_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_3_bits_uop_debug_inst_0 = io_wakeups_3_bits_uop_debug_inst; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_rvc_0 = io_wakeups_3_bits_uop_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_wakeups_3_bits_uop_debug_pc_0 = io_wakeups_3_bits_uop_debug_pc; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iq_type_0_0 = io_wakeups_3_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iq_type_1_0 = io_wakeups_3_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iq_type_2_0 = io_wakeups_3_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iq_type_3_0 = io_wakeups_3_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_0_0 = io_wakeups_3_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_1_0 = io_wakeups_3_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_2_0 = io_wakeups_3_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_3_0 = io_wakeups_3_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_4_0 = io_wakeups_3_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_5_0 = io_wakeups_3_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_6_0 = io_wakeups_3_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_7_0 = io_wakeups_3_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_8_0 = io_wakeups_3_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fu_code_9_0 = io_wakeups_3_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iw_issued_0 = io_wakeups_3_bits_uop_iw_issued; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_iw_p1_speculative_child_0 = io_wakeups_3_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_iw_p2_speculative_child_0 = io_wakeups_3_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_dis_col_sel_0 = io_wakeups_3_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_wakeups_3_bits_uop_br_mask_0 = io_wakeups_3_bits_uop_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_3_bits_uop_br_tag_0 = io_wakeups_3_bits_uop_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_3_bits_uop_br_type_0 = io_wakeups_3_bits_uop_br_type; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_sfb_0 = io_wakeups_3_bits_uop_is_sfb; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_fence_0 = io_wakeups_3_bits_uop_is_fence; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_fencei_0 = io_wakeups_3_bits_uop_is_fencei; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_sfence_0 = io_wakeups_3_bits_uop_is_sfence; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_amo_0 = io_wakeups_3_bits_uop_is_amo; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_eret_0 = io_wakeups_3_bits_uop_is_eret; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_sys_pc2epc_0 = io_wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_rocc_0 = io_wakeups_3_bits_uop_is_rocc; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_mov_0 = io_wakeups_3_bits_uop_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_3_bits_uop_ftq_idx_0 = io_wakeups_3_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_edge_inst_0 = io_wakeups_3_bits_uop_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_3_bits_uop_pc_lob_0 = io_wakeups_3_bits_uop_pc_lob; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_taken_0 = io_wakeups_3_bits_uop_taken; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_imm_rename_0 = io_wakeups_3_bits_uop_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_imm_sel_0 = io_wakeups_3_bits_uop_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_3_bits_uop_pimm_0 = io_wakeups_3_bits_uop_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_wakeups_3_bits_uop_imm_packed_0 = io_wakeups_3_bits_uop_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_op1_sel_0 = io_wakeups_3_bits_uop_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_op2_sel_0 = io_wakeups_3_bits_uop_op2_sel; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ldst_0 = io_wakeups_3_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_wen_0 = io_wakeups_3_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ren1_0 = io_wakeups_3_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ren2_0 = io_wakeups_3_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_ren3_0 = io_wakeups_3_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_swap12_0 = io_wakeups_3_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_swap23_0 = io_wakeups_3_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_fromint_0 = io_wakeups_3_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_toint_0 = io_wakeups_3_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_fma_0 = io_wakeups_3_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_div_0 = io_wakeups_3_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_3_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_wflags_0 = io_wakeups_3_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_ctrl_vec_0 = io_wakeups_3_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_3_bits_uop_rob_idx_0 = io_wakeups_3_bits_uop_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_3_bits_uop_ldq_idx_0 = io_wakeups_3_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_3_bits_uop_stq_idx_0 = io_wakeups_3_bits_uop_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_rxq_idx_0 = io_wakeups_3_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_3_bits_uop_pdst_0 = io_wakeups_3_bits_uop_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_3_bits_uop_prs1_0 = io_wakeups_3_bits_uop_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_3_bits_uop_prs2_0 = io_wakeups_3_bits_uop_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_3_bits_uop_prs3_0 = io_wakeups_3_bits_uop_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_3_bits_uop_ppred_0 = io_wakeups_3_bits_uop_ppred; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_prs1_busy_0 = io_wakeups_3_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_prs2_busy_0 = io_wakeups_3_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_prs3_busy_0 = io_wakeups_3_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_ppred_busy_0 = io_wakeups_3_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_3_bits_uop_stale_pdst_0 = io_wakeups_3_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_exception_0 = io_wakeups_3_bits_uop_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_wakeups_3_bits_uop_exc_cause_0 = io_wakeups_3_bits_uop_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_3_bits_uop_mem_cmd_0 = io_wakeups_3_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_mem_size_0 = io_wakeups_3_bits_uop_mem_size; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_mem_signed_0 = io_wakeups_3_bits_uop_mem_signed; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_uses_ldq_0 = io_wakeups_3_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_uses_stq_0 = io_wakeups_3_bits_uop_uses_stq; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_is_unique_0 = io_wakeups_3_bits_uop_is_unique; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_flush_on_commit_0 = io_wakeups_3_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_csr_cmd_0 = io_wakeups_3_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_ldst_is_rs1_0 = io_wakeups_3_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_3_bits_uop_ldst_0 = io_wakeups_3_bits_uop_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_3_bits_uop_lrs1_0 = io_wakeups_3_bits_uop_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_3_bits_uop_lrs2_0 = io_wakeups_3_bits_uop_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_3_bits_uop_lrs3_0 = io_wakeups_3_bits_uop_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_dst_rtype_0 = io_wakeups_3_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_lrs1_rtype_0 = io_wakeups_3_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_lrs2_rtype_0 = io_wakeups_3_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_frs3_en_0 = io_wakeups_3_bits_uop_frs3_en; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fcn_dw_0 = io_wakeups_3_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_3_bits_uop_fcn_op_0 = io_wakeups_3_bits_uop_fcn_op; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_fp_val_0 = io_wakeups_3_bits_uop_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_fp_rm_0 = io_wakeups_3_bits_uop_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_3_bits_uop_fp_typ_0 = io_wakeups_3_bits_uop_fp_typ; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_xcpt_pf_if_0 = io_wakeups_3_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_xcpt_ae_if_0 = io_wakeups_3_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_xcpt_ma_if_0 = io_wakeups_3_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_bp_debug_if_0 = io_wakeups_3_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_bp_xcpt_if_0 = io_wakeups_3_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_debug_fsrc_0 = io_wakeups_3_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_3_bits_uop_debug_tsrc_0 = io_wakeups_3_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_valid_0 = io_wakeups_4_valid; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_4_bits_uop_inst_0 = io_wakeups_4_bits_uop_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_wakeups_4_bits_uop_debug_inst_0 = io_wakeups_4_bits_uop_debug_inst; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_rvc_0 = io_wakeups_4_bits_uop_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_wakeups_4_bits_uop_debug_pc_0 = io_wakeups_4_bits_uop_debug_pc; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iq_type_0_0 = io_wakeups_4_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iq_type_1_0 = io_wakeups_4_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iq_type_2_0 = io_wakeups_4_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iq_type_3_0 = io_wakeups_4_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_0_0 = io_wakeups_4_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_1_0 = io_wakeups_4_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_2_0 = io_wakeups_4_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_3_0 = io_wakeups_4_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_4_0 = io_wakeups_4_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_5_0 = io_wakeups_4_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_6_0 = io_wakeups_4_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_7_0 = io_wakeups_4_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_8_0 = io_wakeups_4_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fu_code_9_0 = io_wakeups_4_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iw_issued_0 = io_wakeups_4_bits_uop_iw_issued; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_iw_p1_speculative_child_0 = io_wakeups_4_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_iw_p2_speculative_child_0 = io_wakeups_4_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_4_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_4_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_4_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_dis_col_sel_0 = io_wakeups_4_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7]
wire [15:0] io_wakeups_4_bits_uop_br_mask_0 = io_wakeups_4_bits_uop_br_mask; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_4_bits_uop_br_tag_0 = io_wakeups_4_bits_uop_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_wakeups_4_bits_uop_br_type_0 = io_wakeups_4_bits_uop_br_type; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_sfb_0 = io_wakeups_4_bits_uop_is_sfb; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_fence_0 = io_wakeups_4_bits_uop_is_fence; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_fencei_0 = io_wakeups_4_bits_uop_is_fencei; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_sfence_0 = io_wakeups_4_bits_uop_is_sfence; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_amo_0 = io_wakeups_4_bits_uop_is_amo; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_eret_0 = io_wakeups_4_bits_uop_is_eret; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_sys_pc2epc_0 = io_wakeups_4_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_rocc_0 = io_wakeups_4_bits_uop_is_rocc; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_mov_0 = io_wakeups_4_bits_uop_is_mov; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_4_bits_uop_ftq_idx_0 = io_wakeups_4_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_edge_inst_0 = io_wakeups_4_bits_uop_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_4_bits_uop_pc_lob_0 = io_wakeups_4_bits_uop_pc_lob; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_taken_0 = io_wakeups_4_bits_uop_taken; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_imm_rename_0 = io_wakeups_4_bits_uop_imm_rename; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_imm_sel_0 = io_wakeups_4_bits_uop_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_4_bits_uop_pimm_0 = io_wakeups_4_bits_uop_pimm; // @[rename-busytable.scala:27:7]
wire [19:0] io_wakeups_4_bits_uop_imm_packed_0 = io_wakeups_4_bits_uop_imm_packed; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_op1_sel_0 = io_wakeups_4_bits_uop_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_op2_sel_0 = io_wakeups_4_bits_uop_op2_sel; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ldst_0 = io_wakeups_4_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_wen_0 = io_wakeups_4_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ren1_0 = io_wakeups_4_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ren2_0 = io_wakeups_4_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_ren3_0 = io_wakeups_4_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_swap12_0 = io_wakeups_4_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_swap23_0 = io_wakeups_4_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_4_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_4_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_fromint_0 = io_wakeups_4_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_toint_0 = io_wakeups_4_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_4_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_fma_0 = io_wakeups_4_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_div_0 = io_wakeups_4_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_4_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_wflags_0 = io_wakeups_4_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_ctrl_vec_0 = io_wakeups_4_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_4_bits_uop_rob_idx_0 = io_wakeups_4_bits_uop_rob_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_4_bits_uop_ldq_idx_0 = io_wakeups_4_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_4_bits_uop_stq_idx_0 = io_wakeups_4_bits_uop_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_rxq_idx_0 = io_wakeups_4_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_4_bits_uop_pdst_0 = io_wakeups_4_bits_uop_pdst; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_4_bits_uop_prs1_0 = io_wakeups_4_bits_uop_prs1; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_4_bits_uop_prs2_0 = io_wakeups_4_bits_uop_prs2; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_4_bits_uop_prs3_0 = io_wakeups_4_bits_uop_prs3; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_4_bits_uop_ppred_0 = io_wakeups_4_bits_uop_ppred; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_prs1_busy_0 = io_wakeups_4_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_prs2_busy_0 = io_wakeups_4_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_prs3_busy_0 = io_wakeups_4_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_ppred_busy_0 = io_wakeups_4_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7]
wire [6:0] io_wakeups_4_bits_uop_stale_pdst_0 = io_wakeups_4_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_exception_0 = io_wakeups_4_bits_uop_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_wakeups_4_bits_uop_exc_cause_0 = io_wakeups_4_bits_uop_exc_cause; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_4_bits_uop_mem_cmd_0 = io_wakeups_4_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_mem_size_0 = io_wakeups_4_bits_uop_mem_size; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_mem_signed_0 = io_wakeups_4_bits_uop_mem_signed; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_uses_ldq_0 = io_wakeups_4_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_uses_stq_0 = io_wakeups_4_bits_uop_uses_stq; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_is_unique_0 = io_wakeups_4_bits_uop_is_unique; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_flush_on_commit_0 = io_wakeups_4_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_csr_cmd_0 = io_wakeups_4_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_ldst_is_rs1_0 = io_wakeups_4_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_4_bits_uop_ldst_0 = io_wakeups_4_bits_uop_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_4_bits_uop_lrs1_0 = io_wakeups_4_bits_uop_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_4_bits_uop_lrs2_0 = io_wakeups_4_bits_uop_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_wakeups_4_bits_uop_lrs3_0 = io_wakeups_4_bits_uop_lrs3; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_dst_rtype_0 = io_wakeups_4_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_lrs1_rtype_0 = io_wakeups_4_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_lrs2_rtype_0 = io_wakeups_4_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_frs3_en_0 = io_wakeups_4_bits_uop_frs3_en; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fcn_dw_0 = io_wakeups_4_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7]
wire [4:0] io_wakeups_4_bits_uop_fcn_op_0 = io_wakeups_4_bits_uop_fcn_op; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_fp_val_0 = io_wakeups_4_bits_uop_fp_val; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_fp_rm_0 = io_wakeups_4_bits_uop_fp_rm; // @[rename-busytable.scala:27:7]
wire [1:0] io_wakeups_4_bits_uop_fp_typ_0 = io_wakeups_4_bits_uop_fp_typ; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_xcpt_pf_if_0 = io_wakeups_4_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_xcpt_ae_if_0 = io_wakeups_4_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_xcpt_ma_if_0 = io_wakeups_4_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_bp_debug_if_0 = io_wakeups_4_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_bp_xcpt_if_0 = io_wakeups_4_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_debug_fsrc_0 = io_wakeups_4_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_4_bits_uop_debug_tsrc_0 = io_wakeups_4_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[rename-busytable.scala:27:7]
wire [2:0] io_wakeups_1_bits_speculative_mask = 3'h0; // @[rename-busytable.scala:27:7]
wire [2:0] wakeups_1_bits_speculative_mask = 3'h0; // @[rename-busytable.scala:47:18]
wire [2:0] _wakeups_wu_valid_T_3 = 3'h0; // @[rename-busytable.scala:48:72]
wire [2:0] io_wakeups_2_bits_speculative_mask = 3'h1; // @[rename-busytable.scala:27:7]
wire [2:0] wakeups_2_bits_speculative_mask = 3'h1; // @[rename-busytable.scala:47:18]
wire [2:0] io_wakeups_3_bits_speculative_mask = 3'h2; // @[rename-busytable.scala:27:7]
wire [2:0] wakeups_3_bits_speculative_mask = 3'h2; // @[rename-busytable.scala:47:18]
wire [2:0] io_wakeups_4_bits_speculative_mask = 3'h4; // @[rename-busytable.scala:27:7]
wire [2:0] wakeups_4_bits_speculative_mask = 3'h4; // @[rename-busytable.scala:47:18]
wire io_wakeups_2_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7]
wire _wakeups_wu_valid_T_4 = 1'h1; // @[rename-busytable.scala:48:92]
wire wakeups_2_bits_bypassable = 1'h1; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_bypassable = 1'h1; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_bypassable = 1'h1; // @[rename-busytable.scala:47:18]
wire _busy_table_wb_T_6 = 1'h1; // @[rename-busytable.scala:56:59]
wire _busy_table_wb_T_11 = 1'h1; // @[rename-busytable.scala:56:59]
wire _busy_table_wb_T_16 = 1'h1; // @[rename-busytable.scala:56:59]
wire _busy_table_wb_T_21 = 1'h1; // @[rename-busytable.scala:56:59]
wire [99:0] _busy_table_next_T_18 = 100'h0; // @[rename-busytable.scala:63:37]
wire [99:0] _busy_table_next_T_22 = 100'h0; // @[rename-busytable.scala:63:37]
wire [99:0] _busy_table_next_T_26 = 100'h0; // @[rename-busytable.scala:63:37]
wire [99:0] _busy_table_next_T_30 = 100'h0; // @[rename-busytable.scala:63:37]
wire [127:0] _busy_table_next_T_19 = 128'h0; // @[rename-busytable.scala:63:31]
wire [127:0] _busy_table_next_T_23 = 128'h0; // @[rename-busytable.scala:63:31]
wire [127:0] _busy_table_next_T_27 = 128'h0; // @[rename-busytable.scala:63:31]
wire [127:0] _busy_table_next_T_31 = 128'h0; // @[rename-busytable.scala:63:31]
wire io_ren_uops_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_ren_uops_2_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_2_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_2_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_3_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[rename-busytable.scala:27:7]
wire io_wakeups_4_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7]
wire wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18]
wire _busy_table_next_T_17 = 1'h0; // @[rename-busytable.scala:63:56]
wire _busy_table_next_T_21 = 1'h0; // @[rename-busytable.scala:63:56]
wire _busy_table_next_T_25 = 1'h0; // @[rename-busytable.scala:63:56]
wire _busy_table_next_T_29 = 1'h0; // @[rename-busytable.scala:63:56]
wire _io_busy_resps_0_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_0_prs1_busy_T_4 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_0_prs1_busy_T_5 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_0_prs1_busy_T_6 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_0_prs1_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_0_prs2_busy_T_4 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_0_prs2_busy_T_5 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_0_prs2_busy_T_6 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_0_prs2_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_0_prs3_busy_T_4 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_0_prs3_busy_T_5 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_0_prs3_busy_T_6 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_0_prs3_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_1_prs1_busy_T_4 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_1_prs1_busy_T_5 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_1_prs1_busy_T_6 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_1_prs1_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_1_prs2_busy_T_4 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_1_prs2_busy_T_5 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_1_prs2_busy_T_6 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_1_prs2_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_1_prs3_busy_T_4 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_1_prs3_busy_T_5 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_1_prs3_busy_T_6 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_1_prs3_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_2_prs1_busy_T_4 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_2_prs1_busy_T_5 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_2_prs1_busy_T_6 = 1'h0; // @[rename-busytable.scala:79:82]
wire _io_busy_resps_2_prs1_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_2_prs2_busy_T_4 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_2_prs2_busy_T_5 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_2_prs2_busy_T_6 = 1'h0; // @[rename-busytable.scala:82:82]
wire _io_busy_resps_2_prs2_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_2_prs3_busy_T_4 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_2_prs3_busy_T_5 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_2_prs3_busy_T_6 = 1'h0; // @[rename-busytable.scala:85:82]
wire _io_busy_resps_2_prs3_busy_T_8 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_9 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_11 = 1'h0; // @[Mux.scala:30:73]
wire io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_2_prs1_busy_0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_2_prs2_busy_0; // @[rename-busytable.scala:27:7]
wire [99:0] io_debug_busytable; // @[rename-busytable.scala:27:7]
wire _wakeups_wu_valid_T_2; // @[rename-busytable.scala:48:34]
wire wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_0_bits_uop_inst; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:47:18]
wire [39:0] wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18]
wire [15:0] wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_taken; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:47:18]
wire [19:0] wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_exception; // @[rename-busytable.scala:47:18]
wire [63:0] wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_bypassable; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_0_bits_speculative_mask; // @[rename-busytable.scala:47:18]
wire wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18]
wire wakeups_0_valid; // @[rename-busytable.scala:47:18]
reg wakeups_wu_valid_REG; // @[rename-busytable.scala:48:24]
reg [2:0] wakeups_wu_valid_REG_1; // @[rename-busytable.scala:48:46]
wire [2:0] _wakeups_wu_valid_T = wakeups_wu_valid_REG_1 & io_child_rebusys_0; // @[rename-busytable.scala:27:7, :48:{46,72}]
wire _wakeups_wu_valid_T_1 = _wakeups_wu_valid_T == 3'h0; // @[rename-busytable.scala:48:{72,92}]
assign _wakeups_wu_valid_T_2 = wakeups_wu_valid_REG & _wakeups_wu_valid_T_1; // @[rename-busytable.scala:48:{24,34,92}]
assign wakeups_0_valid = _wakeups_wu_valid_T_2; // @[rename-busytable.scala:47:18, :48:34]
reg [31:0] wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_inst = wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [31:0] wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_debug_inst = wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_rvc = wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24]
reg [39:0] wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_debug_pc = wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iq_type_0 = wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iq_type_1 = wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iq_type_2 = wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iq_type_3 = wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_0 = wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_1 = wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_2 = wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_3 = wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_4 = wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_5 = wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_6 = wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_7 = wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_8 = wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fu_code_9 = wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_issued = wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_dis_col_sel = wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [15:0] wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_br_mask = wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_br_tag = wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_br_type = wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_sfb = wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_fence = wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_fencei = wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_sfence = wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_amo = wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_eret = wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_rocc = wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_mov = wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_ftq_idx = wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_edge_inst = wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_pc_lob = wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_taken = wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_imm_rename = wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_imm_sel = wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_pimm = wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:47:18, :49:24]
reg [19:0] wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_imm_packed = wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_op1_sel = wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_op2_sel = wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_rob_idx = wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_ldq_idx = wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_stq_idx = wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_rxq_idx = wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_pdst = wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_prs1 = wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_prs2 = wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_prs3 = wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_ppred = wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_prs1_busy = wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_prs2_busy = wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_prs3_busy = wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_ppred_busy = wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_stale_pdst = wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_exception = wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:47:18, :49:24]
reg [63:0] wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_exc_cause = wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_mem_cmd = wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_mem_size = wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_mem_signed = wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_uses_ldq = wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_uses_stq = wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_is_unique = wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_flush_on_commit = wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_csr_cmd = wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_ldst = wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_lrs1 = wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_lrs2 = wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_lrs3 = wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_dst_rtype = wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_frs3_en = wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fcn_dw = wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fcn_op = wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_val = wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_rm = wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_fp_typ = wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_bp_debug_if = wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_debug_fsrc = wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_uop_debug_tsrc = wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_bypassable = wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_speculative_mask = wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:49:24]
assign wakeups_0_bits_rebusy = wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:47:18, :49:24]
wire _wakeups_wu_valid_T_5; // @[rename-busytable.scala:48:34]
wire _busy_table_wb_T_7 = wakeups_1_valid; // @[rename-busytable.scala:47:18, :56:56]
wire wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_1_bits_uop_inst; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:47:18]
wire [39:0] wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18]
wire [15:0] wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_taken; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:47:18]
wire [19:0] wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_exception; // @[rename-busytable.scala:47:18]
wire [63:0] wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18]
wire wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18]
reg wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:24]
assign _wakeups_wu_valid_T_5 = wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:{24,34}]
assign wakeups_1_valid = _wakeups_wu_valid_T_5; // @[rename-busytable.scala:47:18, :48:34]
reg [31:0] wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_inst = wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [31:0] wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_debug_inst = wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_rvc = wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24]
reg [39:0] wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_debug_pc = wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iq_type_0 = wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iq_type_1 = wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iq_type_2 = wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iq_type_3 = wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_0 = wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_1 = wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_2 = wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_3 = wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_4 = wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_5 = wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_6 = wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_7 = wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_8 = wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fu_code_9 = wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_issued = wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_dis_col_sel = wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [15:0] wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_br_mask = wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_br_tag = wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_br_type = wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_sfb = wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_fence = wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_fencei = wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_sfence = wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_amo = wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_eret = wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_rocc = wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_mov = wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_ftq_idx = wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_edge_inst = wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_pc_lob = wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_taken = wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_imm_rename = wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_imm_sel = wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_pimm = wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:47:18, :49:24]
reg [19:0] wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_imm_packed = wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_op1_sel = wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_op2_sel = wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_rob_idx = wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_ldq_idx = wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_stq_idx = wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_rxq_idx = wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_pdst = wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_prs1 = wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_prs2 = wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_prs3 = wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_ppred = wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_prs1_busy = wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_prs2_busy = wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_prs3_busy = wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_ppred_busy = wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_stale_pdst = wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_exception = wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:47:18, :49:24]
reg [63:0] wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_exc_cause = wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_mem_cmd = wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_mem_size = wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_mem_signed = wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_uses_ldq = wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_uses_stq = wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_is_unique = wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_flush_on_commit = wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_csr_cmd = wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_ldst = wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_lrs1 = wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_lrs2 = wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_lrs3 = wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_dst_rtype = wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_frs3_en = wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fcn_dw = wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fcn_op = wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_val = wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_rm = wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_fp_typ = wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_bp_debug_if = wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_debug_fsrc = wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:49:24]
assign wakeups_1_bits_uop_debug_tsrc = wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24]
wire _wakeups_wu_valid_T_8; // @[rename-busytable.scala:48:34]
wire _busy_table_wb_T_12 = wakeups_2_valid; // @[rename-busytable.scala:47:18, :56:56]
wire wakeups_2_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_2_bits_uop_inst; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_2_bits_uop_debug_inst; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_rvc; // @[rename-busytable.scala:47:18]
wire [39:0] wakeups_2_bits_uop_debug_pc; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iw_issued; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18]
wire [15:0] wakeups_2_bits_uop_br_mask; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_2_bits_uop_br_tag; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_2_bits_uop_br_type; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_sfb; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_fence; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_fencei; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_sfence; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_amo; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_eret; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_rocc; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_mov; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_2_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_edge_inst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_2_bits_uop_pc_lob; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_taken; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_imm_rename; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_imm_sel; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_2_bits_uop_pimm; // @[rename-busytable.scala:47:18]
wire [19:0] wakeups_2_bits_uop_imm_packed; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_op1_sel; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_op2_sel; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_2_bits_uop_rob_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_2_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_2_bits_uop_stq_idx; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_2_bits_uop_pdst; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_2_bits_uop_prs1; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_2_bits_uop_prs2; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_2_bits_uop_prs3; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_2_bits_uop_ppred; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_2_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_exception; // @[rename-busytable.scala:47:18]
wire [63:0] wakeups_2_bits_uop_exc_cause; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_2_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_mem_size; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_mem_signed; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_uses_stq; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_is_unique; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_2_bits_uop_ldst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_2_bits_uop_lrs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_2_bits_uop_lrs2; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_2_bits_uop_lrs3; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_frs3_en; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_2_bits_uop_fcn_op; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_fp_val; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_fp_rm; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_2_bits_uop_fp_typ; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18]
wire wakeups_2_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_2_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18]
reg wakeups_wu_valid_REG_4; // @[rename-busytable.scala:48:24]
wire [2:0] _wakeups_wu_valid_T_6 = io_child_rebusys_0 & 3'h1; // @[rename-busytable.scala:27:7, :48:72]
wire _wakeups_wu_valid_T_7 = _wakeups_wu_valid_T_6 == 3'h0; // @[rename-busytable.scala:48:{72,92}]
assign _wakeups_wu_valid_T_8 = wakeups_wu_valid_REG_4 & _wakeups_wu_valid_T_7; // @[rename-busytable.scala:48:{24,34,92}]
assign wakeups_2_valid = _wakeups_wu_valid_T_8; // @[rename-busytable.scala:47:18, :48:34]
reg [31:0] wakeups_wu_bits_REG_2_uop_inst; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_inst = wakeups_wu_bits_REG_2_uop_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [31:0] wakeups_wu_bits_REG_2_uop_debug_inst; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_debug_inst = wakeups_wu_bits_REG_2_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_rvc; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_rvc = wakeups_wu_bits_REG_2_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24]
reg [39:0] wakeups_wu_bits_REG_2_uop_debug_pc; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_debug_pc = wakeups_wu_bits_REG_2_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iq_type_0; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iq_type_0 = wakeups_wu_bits_REG_2_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iq_type_1; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iq_type_1 = wakeups_wu_bits_REG_2_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iq_type_2; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iq_type_2 = wakeups_wu_bits_REG_2_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iq_type_3; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iq_type_3 = wakeups_wu_bits_REG_2_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_0; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_0 = wakeups_wu_bits_REG_2_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_1; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_1 = wakeups_wu_bits_REG_2_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_2; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_2 = wakeups_wu_bits_REG_2_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_3; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_3 = wakeups_wu_bits_REG_2_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_4; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_4 = wakeups_wu_bits_REG_2_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_5; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_5 = wakeups_wu_bits_REG_2_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_6; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_6 = wakeups_wu_bits_REG_2_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_7; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_7 = wakeups_wu_bits_REG_2_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_8; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_8 = wakeups_wu_bits_REG_2_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fu_code_9; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fu_code_9 = wakeups_wu_bits_REG_2_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iw_issued; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_issued = wakeups_wu_bits_REG_2_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_dis_col_sel; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_dis_col_sel = wakeups_wu_bits_REG_2_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [15:0] wakeups_wu_bits_REG_2_uop_br_mask; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_br_mask = wakeups_wu_bits_REG_2_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_2_uop_br_tag; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_br_tag = wakeups_wu_bits_REG_2_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_2_uop_br_type; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_br_type = wakeups_wu_bits_REG_2_uop_br_type; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_sfb; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_sfb = wakeups_wu_bits_REG_2_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_fence; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_fence = wakeups_wu_bits_REG_2_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_fencei; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_fencei = wakeups_wu_bits_REG_2_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_sfence; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_sfence = wakeups_wu_bits_REG_2_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_amo; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_amo = wakeups_wu_bits_REG_2_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_eret; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_eret = wakeups_wu_bits_REG_2_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_2_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_rocc; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_rocc = wakeups_wu_bits_REG_2_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_mov; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_mov = wakeups_wu_bits_REG_2_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_2_uop_ftq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_ftq_idx = wakeups_wu_bits_REG_2_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_edge_inst; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_edge_inst = wakeups_wu_bits_REG_2_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_2_uop_pc_lob; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_pc_lob = wakeups_wu_bits_REG_2_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_taken; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_taken = wakeups_wu_bits_REG_2_uop_taken; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_imm_rename; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_imm_rename = wakeups_wu_bits_REG_2_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_imm_sel; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_imm_sel = wakeups_wu_bits_REG_2_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_2_uop_pimm; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_pimm = wakeups_wu_bits_REG_2_uop_pimm; // @[rename-busytable.scala:47:18, :49:24]
reg [19:0] wakeups_wu_bits_REG_2_uop_imm_packed; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_imm_packed = wakeups_wu_bits_REG_2_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_op1_sel; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_op1_sel = wakeups_wu_bits_REG_2_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_op2_sel; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_op2_sel = wakeups_wu_bits_REG_2_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_2_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_2_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_2_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_2_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_2_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_2_uop_rob_idx; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_rob_idx = wakeups_wu_bits_REG_2_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_2_uop_ldq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_ldq_idx = wakeups_wu_bits_REG_2_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_2_uop_stq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_stq_idx = wakeups_wu_bits_REG_2_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_rxq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_rxq_idx = wakeups_wu_bits_REG_2_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_2_uop_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_pdst = wakeups_wu_bits_REG_2_uop_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_2_uop_prs1; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_prs1 = wakeups_wu_bits_REG_2_uop_prs1; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_2_uop_prs2; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_prs2 = wakeups_wu_bits_REG_2_uop_prs2; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_2_uop_prs3; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_prs3 = wakeups_wu_bits_REG_2_uop_prs3; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_2_uop_ppred; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_ppred = wakeups_wu_bits_REG_2_uop_ppred; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_prs1_busy; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_prs1_busy = wakeups_wu_bits_REG_2_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_prs2_busy; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_prs2_busy = wakeups_wu_bits_REG_2_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_prs3_busy; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_prs3_busy = wakeups_wu_bits_REG_2_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_ppred_busy; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_ppred_busy = wakeups_wu_bits_REG_2_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_2_uop_stale_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_stale_pdst = wakeups_wu_bits_REG_2_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_exception; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_exception = wakeups_wu_bits_REG_2_uop_exception; // @[rename-busytable.scala:47:18, :49:24]
reg [63:0] wakeups_wu_bits_REG_2_uop_exc_cause; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_exc_cause = wakeups_wu_bits_REG_2_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_2_uop_mem_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_mem_cmd = wakeups_wu_bits_REG_2_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_mem_size; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_mem_size = wakeups_wu_bits_REG_2_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_mem_signed; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_mem_signed = wakeups_wu_bits_REG_2_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_uses_ldq; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_uses_ldq = wakeups_wu_bits_REG_2_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_uses_stq; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_uses_stq = wakeups_wu_bits_REG_2_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_is_unique; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_is_unique = wakeups_wu_bits_REG_2_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_flush_on_commit; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_flush_on_commit = wakeups_wu_bits_REG_2_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_csr_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_csr_cmd = wakeups_wu_bits_REG_2_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_2_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_2_uop_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_ldst = wakeups_wu_bits_REG_2_uop_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_2_uop_lrs1; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_lrs1 = wakeups_wu_bits_REG_2_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_2_uop_lrs2; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_lrs2 = wakeups_wu_bits_REG_2_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_2_uop_lrs3; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_lrs3 = wakeups_wu_bits_REG_2_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_dst_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_dst_rtype = wakeups_wu_bits_REG_2_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_lrs1_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_2_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_lrs2_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_2_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_frs3_en; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_frs3_en = wakeups_wu_bits_REG_2_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fcn_dw; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fcn_dw = wakeups_wu_bits_REG_2_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_2_uop_fcn_op; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fcn_op = wakeups_wu_bits_REG_2_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_fp_val; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_val = wakeups_wu_bits_REG_2_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_fp_rm; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_rm = wakeups_wu_bits_REG_2_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_2_uop_fp_typ; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_fp_typ = wakeups_wu_bits_REG_2_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_2_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_2_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_2_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_bp_debug_if; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_bp_debug_if = wakeups_wu_bits_REG_2_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_2_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_2_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_debug_fsrc; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_debug_fsrc = wakeups_wu_bits_REG_2_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_2_uop_debug_tsrc; // @[rename-busytable.scala:49:24]
assign wakeups_2_bits_uop_debug_tsrc = wakeups_wu_bits_REG_2_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24]
wire _wakeups_wu_valid_T_11; // @[rename-busytable.scala:48:34]
wire _busy_table_wb_T_17 = wakeups_3_valid; // @[rename-busytable.scala:47:18, :56:56]
wire wakeups_3_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_3_bits_uop_inst; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_3_bits_uop_debug_inst; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_rvc; // @[rename-busytable.scala:47:18]
wire [39:0] wakeups_3_bits_uop_debug_pc; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iw_issued; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18]
wire [15:0] wakeups_3_bits_uop_br_mask; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_3_bits_uop_br_tag; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_3_bits_uop_br_type; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_sfb; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_fence; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_fencei; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_sfence; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_amo; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_eret; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_rocc; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_mov; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_3_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_edge_inst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_3_bits_uop_pc_lob; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_taken; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_imm_rename; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_imm_sel; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_3_bits_uop_pimm; // @[rename-busytable.scala:47:18]
wire [19:0] wakeups_3_bits_uop_imm_packed; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_op1_sel; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_op2_sel; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_3_bits_uop_rob_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_3_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_3_bits_uop_stq_idx; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_3_bits_uop_pdst; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_3_bits_uop_prs1; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_3_bits_uop_prs2; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_3_bits_uop_prs3; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_3_bits_uop_ppred; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_3_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_exception; // @[rename-busytable.scala:47:18]
wire [63:0] wakeups_3_bits_uop_exc_cause; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_3_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_mem_size; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_mem_signed; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_uses_stq; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_is_unique; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_3_bits_uop_ldst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_3_bits_uop_lrs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_3_bits_uop_lrs2; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_3_bits_uop_lrs3; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_frs3_en; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_3_bits_uop_fcn_op; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_fp_val; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_fp_rm; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_3_bits_uop_fp_typ; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18]
wire wakeups_3_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_3_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18]
reg wakeups_wu_valid_REG_6; // @[rename-busytable.scala:48:24]
wire [2:0] _wakeups_wu_valid_T_9 = io_child_rebusys_0 & 3'h2; // @[rename-busytable.scala:27:7, :48:72]
wire _wakeups_wu_valid_T_10 = _wakeups_wu_valid_T_9 == 3'h0; // @[rename-busytable.scala:48:{72,92}]
assign _wakeups_wu_valid_T_11 = wakeups_wu_valid_REG_6 & _wakeups_wu_valid_T_10; // @[rename-busytable.scala:48:{24,34,92}]
assign wakeups_3_valid = _wakeups_wu_valid_T_11; // @[rename-busytable.scala:47:18, :48:34]
reg [31:0] wakeups_wu_bits_REG_3_uop_inst; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_inst = wakeups_wu_bits_REG_3_uop_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [31:0] wakeups_wu_bits_REG_3_uop_debug_inst; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_debug_inst = wakeups_wu_bits_REG_3_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_rvc; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_rvc = wakeups_wu_bits_REG_3_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24]
reg [39:0] wakeups_wu_bits_REG_3_uop_debug_pc; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_debug_pc = wakeups_wu_bits_REG_3_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iq_type_0; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iq_type_0 = wakeups_wu_bits_REG_3_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iq_type_1; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iq_type_1 = wakeups_wu_bits_REG_3_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iq_type_2; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iq_type_2 = wakeups_wu_bits_REG_3_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iq_type_3; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iq_type_3 = wakeups_wu_bits_REG_3_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_0; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_0 = wakeups_wu_bits_REG_3_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_1; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_1 = wakeups_wu_bits_REG_3_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_2; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_2 = wakeups_wu_bits_REG_3_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_3; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_3 = wakeups_wu_bits_REG_3_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_4; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_4 = wakeups_wu_bits_REG_3_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_5; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_5 = wakeups_wu_bits_REG_3_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_6; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_6 = wakeups_wu_bits_REG_3_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_7; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_7 = wakeups_wu_bits_REG_3_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_8; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_8 = wakeups_wu_bits_REG_3_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fu_code_9; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fu_code_9 = wakeups_wu_bits_REG_3_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iw_issued; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_issued = wakeups_wu_bits_REG_3_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_dis_col_sel; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_dis_col_sel = wakeups_wu_bits_REG_3_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [15:0] wakeups_wu_bits_REG_3_uop_br_mask; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_br_mask = wakeups_wu_bits_REG_3_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_3_uop_br_tag; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_br_tag = wakeups_wu_bits_REG_3_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_3_uop_br_type; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_br_type = wakeups_wu_bits_REG_3_uop_br_type; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_sfb; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_sfb = wakeups_wu_bits_REG_3_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_fence; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_fence = wakeups_wu_bits_REG_3_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_fencei; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_fencei = wakeups_wu_bits_REG_3_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_sfence; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_sfence = wakeups_wu_bits_REG_3_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_amo; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_amo = wakeups_wu_bits_REG_3_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_eret; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_eret = wakeups_wu_bits_REG_3_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_3_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_rocc; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_rocc = wakeups_wu_bits_REG_3_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_mov; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_mov = wakeups_wu_bits_REG_3_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_3_uop_ftq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_ftq_idx = wakeups_wu_bits_REG_3_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_edge_inst; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_edge_inst = wakeups_wu_bits_REG_3_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_3_uop_pc_lob; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_pc_lob = wakeups_wu_bits_REG_3_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_taken; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_taken = wakeups_wu_bits_REG_3_uop_taken; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_imm_rename; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_imm_rename = wakeups_wu_bits_REG_3_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_imm_sel; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_imm_sel = wakeups_wu_bits_REG_3_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_3_uop_pimm; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_pimm = wakeups_wu_bits_REG_3_uop_pimm; // @[rename-busytable.scala:47:18, :49:24]
reg [19:0] wakeups_wu_bits_REG_3_uop_imm_packed; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_imm_packed = wakeups_wu_bits_REG_3_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_op1_sel; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_op1_sel = wakeups_wu_bits_REG_3_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_op2_sel; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_op2_sel = wakeups_wu_bits_REG_3_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_3_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_3_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_3_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_3_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_3_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_3_uop_rob_idx; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_rob_idx = wakeups_wu_bits_REG_3_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_3_uop_ldq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_ldq_idx = wakeups_wu_bits_REG_3_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_3_uop_stq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_stq_idx = wakeups_wu_bits_REG_3_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_rxq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_rxq_idx = wakeups_wu_bits_REG_3_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_3_uop_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_pdst = wakeups_wu_bits_REG_3_uop_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_3_uop_prs1; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_prs1 = wakeups_wu_bits_REG_3_uop_prs1; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_3_uop_prs2; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_prs2 = wakeups_wu_bits_REG_3_uop_prs2; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_3_uop_prs3; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_prs3 = wakeups_wu_bits_REG_3_uop_prs3; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_3_uop_ppred; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_ppred = wakeups_wu_bits_REG_3_uop_ppred; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_prs1_busy; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_prs1_busy = wakeups_wu_bits_REG_3_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_prs2_busy; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_prs2_busy = wakeups_wu_bits_REG_3_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_prs3_busy; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_prs3_busy = wakeups_wu_bits_REG_3_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_ppred_busy; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_ppred_busy = wakeups_wu_bits_REG_3_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_3_uop_stale_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_stale_pdst = wakeups_wu_bits_REG_3_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_exception; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_exception = wakeups_wu_bits_REG_3_uop_exception; // @[rename-busytable.scala:47:18, :49:24]
reg [63:0] wakeups_wu_bits_REG_3_uop_exc_cause; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_exc_cause = wakeups_wu_bits_REG_3_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_3_uop_mem_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_mem_cmd = wakeups_wu_bits_REG_3_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_mem_size; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_mem_size = wakeups_wu_bits_REG_3_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_mem_signed; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_mem_signed = wakeups_wu_bits_REG_3_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_uses_ldq; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_uses_ldq = wakeups_wu_bits_REG_3_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_uses_stq; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_uses_stq = wakeups_wu_bits_REG_3_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_is_unique; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_is_unique = wakeups_wu_bits_REG_3_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_flush_on_commit; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_flush_on_commit = wakeups_wu_bits_REG_3_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_csr_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_csr_cmd = wakeups_wu_bits_REG_3_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_3_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_3_uop_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_ldst = wakeups_wu_bits_REG_3_uop_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_3_uop_lrs1; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_lrs1 = wakeups_wu_bits_REG_3_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_3_uop_lrs2; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_lrs2 = wakeups_wu_bits_REG_3_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_3_uop_lrs3; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_lrs3 = wakeups_wu_bits_REG_3_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_dst_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_dst_rtype = wakeups_wu_bits_REG_3_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_lrs1_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_3_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_lrs2_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_3_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_frs3_en; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_frs3_en = wakeups_wu_bits_REG_3_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fcn_dw; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fcn_dw = wakeups_wu_bits_REG_3_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_3_uop_fcn_op; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fcn_op = wakeups_wu_bits_REG_3_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_fp_val; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_val = wakeups_wu_bits_REG_3_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_fp_rm; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_rm = wakeups_wu_bits_REG_3_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_3_uop_fp_typ; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_fp_typ = wakeups_wu_bits_REG_3_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_3_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_3_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_3_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_bp_debug_if; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_bp_debug_if = wakeups_wu_bits_REG_3_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_3_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_3_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_debug_fsrc; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_debug_fsrc = wakeups_wu_bits_REG_3_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_3_uop_debug_tsrc; // @[rename-busytable.scala:49:24]
assign wakeups_3_bits_uop_debug_tsrc = wakeups_wu_bits_REG_3_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24]
wire _wakeups_wu_valid_T_14; // @[rename-busytable.scala:48:34]
wire _busy_table_wb_T_22 = wakeups_4_valid; // @[rename-busytable.scala:47:18, :56:56]
wire wakeups_4_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_4_bits_uop_inst; // @[rename-busytable.scala:47:18]
wire [31:0] wakeups_4_bits_uop_debug_inst; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_rvc; // @[rename-busytable.scala:47:18]
wire [39:0] wakeups_4_bits_uop_debug_pc; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iw_issued; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18]
wire [15:0] wakeups_4_bits_uop_br_mask; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_4_bits_uop_br_tag; // @[rename-busytable.scala:47:18]
wire [3:0] wakeups_4_bits_uop_br_type; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_sfb; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_fence; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_fencei; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_sfence; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_amo; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_eret; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_rocc; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_mov; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_4_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_edge_inst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_4_bits_uop_pc_lob; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_taken; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_imm_rename; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_imm_sel; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_4_bits_uop_pimm; // @[rename-busytable.scala:47:18]
wire [19:0] wakeups_4_bits_uop_imm_packed; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_op1_sel; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_op2_sel; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_4_bits_uop_rob_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_4_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_4_bits_uop_stq_idx; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_4_bits_uop_pdst; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_4_bits_uop_prs1; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_4_bits_uop_prs2; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_4_bits_uop_prs3; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_4_bits_uop_ppred; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18]
wire [6:0] wakeups_4_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_exception; // @[rename-busytable.scala:47:18]
wire [63:0] wakeups_4_bits_uop_exc_cause; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_4_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_mem_size; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_mem_signed; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_uses_stq; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_is_unique; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_4_bits_uop_ldst; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_4_bits_uop_lrs1; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_4_bits_uop_lrs2; // @[rename-busytable.scala:47:18]
wire [5:0] wakeups_4_bits_uop_lrs3; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_frs3_en; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18]
wire [4:0] wakeups_4_bits_uop_fcn_op; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_fp_val; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_fp_rm; // @[rename-busytable.scala:47:18]
wire [1:0] wakeups_4_bits_uop_fp_typ; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18]
wire wakeups_4_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18]
wire [2:0] wakeups_4_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18]
reg wakeups_wu_valid_REG_8; // @[rename-busytable.scala:48:24]
wire [2:0] _wakeups_wu_valid_T_12 = io_child_rebusys_0 & 3'h4; // @[rename-busytable.scala:27:7, :48:72]
wire _wakeups_wu_valid_T_13 = _wakeups_wu_valid_T_12 == 3'h0; // @[rename-busytable.scala:48:{72,92}]
assign _wakeups_wu_valid_T_14 = wakeups_wu_valid_REG_8 & _wakeups_wu_valid_T_13; // @[rename-busytable.scala:48:{24,34,92}]
assign wakeups_4_valid = _wakeups_wu_valid_T_14; // @[rename-busytable.scala:47:18, :48:34]
reg [31:0] wakeups_wu_bits_REG_4_uop_inst; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_inst = wakeups_wu_bits_REG_4_uop_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [31:0] wakeups_wu_bits_REG_4_uop_debug_inst; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_debug_inst = wakeups_wu_bits_REG_4_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_rvc; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_rvc = wakeups_wu_bits_REG_4_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24]
reg [39:0] wakeups_wu_bits_REG_4_uop_debug_pc; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_debug_pc = wakeups_wu_bits_REG_4_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iq_type_0; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iq_type_0 = wakeups_wu_bits_REG_4_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iq_type_1; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iq_type_1 = wakeups_wu_bits_REG_4_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iq_type_2; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iq_type_2 = wakeups_wu_bits_REG_4_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iq_type_3; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iq_type_3 = wakeups_wu_bits_REG_4_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_0; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_0 = wakeups_wu_bits_REG_4_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_1; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_1 = wakeups_wu_bits_REG_4_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_2; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_2 = wakeups_wu_bits_REG_4_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_3; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_3 = wakeups_wu_bits_REG_4_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_4; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_4 = wakeups_wu_bits_REG_4_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_5; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_5 = wakeups_wu_bits_REG_4_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_6; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_6 = wakeups_wu_bits_REG_4_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_7; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_7 = wakeups_wu_bits_REG_4_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_8; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_8 = wakeups_wu_bits_REG_4_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fu_code_9; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fu_code_9 = wakeups_wu_bits_REG_4_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iw_issued; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_issued = wakeups_wu_bits_REG_4_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_4_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_4_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_4_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_4_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_4_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_4_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_4_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_dis_col_sel; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_dis_col_sel = wakeups_wu_bits_REG_4_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [15:0] wakeups_wu_bits_REG_4_uop_br_mask; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_br_mask = wakeups_wu_bits_REG_4_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_4_uop_br_tag; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_br_tag = wakeups_wu_bits_REG_4_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24]
reg [3:0] wakeups_wu_bits_REG_4_uop_br_type; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_br_type = wakeups_wu_bits_REG_4_uop_br_type; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_sfb; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_sfb = wakeups_wu_bits_REG_4_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_fence; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_fence = wakeups_wu_bits_REG_4_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_fencei; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_fencei = wakeups_wu_bits_REG_4_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_sfence; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_sfence = wakeups_wu_bits_REG_4_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_amo; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_amo = wakeups_wu_bits_REG_4_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_eret; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_eret = wakeups_wu_bits_REG_4_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_4_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_rocc; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_rocc = wakeups_wu_bits_REG_4_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_mov; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_mov = wakeups_wu_bits_REG_4_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_4_uop_ftq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_ftq_idx = wakeups_wu_bits_REG_4_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_edge_inst; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_edge_inst = wakeups_wu_bits_REG_4_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_4_uop_pc_lob; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_pc_lob = wakeups_wu_bits_REG_4_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_taken; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_taken = wakeups_wu_bits_REG_4_uop_taken; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_imm_rename; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_imm_rename = wakeups_wu_bits_REG_4_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_imm_sel; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_imm_sel = wakeups_wu_bits_REG_4_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_4_uop_pimm; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_pimm = wakeups_wu_bits_REG_4_uop_pimm; // @[rename-busytable.scala:47:18, :49:24]
reg [19:0] wakeups_wu_bits_REG_4_uop_imm_packed; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_imm_packed = wakeups_wu_bits_REG_4_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_op1_sel; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_op1_sel = wakeups_wu_bits_REG_4_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_op2_sel; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_op2_sel = wakeups_wu_bits_REG_4_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_4_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_4_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_4_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_4_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_4_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_4_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_4_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_4_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_4_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_4_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_4_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_4_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_4_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_4_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_4_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_4_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_4_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_4_uop_rob_idx; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_rob_idx = wakeups_wu_bits_REG_4_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_4_uop_ldq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_ldq_idx = wakeups_wu_bits_REG_4_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_4_uop_stq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_stq_idx = wakeups_wu_bits_REG_4_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_rxq_idx; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_rxq_idx = wakeups_wu_bits_REG_4_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_4_uop_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_pdst = wakeups_wu_bits_REG_4_uop_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_4_uop_prs1; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_prs1 = wakeups_wu_bits_REG_4_uop_prs1; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_4_uop_prs2; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_prs2 = wakeups_wu_bits_REG_4_uop_prs2; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_4_uop_prs3; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_prs3 = wakeups_wu_bits_REG_4_uop_prs3; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_4_uop_ppred; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_ppred = wakeups_wu_bits_REG_4_uop_ppred; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_prs1_busy; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_prs1_busy = wakeups_wu_bits_REG_4_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_prs2_busy; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_prs2_busy = wakeups_wu_bits_REG_4_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_prs3_busy; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_prs3_busy = wakeups_wu_bits_REG_4_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_ppred_busy; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_ppred_busy = wakeups_wu_bits_REG_4_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24]
reg [6:0] wakeups_wu_bits_REG_4_uop_stale_pdst; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_stale_pdst = wakeups_wu_bits_REG_4_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_exception; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_exception = wakeups_wu_bits_REG_4_uop_exception; // @[rename-busytable.scala:47:18, :49:24]
reg [63:0] wakeups_wu_bits_REG_4_uop_exc_cause; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_exc_cause = wakeups_wu_bits_REG_4_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_4_uop_mem_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_mem_cmd = wakeups_wu_bits_REG_4_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_mem_size; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_mem_size = wakeups_wu_bits_REG_4_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_mem_signed; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_mem_signed = wakeups_wu_bits_REG_4_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_uses_ldq; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_uses_ldq = wakeups_wu_bits_REG_4_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_uses_stq; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_uses_stq = wakeups_wu_bits_REG_4_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_is_unique; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_is_unique = wakeups_wu_bits_REG_4_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_flush_on_commit; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_flush_on_commit = wakeups_wu_bits_REG_4_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_csr_cmd; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_csr_cmd = wakeups_wu_bits_REG_4_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_4_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_4_uop_ldst; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_ldst = wakeups_wu_bits_REG_4_uop_ldst; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_4_uop_lrs1; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_lrs1 = wakeups_wu_bits_REG_4_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_4_uop_lrs2; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_lrs2 = wakeups_wu_bits_REG_4_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24]
reg [5:0] wakeups_wu_bits_REG_4_uop_lrs3; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_lrs3 = wakeups_wu_bits_REG_4_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_dst_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_dst_rtype = wakeups_wu_bits_REG_4_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_lrs1_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_4_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_lrs2_rtype; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_4_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_frs3_en; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_frs3_en = wakeups_wu_bits_REG_4_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fcn_dw; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fcn_dw = wakeups_wu_bits_REG_4_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24]
reg [4:0] wakeups_wu_bits_REG_4_uop_fcn_op; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fcn_op = wakeups_wu_bits_REG_4_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_fp_val; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_val = wakeups_wu_bits_REG_4_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_fp_rm; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_rm = wakeups_wu_bits_REG_4_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24]
reg [1:0] wakeups_wu_bits_REG_4_uop_fp_typ; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_fp_typ = wakeups_wu_bits_REG_4_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_4_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_4_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_4_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_bp_debug_if; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_bp_debug_if = wakeups_wu_bits_REG_4_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24]
reg wakeups_wu_bits_REG_4_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_4_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_debug_fsrc; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_debug_fsrc = wakeups_wu_bits_REG_4_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24]
reg [2:0] wakeups_wu_bits_REG_4_uop_debug_tsrc; // @[rename-busytable.scala:49:24]
assign wakeups_4_bits_uop_debug_tsrc = wakeups_wu_bits_REG_4_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24]
reg [99:0] busy_table; // @[rename-busytable.scala:53:27]
assign io_debug_busytable = busy_table; // @[rename-busytable.scala:27:7, :53:27]
wire [127:0] _GEN = 128'h1 << wakeups_0_bits_uop_pdst; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_wb_T; // @[OneHot.scala:58:35]
assign _busy_table_wb_T = _GEN; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_12; // @[OneHot.scala:58:35]
assign _busy_table_next_T_12 = _GEN; // @[OneHot.scala:58:35]
wire _busy_table_wb_T_1 = ~wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :56:59]
wire _busy_table_wb_T_2 = wakeups_0_valid & _busy_table_wb_T_1; // @[rename-busytable.scala:47:18, :56:{56,59}]
wire [99:0] _busy_table_wb_T_3 = {100{_busy_table_wb_T_2}}; // @[rename-busytable.scala:56:{37,56}]
wire [127:0] _busy_table_wb_T_4 = {28'h0, _busy_table_wb_T[99:0] & _busy_table_wb_T_3}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_0 = 128'h1 << wakeups_1_bits_uop_pdst; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_wb_T_5; // @[OneHot.scala:58:35]
assign _busy_table_wb_T_5 = _GEN_0; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_16; // @[OneHot.scala:58:35]
assign _busy_table_next_T_16 = _GEN_0; // @[OneHot.scala:58:35]
wire [99:0] _busy_table_wb_T_8 = {100{_busy_table_wb_T_7}}; // @[rename-busytable.scala:56:{37,56}]
wire [127:0] _busy_table_wb_T_9 = {28'h0, _busy_table_wb_T_5[99:0] & _busy_table_wb_T_8}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_1 = 128'h1 << wakeups_2_bits_uop_pdst; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_wb_T_10; // @[OneHot.scala:58:35]
assign _busy_table_wb_T_10 = _GEN_1; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_20; // @[OneHot.scala:58:35]
assign _busy_table_next_T_20 = _GEN_1; // @[OneHot.scala:58:35]
wire [99:0] _busy_table_wb_T_13 = {100{_busy_table_wb_T_12}}; // @[rename-busytable.scala:56:{37,56}]
wire [127:0] _busy_table_wb_T_14 = {28'h0, _busy_table_wb_T_10[99:0] & _busy_table_wb_T_13}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_2 = 128'h1 << wakeups_3_bits_uop_pdst; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_wb_T_15; // @[OneHot.scala:58:35]
assign _busy_table_wb_T_15 = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_24; // @[OneHot.scala:58:35]
assign _busy_table_next_T_24 = _GEN_2; // @[OneHot.scala:58:35]
wire [99:0] _busy_table_wb_T_18 = {100{_busy_table_wb_T_17}}; // @[rename-busytable.scala:56:{37,56}]
wire [127:0] _busy_table_wb_T_19 = {28'h0, _busy_table_wb_T_15[99:0] & _busy_table_wb_T_18}; // @[OneHot.scala:58:35]
wire [127:0] _GEN_3 = 128'h1 << wakeups_4_bits_uop_pdst; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_wb_T_20; // @[OneHot.scala:58:35]
assign _busy_table_wb_T_20 = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_28; // @[OneHot.scala:58:35]
assign _busy_table_next_T_28 = _GEN_3; // @[OneHot.scala:58:35]
wire [99:0] _busy_table_wb_T_23 = {100{_busy_table_wb_T_22}}; // @[rename-busytable.scala:56:{37,56}]
wire [127:0] _busy_table_wb_T_24 = {28'h0, _busy_table_wb_T_20[99:0] & _busy_table_wb_T_23}; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_wb_T_25 = _busy_table_wb_T_4 | _busy_table_wb_T_9; // @[rename-busytable.scala:56:31, :57:14]
wire [127:0] _busy_table_wb_T_26 = _busy_table_wb_T_25 | _busy_table_wb_T_14; // @[rename-busytable.scala:56:31, :57:14]
wire [127:0] _busy_table_wb_T_27 = _busy_table_wb_T_26 | _busy_table_wb_T_19; // @[rename-busytable.scala:56:31, :57:14]
wire [127:0] _busy_table_wb_T_28 = _busy_table_wb_T_27 | _busy_table_wb_T_24; // @[rename-busytable.scala:56:31, :57:14]
wire [127:0] _busy_table_wb_T_29 = ~_busy_table_wb_T_28; // @[rename-busytable.scala:55:36, :57:14]
wire [127:0] busy_table_wb = {28'h0, _busy_table_wb_T_29[99:0] & busy_table}; // @[rename-busytable.scala:53:27, :55:{34,36}, :56:31]
wire [127:0] _busy_table_next_T = 128'h1 << io_ren_uops_0_pdst_0; // @[OneHot.scala:58:35]
wire [99:0] _busy_table_next_T_1 = {100{io_rebusy_reqs_0_0}}; // @[rename-busytable.scala:27:7, :61:57]
wire [127:0] _busy_table_next_T_2 = {28'h0, _busy_table_next_T[99:0] & _busy_table_next_T_1}; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_3 = 128'h1 << io_ren_uops_1_pdst_0; // @[OneHot.scala:58:35]
wire [99:0] _busy_table_next_T_4 = {100{io_rebusy_reqs_1_0}}; // @[rename-busytable.scala:27:7, :61:57]
wire [127:0] _busy_table_next_T_5 = {28'h0, _busy_table_next_T_3[99:0] & _busy_table_next_T_4}; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_6 = 128'h1 << io_ren_uops_2_pdst_0; // @[OneHot.scala:58:35]
wire [99:0] _busy_table_next_T_7 = {100{io_rebusy_reqs_2_0}}; // @[rename-busytable.scala:27:7, :61:57]
wire [127:0] _busy_table_next_T_8 = {28'h0, _busy_table_next_T_6[99:0] & _busy_table_next_T_7}; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_9 = _busy_table_next_T_2 | _busy_table_next_T_5; // @[rename-busytable.scala:61:{51,82}]
wire [127:0] _busy_table_next_T_10 = _busy_table_next_T_9 | _busy_table_next_T_8; // @[rename-busytable.scala:61:{51,82}]
wire [127:0] _busy_table_next_T_11 = busy_table_wb | _busy_table_next_T_10; // @[rename-busytable.scala:55:34, :59:39, :61:82]
wire _GEN_4 = wakeups_0_valid & wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :63:56]
wire _busy_table_next_T_13; // @[rename-busytable.scala:63:56]
assign _busy_table_next_T_13 = _GEN_4; // @[rename-busytable.scala:63:56]
wire _io_busy_resps_0_prs1_busy_T_2; // @[rename-busytable.scala:79:82]
assign _io_busy_resps_0_prs1_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :79:82]
wire _io_busy_resps_0_prs2_busy_T_2; // @[rename-busytable.scala:82:82]
assign _io_busy_resps_0_prs2_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :82:82]
wire _io_busy_resps_0_prs3_busy_T_2; // @[rename-busytable.scala:85:82]
assign _io_busy_resps_0_prs3_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :85:82]
wire _io_busy_resps_1_prs1_busy_T_2; // @[rename-busytable.scala:79:82]
assign _io_busy_resps_1_prs1_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :79:82]
wire _io_busy_resps_1_prs2_busy_T_2; // @[rename-busytable.scala:82:82]
assign _io_busy_resps_1_prs2_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :82:82]
wire _io_busy_resps_1_prs3_busy_T_2; // @[rename-busytable.scala:85:82]
assign _io_busy_resps_1_prs3_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :85:82]
wire _io_busy_resps_2_prs1_busy_T_2; // @[rename-busytable.scala:79:82]
assign _io_busy_resps_2_prs1_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :79:82]
wire _io_busy_resps_2_prs2_busy_T_2; // @[rename-busytable.scala:82:82]
assign _io_busy_resps_2_prs2_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :82:82]
wire _io_busy_resps_2_prs3_busy_T_2; // @[rename-busytable.scala:85:82]
assign _io_busy_resps_2_prs3_busy_T_2 = _GEN_4; // @[rename-busytable.scala:63:56, :85:82]
wire [99:0] _busy_table_next_T_14 = {100{_busy_table_next_T_13}}; // @[rename-busytable.scala:63:{37,56}]
wire [127:0] _busy_table_next_T_15 = {28'h0, _busy_table_next_T_12[99:0] & _busy_table_next_T_14}; // @[OneHot.scala:58:35]
wire [127:0] _busy_table_next_T_32 = _busy_table_next_T_15; // @[rename-busytable.scala:63:31, :64:14]
wire [127:0] _busy_table_next_T_33 = _busy_table_next_T_32; // @[rename-busytable.scala:64:14]
wire [127:0] _busy_table_next_T_34 = _busy_table_next_T_33; // @[rename-busytable.scala:64:14]
wire [127:0] _busy_table_next_T_35 = _busy_table_next_T_34; // @[rename-busytable.scala:64:14]
wire [127:0] busy_table_next = _busy_table_next_T_11 | _busy_table_next_T_35; // @[rename-busytable.scala:59:39, :62:5, :64:14]
wire _prs1_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_0 = wakeups_0_valid & _prs1_match_T; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_1 = wakeups_1_valid & _prs1_match_T_1; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_2 = wakeups_2_valid & _prs1_match_T_2; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_3 = wakeups_3_valid & _prs1_match_T_3; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_4 = wakeups_4_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_4 = wakeups_4_valid & _prs1_match_T_4; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs2_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_0 = wakeups_0_valid & _prs2_match_T; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_1 = wakeups_1_valid & _prs2_match_T_1; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_2 = wakeups_2_valid & _prs2_match_T_2; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_3 = wakeups_3_valid & _prs2_match_T_3; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_4 = wakeups_4_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_4 = wakeups_4_valid & _prs2_match_T_4; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs3_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_0 = wakeups_0_valid & _prs3_match_T; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_1 = wakeups_1_valid & _prs3_match_T_1; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_2 = wakeups_2_valid & _prs3_match_T_2; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_3 = wakeups_3_valid & _prs3_match_T_3; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_4 = wakeups_4_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_4 = wakeups_4_valid & _prs3_match_T_4; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire [99:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45]
wire _io_busy_resps_0_prs1_busy_T_1 = _io_busy_resps_0_prs1_busy_T[0]; // @[rename-busytable.scala:74:45]
wire [99:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45]
wire _io_busy_resps_0_prs2_busy_T_1 = _io_busy_resps_0_prs2_busy_T[0]; // @[rename-busytable.scala:75:45]
wire [99:0] _io_busy_resps_0_prs3_busy_T = busy_table >> io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45]
wire _io_busy_resps_0_prs3_busy_T_1 = _io_busy_resps_0_prs3_busy_T[0]; // @[rename-busytable.scala:76:45]
wire _io_busy_resps_0_prs1_busy_T_7 = prs1_match_0 & _io_busy_resps_0_prs1_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_T_12 = _io_busy_resps_0_prs1_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_T_13 = _io_busy_resps_0_prs1_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_T_14 = _io_busy_resps_0_prs1_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_T_15 = _io_busy_resps_0_prs1_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs1_busy_WIRE = _io_busy_resps_0_prs1_busy_T_15; // @[Mux.scala:30:73]
assign io_busy_resps_0_prs1_busy_0 = prs1_match_0 | prs1_match_1 | prs1_match_2 | prs1_match_3 | prs1_match_4 ? _io_busy_resps_0_prs1_busy_WIRE : _io_busy_resps_0_prs1_busy_T_1; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_7 = prs2_match_0 & _io_busy_resps_0_prs2_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_12 = _io_busy_resps_0_prs2_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_13 = _io_busy_resps_0_prs2_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_14 = _io_busy_resps_0_prs2_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_T_15 = _io_busy_resps_0_prs2_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs2_busy_WIRE = _io_busy_resps_0_prs2_busy_T_15; // @[Mux.scala:30:73]
assign io_busy_resps_0_prs2_busy_0 = prs2_match_0 | prs2_match_1 | prs2_match_2 | prs2_match_3 | prs2_match_4 ? _io_busy_resps_0_prs2_busy_WIRE : _io_busy_resps_0_prs2_busy_T_1; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_7 = prs3_match_0 & _io_busy_resps_0_prs3_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_12 = _io_busy_resps_0_prs3_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_13 = _io_busy_resps_0_prs3_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_14 = _io_busy_resps_0_prs3_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_T_15 = _io_busy_resps_0_prs3_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_0_prs3_busy_WIRE = _io_busy_resps_0_prs3_busy_T_15; // @[Mux.scala:30:73]
wire _prs1_match_T_5 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_0_1 = wakeups_0_valid & _prs1_match_T_5; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_6 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_1_1 = wakeups_1_valid & _prs1_match_T_6; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_7 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_2_1 = wakeups_2_valid & _prs1_match_T_7; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_8 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_3_1 = wakeups_3_valid & _prs1_match_T_8; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_9 = wakeups_4_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_4_1 = wakeups_4_valid & _prs1_match_T_9; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs2_match_T_5 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_0_1 = wakeups_0_valid & _prs2_match_T_5; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_6 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_1_1 = wakeups_1_valid & _prs2_match_T_6; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_7 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_2_1 = wakeups_2_valid & _prs2_match_T_7; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_8 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_3_1 = wakeups_3_valid & _prs2_match_T_8; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_9 = wakeups_4_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_4_1 = wakeups_4_valid & _prs2_match_T_9; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs3_match_T_5 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_0_1 = wakeups_0_valid & _prs3_match_T_5; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_6 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_1_1 = wakeups_1_valid & _prs3_match_T_6; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_7 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_2_1 = wakeups_2_valid & _prs3_match_T_7; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_8 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_3_1 = wakeups_3_valid & _prs3_match_T_8; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_9 = wakeups_4_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_4_1 = wakeups_4_valid & _prs3_match_T_9; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire [99:0] _io_busy_resps_1_prs1_busy_T = busy_table >> io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45]
wire _io_busy_resps_1_prs1_busy_T_1 = _io_busy_resps_1_prs1_busy_T[0]; // @[rename-busytable.scala:74:45]
wire [99:0] _io_busy_resps_1_prs2_busy_T = busy_table >> io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45]
wire _io_busy_resps_1_prs2_busy_T_1 = _io_busy_resps_1_prs2_busy_T[0]; // @[rename-busytable.scala:75:45]
wire [99:0] _io_busy_resps_1_prs3_busy_T = busy_table >> io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45]
wire _io_busy_resps_1_prs3_busy_T_1 = _io_busy_resps_1_prs3_busy_T[0]; // @[rename-busytable.scala:76:45]
wire _io_busy_resps_1_prs1_busy_T_7 = prs1_match_0_1 & _io_busy_resps_1_prs1_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_12 = _io_busy_resps_1_prs1_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_13 = _io_busy_resps_1_prs1_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_14 = _io_busy_resps_1_prs1_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_T_15 = _io_busy_resps_1_prs1_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs1_busy_WIRE = _io_busy_resps_1_prs1_busy_T_15; // @[Mux.scala:30:73]
assign io_busy_resps_1_prs1_busy_0 = prs1_match_0_1 | prs1_match_1_1 | prs1_match_2_1 | prs1_match_3_1 | prs1_match_4_1 ? _io_busy_resps_1_prs1_busy_WIRE : _io_busy_resps_1_prs1_busy_T_1; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_7 = prs2_match_0_1 & _io_busy_resps_1_prs2_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_12 = _io_busy_resps_1_prs2_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_13 = _io_busy_resps_1_prs2_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_14 = _io_busy_resps_1_prs2_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_T_15 = _io_busy_resps_1_prs2_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs2_busy_WIRE = _io_busy_resps_1_prs2_busy_T_15; // @[Mux.scala:30:73]
assign io_busy_resps_1_prs2_busy_0 = prs2_match_0_1 | prs2_match_1_1 | prs2_match_2_1 | prs2_match_3_1 | prs2_match_4_1 ? _io_busy_resps_1_prs2_busy_WIRE : _io_busy_resps_1_prs2_busy_T_1; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_7 = prs3_match_0_1 & _io_busy_resps_1_prs3_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_12 = _io_busy_resps_1_prs3_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_13 = _io_busy_resps_1_prs3_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_14 = _io_busy_resps_1_prs3_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_T_15 = _io_busy_resps_1_prs3_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_1_prs3_busy_WIRE = _io_busy_resps_1_prs3_busy_T_15; // @[Mux.scala:30:73]
wire _prs1_match_T_10 = wakeups_0_bits_uop_pdst == io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_0_2 = wakeups_0_valid & _prs1_match_T_10; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_11 = wakeups_1_bits_uop_pdst == io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_1_2 = wakeups_1_valid & _prs1_match_T_11; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_12 = wakeups_2_bits_uop_pdst == io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_2_2 = wakeups_2_valid & _prs1_match_T_12; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_13 = wakeups_3_bits_uop_pdst == io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_3_2 = wakeups_3_valid & _prs1_match_T_13; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs1_match_T_14 = wakeups_4_bits_uop_pdst == io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68]
wire prs1_match_4_2 = wakeups_4_valid & _prs1_match_T_14; // @[rename-busytable.scala:47:18, :70:{49,68}]
wire _prs2_match_T_10 = wakeups_0_bits_uop_pdst == io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_0_2 = wakeups_0_valid & _prs2_match_T_10; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_11 = wakeups_1_bits_uop_pdst == io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_1_2 = wakeups_1_valid & _prs2_match_T_11; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_12 = wakeups_2_bits_uop_pdst == io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_2_2 = wakeups_2_valid & _prs2_match_T_12; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_13 = wakeups_3_bits_uop_pdst == io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_3_2 = wakeups_3_valid & _prs2_match_T_13; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs2_match_T_14 = wakeups_4_bits_uop_pdst == io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68]
wire prs2_match_4_2 = wakeups_4_valid & _prs2_match_T_14; // @[rename-busytable.scala:47:18, :71:{49,68}]
wire _prs3_match_T_10 = wakeups_0_bits_uop_pdst == io_ren_uops_2_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_0_2 = wakeups_0_valid & _prs3_match_T_10; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_11 = wakeups_1_bits_uop_pdst == io_ren_uops_2_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_1_2 = wakeups_1_valid & _prs3_match_T_11; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_12 = wakeups_2_bits_uop_pdst == io_ren_uops_2_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_2_2 = wakeups_2_valid & _prs3_match_T_12; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_13 = wakeups_3_bits_uop_pdst == io_ren_uops_2_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_3_2 = wakeups_3_valid & _prs3_match_T_13; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire _prs3_match_T_14 = wakeups_4_bits_uop_pdst == io_ren_uops_2_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68]
wire prs3_match_4_2 = wakeups_4_valid & _prs3_match_T_14; // @[rename-busytable.scala:47:18, :72:{49,68}]
wire [99:0] _io_busy_resps_2_prs1_busy_T = busy_table >> io_ren_uops_2_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45]
wire _io_busy_resps_2_prs1_busy_T_1 = _io_busy_resps_2_prs1_busy_T[0]; // @[rename-busytable.scala:74:45]
wire [99:0] _io_busy_resps_2_prs2_busy_T = busy_table >> io_ren_uops_2_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45]
wire _io_busy_resps_2_prs2_busy_T_1 = _io_busy_resps_2_prs2_busy_T[0]; // @[rename-busytable.scala:75:45]
wire [99:0] _io_busy_resps_2_prs3_busy_T = busy_table >> io_ren_uops_2_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45]
wire _io_busy_resps_2_prs3_busy_T_1 = _io_busy_resps_2_prs3_busy_T[0]; // @[rename-busytable.scala:76:45]
wire _io_busy_resps_2_prs1_busy_T_7 = prs1_match_0_2 & _io_busy_resps_2_prs1_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_12 = _io_busy_resps_2_prs1_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_13 = _io_busy_resps_2_prs1_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_14 = _io_busy_resps_2_prs1_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_T_15 = _io_busy_resps_2_prs1_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs1_busy_WIRE = _io_busy_resps_2_prs1_busy_T_15; // @[Mux.scala:30:73]
assign io_busy_resps_2_prs1_busy_0 = prs1_match_0_2 | prs1_match_1_2 | prs1_match_2_2 | prs1_match_3_2 | prs1_match_4_2 ? _io_busy_resps_2_prs1_busy_WIRE : _io_busy_resps_2_prs1_busy_T_1; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_7 = prs2_match_0_2 & _io_busy_resps_2_prs2_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_12 = _io_busy_resps_2_prs2_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_13 = _io_busy_resps_2_prs2_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_14 = _io_busy_resps_2_prs2_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_T_15 = _io_busy_resps_2_prs2_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs2_busy_WIRE = _io_busy_resps_2_prs2_busy_T_15; // @[Mux.scala:30:73]
assign io_busy_resps_2_prs2_busy_0 = prs2_match_0_2 | prs2_match_1_2 | prs2_match_2_2 | prs2_match_3_2 | prs2_match_4_2 ? _io_busy_resps_2_prs2_busy_WIRE : _io_busy_resps_2_prs2_busy_T_1; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_7 = prs3_match_0_2 & _io_busy_resps_2_prs3_busy_T_2; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_12 = _io_busy_resps_2_prs3_busy_T_7; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_13 = _io_busy_resps_2_prs3_busy_T_12; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_14 = _io_busy_resps_2_prs3_busy_T_13; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_T_15 = _io_busy_resps_2_prs3_busy_T_14; // @[Mux.scala:30:73]
wire _io_busy_resps_2_prs3_busy_WIRE = _io_busy_resps_2_prs3_busy_T_15; // @[Mux.scala:30:73]
always @(posedge clock) begin // @[rename-busytable.scala:27:7]
wakeups_wu_valid_REG <= io_wakeups_0_valid_0; // @[rename-busytable.scala:27:7, :48:24]
wakeups_wu_valid_REG_1 <= io_wakeups_0_bits_speculative_mask_0; // @[rename-busytable.scala:27:7, :48:46]
wakeups_wu_bits_REG_uop_inst <= io_wakeups_0_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_debug_inst <= io_wakeups_0_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_rvc <= io_wakeups_0_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_debug_pc <= io_wakeups_0_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iq_type_0 <= io_wakeups_0_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iq_type_1 <= io_wakeups_0_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iq_type_2 <= io_wakeups_0_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iq_type_3 <= io_wakeups_0_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_0 <= io_wakeups_0_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_1 <= io_wakeups_0_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_2 <= io_wakeups_0_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_3 <= io_wakeups_0_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_4 <= io_wakeups_0_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_5 <= io_wakeups_0_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_6 <= io_wakeups_0_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_7 <= io_wakeups_0_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_8 <= io_wakeups_0_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fu_code_9 <= io_wakeups_0_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_issued <= io_wakeups_0_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_issued_partial_agen <= io_wakeups_0_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_issued_partial_dgen <= io_wakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_p1_speculative_child <= io_wakeups_0_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_p2_speculative_child <= io_wakeups_0_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_p1_bypass_hint <= io_wakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_p2_bypass_hint <= io_wakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_iw_p3_bypass_hint <= io_wakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_dis_col_sel <= io_wakeups_0_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_br_mask <= io_wakeups_0_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_br_tag <= io_wakeups_0_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_br_type <= io_wakeups_0_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_sfb <= io_wakeups_0_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_fence <= io_wakeups_0_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_fencei <= io_wakeups_0_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_sfence <= io_wakeups_0_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_amo <= io_wakeups_0_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_eret <= io_wakeups_0_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_sys_pc2epc <= io_wakeups_0_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_rocc <= io_wakeups_0_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_mov <= io_wakeups_0_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_ftq_idx <= io_wakeups_0_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_edge_inst <= io_wakeups_0_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_pc_lob <= io_wakeups_0_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_taken <= io_wakeups_0_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_imm_rename <= io_wakeups_0_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_imm_sel <= io_wakeups_0_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_pimm <= io_wakeups_0_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_imm_packed <= io_wakeups_0_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_op1_sel <= io_wakeups_0_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_op2_sel <= io_wakeups_0_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_ldst <= io_wakeups_0_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_wen <= io_wakeups_0_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_ren1 <= io_wakeups_0_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_ren2 <= io_wakeups_0_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_ren3 <= io_wakeups_0_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_swap12 <= io_wakeups_0_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_swap23 <= io_wakeups_0_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn <= io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut <= io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_fromint <= io_wakeups_0_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_toint <= io_wakeups_0_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe <= io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_fma <= io_wakeups_0_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_div <= io_wakeups_0_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_sqrt <= io_wakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_wflags <= io_wakeups_0_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_ctrl_vec <= io_wakeups_0_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_rob_idx <= io_wakeups_0_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_ldq_idx <= io_wakeups_0_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_stq_idx <= io_wakeups_0_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_rxq_idx <= io_wakeups_0_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_pdst <= io_wakeups_0_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_prs1 <= io_wakeups_0_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_prs2 <= io_wakeups_0_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_prs3 <= io_wakeups_0_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_ppred <= io_wakeups_0_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_prs1_busy <= io_wakeups_0_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_prs2_busy <= io_wakeups_0_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_prs3_busy <= io_wakeups_0_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_ppred_busy <= io_wakeups_0_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_stale_pdst <= io_wakeups_0_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_exception <= io_wakeups_0_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_exc_cause <= io_wakeups_0_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_mem_cmd <= io_wakeups_0_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_mem_size <= io_wakeups_0_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_mem_signed <= io_wakeups_0_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_uses_ldq <= io_wakeups_0_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_uses_stq <= io_wakeups_0_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_is_unique <= io_wakeups_0_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_flush_on_commit <= io_wakeups_0_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_csr_cmd <= io_wakeups_0_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_ldst_is_rs1 <= io_wakeups_0_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_ldst <= io_wakeups_0_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_lrs1 <= io_wakeups_0_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_lrs2 <= io_wakeups_0_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_lrs3 <= io_wakeups_0_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_dst_rtype <= io_wakeups_0_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_lrs1_rtype <= io_wakeups_0_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_lrs2_rtype <= io_wakeups_0_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_frs3_en <= io_wakeups_0_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fcn_dw <= io_wakeups_0_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fcn_op <= io_wakeups_0_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_val <= io_wakeups_0_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_rm <= io_wakeups_0_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_fp_typ <= io_wakeups_0_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_xcpt_pf_if <= io_wakeups_0_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_xcpt_ae_if <= io_wakeups_0_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_xcpt_ma_if <= io_wakeups_0_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_bp_debug_if <= io_wakeups_0_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_bp_xcpt_if <= io_wakeups_0_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_debug_fsrc <= io_wakeups_0_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_uop_debug_tsrc <= io_wakeups_0_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_bypassable <= io_wakeups_0_bits_bypassable_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_speculative_mask <= io_wakeups_0_bits_speculative_mask_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_rebusy <= io_wakeups_0_bits_rebusy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_valid_REG_2 <= io_wakeups_1_valid_0; // @[rename-busytable.scala:27:7, :48:24]
wakeups_wu_bits_REG_1_uop_inst <= io_wakeups_1_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_debug_inst <= io_wakeups_1_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_rvc <= io_wakeups_1_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_debug_pc <= io_wakeups_1_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iq_type_0 <= io_wakeups_1_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iq_type_1 <= io_wakeups_1_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iq_type_2 <= io_wakeups_1_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iq_type_3 <= io_wakeups_1_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_0 <= io_wakeups_1_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_1 <= io_wakeups_1_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_2 <= io_wakeups_1_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_3 <= io_wakeups_1_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_4 <= io_wakeups_1_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_5 <= io_wakeups_1_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_6 <= io_wakeups_1_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_7 <= io_wakeups_1_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_8 <= io_wakeups_1_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fu_code_9 <= io_wakeups_1_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_issued <= io_wakeups_1_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen <= io_wakeups_1_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen <= io_wakeups_1_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child <= io_wakeups_1_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child <= io_wakeups_1_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint <= io_wakeups_1_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint <= io_wakeups_1_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint <= io_wakeups_1_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_dis_col_sel <= io_wakeups_1_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_br_mask <= io_wakeups_1_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_br_tag <= io_wakeups_1_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_br_type <= io_wakeups_1_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_sfb <= io_wakeups_1_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_fence <= io_wakeups_1_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_fencei <= io_wakeups_1_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_sfence <= io_wakeups_1_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_amo <= io_wakeups_1_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_eret <= io_wakeups_1_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_sys_pc2epc <= io_wakeups_1_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_rocc <= io_wakeups_1_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_mov <= io_wakeups_1_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_ftq_idx <= io_wakeups_1_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_edge_inst <= io_wakeups_1_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_pc_lob <= io_wakeups_1_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_taken <= io_wakeups_1_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_imm_rename <= io_wakeups_1_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_imm_sel <= io_wakeups_1_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_pimm <= io_wakeups_1_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_imm_packed <= io_wakeups_1_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_op1_sel <= io_wakeups_1_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_op2_sel <= io_wakeups_1_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst <= io_wakeups_1_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_wen <= io_wakeups_1_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1 <= io_wakeups_1_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2 <= io_wakeups_1_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3 <= io_wakeups_1_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12 <= io_wakeups_1_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23 <= io_wakeups_1_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn <= io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut <= io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint <= io_wakeups_1_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_toint <= io_wakeups_1_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe <= io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_fma <= io_wakeups_1_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_div <= io_wakeups_1_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt <= io_wakeups_1_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags <= io_wakeups_1_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_ctrl_vec <= io_wakeups_1_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_rob_idx <= io_wakeups_1_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_ldq_idx <= io_wakeups_1_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_stq_idx <= io_wakeups_1_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_rxq_idx <= io_wakeups_1_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_pdst <= io_wakeups_1_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_prs1 <= io_wakeups_1_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_prs2 <= io_wakeups_1_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_prs3 <= io_wakeups_1_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_ppred <= io_wakeups_1_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_prs1_busy <= io_wakeups_1_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_prs2_busy <= io_wakeups_1_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_prs3_busy <= io_wakeups_1_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_ppred_busy <= io_wakeups_1_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_stale_pdst <= io_wakeups_1_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_exception <= io_wakeups_1_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_exc_cause <= io_wakeups_1_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_mem_cmd <= io_wakeups_1_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_mem_size <= io_wakeups_1_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_mem_signed <= io_wakeups_1_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_uses_ldq <= io_wakeups_1_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_uses_stq <= io_wakeups_1_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_is_unique <= io_wakeups_1_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_flush_on_commit <= io_wakeups_1_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_csr_cmd <= io_wakeups_1_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_ldst_is_rs1 <= io_wakeups_1_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_ldst <= io_wakeups_1_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_lrs1 <= io_wakeups_1_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_lrs2 <= io_wakeups_1_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_lrs3 <= io_wakeups_1_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_dst_rtype <= io_wakeups_1_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_lrs1_rtype <= io_wakeups_1_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_lrs2_rtype <= io_wakeups_1_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_frs3_en <= io_wakeups_1_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fcn_dw <= io_wakeups_1_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fcn_op <= io_wakeups_1_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_val <= io_wakeups_1_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_rm <= io_wakeups_1_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_fp_typ <= io_wakeups_1_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_xcpt_pf_if <= io_wakeups_1_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_xcpt_ae_if <= io_wakeups_1_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_xcpt_ma_if <= io_wakeups_1_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_bp_debug_if <= io_wakeups_1_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_bp_xcpt_if <= io_wakeups_1_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_debug_fsrc <= io_wakeups_1_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_1_uop_debug_tsrc <= io_wakeups_1_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_valid_REG_4 <= io_wakeups_2_valid_0; // @[rename-busytable.scala:27:7, :48:24]
wakeups_wu_bits_REG_2_uop_inst <= io_wakeups_2_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_debug_inst <= io_wakeups_2_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_rvc <= io_wakeups_2_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_debug_pc <= io_wakeups_2_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iq_type_0 <= io_wakeups_2_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iq_type_1 <= io_wakeups_2_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iq_type_2 <= io_wakeups_2_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iq_type_3 <= io_wakeups_2_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_0 <= io_wakeups_2_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_1 <= io_wakeups_2_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_2 <= io_wakeups_2_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_3 <= io_wakeups_2_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_4 <= io_wakeups_2_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_5 <= io_wakeups_2_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_6 <= io_wakeups_2_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_7 <= io_wakeups_2_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_8 <= io_wakeups_2_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fu_code_9 <= io_wakeups_2_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iw_issued <= io_wakeups_2_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen <= 1'h0; // @[rename-busytable.scala:49:24]
wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen <= 1'h0; // @[rename-busytable.scala:49:24]
wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child <= io_wakeups_2_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child <= io_wakeups_2_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint <= io_wakeups_2_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint <= io_wakeups_2_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint <= io_wakeups_2_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_dis_col_sel <= io_wakeups_2_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_br_mask <= io_wakeups_2_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_br_tag <= io_wakeups_2_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_br_type <= io_wakeups_2_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_sfb <= io_wakeups_2_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_fence <= io_wakeups_2_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_fencei <= io_wakeups_2_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_sfence <= io_wakeups_2_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_amo <= io_wakeups_2_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_eret <= io_wakeups_2_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_sys_pc2epc <= io_wakeups_2_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_rocc <= io_wakeups_2_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_mov <= io_wakeups_2_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_ftq_idx <= io_wakeups_2_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_edge_inst <= io_wakeups_2_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_pc_lob <= io_wakeups_2_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_taken <= io_wakeups_2_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_imm_rename <= io_wakeups_2_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_imm_sel <= io_wakeups_2_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_pimm <= io_wakeups_2_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_imm_packed <= io_wakeups_2_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_op1_sel <= io_wakeups_2_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_op2_sel <= io_wakeups_2_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst <= io_wakeups_2_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_wen <= io_wakeups_2_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1 <= io_wakeups_2_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2 <= io_wakeups_2_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3 <= io_wakeups_2_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12 <= io_wakeups_2_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23 <= io_wakeups_2_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn <= io_wakeups_2_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut <= io_wakeups_2_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint <= io_wakeups_2_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_toint <= io_wakeups_2_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe <= io_wakeups_2_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_fma <= io_wakeups_2_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_div <= io_wakeups_2_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt <= io_wakeups_2_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags <= io_wakeups_2_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_ctrl_vec <= io_wakeups_2_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_rob_idx <= io_wakeups_2_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_ldq_idx <= io_wakeups_2_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_stq_idx <= io_wakeups_2_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_rxq_idx <= io_wakeups_2_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_pdst <= io_wakeups_2_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_prs1 <= io_wakeups_2_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_prs2 <= io_wakeups_2_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_prs3 <= io_wakeups_2_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_ppred <= io_wakeups_2_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_prs1_busy <= io_wakeups_2_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_prs2_busy <= io_wakeups_2_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_prs3_busy <= io_wakeups_2_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_ppred_busy <= io_wakeups_2_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_stale_pdst <= io_wakeups_2_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_exception <= io_wakeups_2_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_exc_cause <= io_wakeups_2_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_mem_cmd <= io_wakeups_2_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_mem_size <= io_wakeups_2_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_mem_signed <= io_wakeups_2_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_uses_ldq <= io_wakeups_2_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_uses_stq <= io_wakeups_2_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_is_unique <= io_wakeups_2_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_flush_on_commit <= io_wakeups_2_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_csr_cmd <= io_wakeups_2_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_ldst_is_rs1 <= io_wakeups_2_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_ldst <= io_wakeups_2_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_lrs1 <= io_wakeups_2_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_lrs2 <= io_wakeups_2_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_lrs3 <= io_wakeups_2_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_dst_rtype <= io_wakeups_2_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_lrs1_rtype <= io_wakeups_2_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_lrs2_rtype <= io_wakeups_2_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_frs3_en <= io_wakeups_2_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fcn_dw <= io_wakeups_2_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fcn_op <= io_wakeups_2_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_val <= io_wakeups_2_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_rm <= io_wakeups_2_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_fp_typ <= io_wakeups_2_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_xcpt_pf_if <= io_wakeups_2_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_xcpt_ae_if <= io_wakeups_2_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_xcpt_ma_if <= io_wakeups_2_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_bp_debug_if <= io_wakeups_2_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_bp_xcpt_if <= io_wakeups_2_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_debug_fsrc <= io_wakeups_2_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_2_uop_debug_tsrc <= io_wakeups_2_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_valid_REG_6 <= io_wakeups_3_valid_0; // @[rename-busytable.scala:27:7, :48:24]
wakeups_wu_bits_REG_3_uop_inst <= io_wakeups_3_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_debug_inst <= io_wakeups_3_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_rvc <= io_wakeups_3_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_debug_pc <= io_wakeups_3_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iq_type_0 <= io_wakeups_3_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iq_type_1 <= io_wakeups_3_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iq_type_2 <= io_wakeups_3_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iq_type_3 <= io_wakeups_3_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_0 <= io_wakeups_3_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_1 <= io_wakeups_3_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_2 <= io_wakeups_3_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_3 <= io_wakeups_3_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_4 <= io_wakeups_3_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_5 <= io_wakeups_3_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_6 <= io_wakeups_3_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_7 <= io_wakeups_3_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_8 <= io_wakeups_3_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fu_code_9 <= io_wakeups_3_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iw_issued <= io_wakeups_3_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen <= 1'h0; // @[rename-busytable.scala:49:24]
wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen <= 1'h0; // @[rename-busytable.scala:49:24]
wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child <= io_wakeups_3_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child <= io_wakeups_3_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint <= io_wakeups_3_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint <= io_wakeups_3_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint <= io_wakeups_3_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_dis_col_sel <= io_wakeups_3_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_br_mask <= io_wakeups_3_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_br_tag <= io_wakeups_3_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_br_type <= io_wakeups_3_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_sfb <= io_wakeups_3_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_fence <= io_wakeups_3_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_fencei <= io_wakeups_3_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_sfence <= io_wakeups_3_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_amo <= io_wakeups_3_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_eret <= io_wakeups_3_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_sys_pc2epc <= io_wakeups_3_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_rocc <= io_wakeups_3_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_mov <= io_wakeups_3_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_ftq_idx <= io_wakeups_3_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_edge_inst <= io_wakeups_3_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_pc_lob <= io_wakeups_3_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_taken <= io_wakeups_3_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_imm_rename <= io_wakeups_3_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_imm_sel <= io_wakeups_3_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_pimm <= io_wakeups_3_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_imm_packed <= io_wakeups_3_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_op1_sel <= io_wakeups_3_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_op2_sel <= io_wakeups_3_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst <= io_wakeups_3_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_wen <= io_wakeups_3_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1 <= io_wakeups_3_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2 <= io_wakeups_3_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3 <= io_wakeups_3_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12 <= io_wakeups_3_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23 <= io_wakeups_3_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn <= io_wakeups_3_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut <= io_wakeups_3_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint <= io_wakeups_3_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_toint <= io_wakeups_3_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe <= io_wakeups_3_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_fma <= io_wakeups_3_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_div <= io_wakeups_3_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt <= io_wakeups_3_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags <= io_wakeups_3_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_ctrl_vec <= io_wakeups_3_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_rob_idx <= io_wakeups_3_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_ldq_idx <= io_wakeups_3_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_stq_idx <= io_wakeups_3_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_rxq_idx <= io_wakeups_3_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_pdst <= io_wakeups_3_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_prs1 <= io_wakeups_3_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_prs2 <= io_wakeups_3_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_prs3 <= io_wakeups_3_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_ppred <= io_wakeups_3_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_prs1_busy <= io_wakeups_3_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_prs2_busy <= io_wakeups_3_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_prs3_busy <= io_wakeups_3_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_ppred_busy <= io_wakeups_3_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_stale_pdst <= io_wakeups_3_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_exception <= io_wakeups_3_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_exc_cause <= io_wakeups_3_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_mem_cmd <= io_wakeups_3_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_mem_size <= io_wakeups_3_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_mem_signed <= io_wakeups_3_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_uses_ldq <= io_wakeups_3_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_uses_stq <= io_wakeups_3_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_is_unique <= io_wakeups_3_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_flush_on_commit <= io_wakeups_3_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_csr_cmd <= io_wakeups_3_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_ldst_is_rs1 <= io_wakeups_3_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_ldst <= io_wakeups_3_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_lrs1 <= io_wakeups_3_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_lrs2 <= io_wakeups_3_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_lrs3 <= io_wakeups_3_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_dst_rtype <= io_wakeups_3_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_lrs1_rtype <= io_wakeups_3_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_lrs2_rtype <= io_wakeups_3_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_frs3_en <= io_wakeups_3_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fcn_dw <= io_wakeups_3_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fcn_op <= io_wakeups_3_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_val <= io_wakeups_3_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_rm <= io_wakeups_3_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_fp_typ <= io_wakeups_3_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_xcpt_pf_if <= io_wakeups_3_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_xcpt_ae_if <= io_wakeups_3_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_xcpt_ma_if <= io_wakeups_3_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_bp_debug_if <= io_wakeups_3_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_bp_xcpt_if <= io_wakeups_3_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_debug_fsrc <= io_wakeups_3_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_3_uop_debug_tsrc <= io_wakeups_3_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_valid_REG_8 <= io_wakeups_4_valid_0; // @[rename-busytable.scala:27:7, :48:24]
wakeups_wu_bits_REG_4_uop_inst <= io_wakeups_4_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_debug_inst <= io_wakeups_4_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_rvc <= io_wakeups_4_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_debug_pc <= io_wakeups_4_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iq_type_0 <= io_wakeups_4_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iq_type_1 <= io_wakeups_4_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iq_type_2 <= io_wakeups_4_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iq_type_3 <= io_wakeups_4_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_0 <= io_wakeups_4_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_1 <= io_wakeups_4_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_2 <= io_wakeups_4_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_3 <= io_wakeups_4_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_4 <= io_wakeups_4_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_5 <= io_wakeups_4_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_6 <= io_wakeups_4_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_7 <= io_wakeups_4_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_8 <= io_wakeups_4_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fu_code_9 <= io_wakeups_4_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iw_issued <= io_wakeups_4_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iw_issued_partial_agen <= 1'h0; // @[rename-busytable.scala:49:24]
wakeups_wu_bits_REG_4_uop_iw_issued_partial_dgen <= 1'h0; // @[rename-busytable.scala:49:24]
wakeups_wu_bits_REG_4_uop_iw_p1_speculative_child <= io_wakeups_4_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iw_p2_speculative_child <= io_wakeups_4_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iw_p1_bypass_hint <= io_wakeups_4_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iw_p2_bypass_hint <= io_wakeups_4_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_iw_p3_bypass_hint <= io_wakeups_4_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_dis_col_sel <= io_wakeups_4_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_br_mask <= io_wakeups_4_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_br_tag <= io_wakeups_4_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_br_type <= io_wakeups_4_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_sfb <= io_wakeups_4_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_fence <= io_wakeups_4_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_fencei <= io_wakeups_4_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_sfence <= io_wakeups_4_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_amo <= io_wakeups_4_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_eret <= io_wakeups_4_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_sys_pc2epc <= io_wakeups_4_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_rocc <= io_wakeups_4_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_mov <= io_wakeups_4_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_ftq_idx <= io_wakeups_4_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_edge_inst <= io_wakeups_4_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_pc_lob <= io_wakeups_4_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_taken <= io_wakeups_4_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_imm_rename <= io_wakeups_4_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_imm_sel <= io_wakeups_4_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_pimm <= io_wakeups_4_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_imm_packed <= io_wakeups_4_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_op1_sel <= io_wakeups_4_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_op2_sel <= io_wakeups_4_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_ldst <= io_wakeups_4_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_wen <= io_wakeups_4_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_ren1 <= io_wakeups_4_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_ren2 <= io_wakeups_4_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_ren3 <= io_wakeups_4_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_swap12 <= io_wakeups_4_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_swap23 <= io_wakeups_4_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_typeTagIn <= io_wakeups_4_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_typeTagOut <= io_wakeups_4_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_fromint <= io_wakeups_4_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_toint <= io_wakeups_4_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_fastpipe <= io_wakeups_4_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_fma <= io_wakeups_4_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_div <= io_wakeups_4_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_sqrt <= io_wakeups_4_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_wflags <= io_wakeups_4_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_ctrl_vec <= io_wakeups_4_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_rob_idx <= io_wakeups_4_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_ldq_idx <= io_wakeups_4_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_stq_idx <= io_wakeups_4_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_rxq_idx <= io_wakeups_4_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_pdst <= io_wakeups_4_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_prs1 <= io_wakeups_4_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_prs2 <= io_wakeups_4_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_prs3 <= io_wakeups_4_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_ppred <= io_wakeups_4_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_prs1_busy <= io_wakeups_4_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_prs2_busy <= io_wakeups_4_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_prs3_busy <= io_wakeups_4_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_ppred_busy <= io_wakeups_4_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_stale_pdst <= io_wakeups_4_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_exception <= io_wakeups_4_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_exc_cause <= io_wakeups_4_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_mem_cmd <= io_wakeups_4_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_mem_size <= io_wakeups_4_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_mem_signed <= io_wakeups_4_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_uses_ldq <= io_wakeups_4_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_uses_stq <= io_wakeups_4_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_is_unique <= io_wakeups_4_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_flush_on_commit <= io_wakeups_4_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_csr_cmd <= io_wakeups_4_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_ldst_is_rs1 <= io_wakeups_4_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_ldst <= io_wakeups_4_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_lrs1 <= io_wakeups_4_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_lrs2 <= io_wakeups_4_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_lrs3 <= io_wakeups_4_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_dst_rtype <= io_wakeups_4_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_lrs1_rtype <= io_wakeups_4_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_lrs2_rtype <= io_wakeups_4_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_frs3_en <= io_wakeups_4_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fcn_dw <= io_wakeups_4_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fcn_op <= io_wakeups_4_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_val <= io_wakeups_4_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_rm <= io_wakeups_4_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_fp_typ <= io_wakeups_4_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_xcpt_pf_if <= io_wakeups_4_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_xcpt_ae_if <= io_wakeups_4_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_xcpt_ma_if <= io_wakeups_4_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_bp_debug_if <= io_wakeups_4_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_bp_xcpt_if <= io_wakeups_4_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_debug_fsrc <= io_wakeups_4_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24]
wakeups_wu_bits_REG_4_uop_debug_tsrc <= io_wakeups_4_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24]
if (reset) // @[rename-busytable.scala:27:7]
busy_table <= 100'h0; // @[rename-busytable.scala:53:27]
else // @[rename-busytable.scala:27:7]
busy_table <= busy_table_next[99:0]; // @[rename-busytable.scala:53:27, :62:5, :66:14]
always @(posedge)
assign io_busy_resps_0_prs1_busy = io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7]
assign io_busy_resps_0_prs2_busy = io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7]
assign io_busy_resps_1_prs1_busy = io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7]
assign io_busy_resps_1_prs2_busy = io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7]
assign io_busy_resps_2_prs1_busy = io_busy_resps_2_prs1_busy_0; // @[rename-busytable.scala:27:7]
assign io_busy_resps_2_prs2_busy = io_busy_resps_2_prs2_busy_0; // @[rename-busytable.scala:27:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_21 = and(_T_19, _T_20)
node _T_22 = or(UInt<1>(0h0), _T_21)
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = and(_T_22, _T_27)
node _T_29 = or(UInt<1>(0h0), _T_28)
node _T_30 = and(_T_18, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_30, UInt<1>(0h1), "") : assert_2
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = or(UInt<1>(0h0), _T_36)
node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = and(_T_37, _T_42)
node _T_44 = or(UInt<1>(0h0), _T_43)
node _T_45 = and(UInt<1>(0h0), _T_44)
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_T_45, UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_45, UInt<1>(0h1), "") : assert_3
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_52, UInt<1>(0h1), "") : assert_5
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(is_aligned, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_60 = asUInt(reset)
node _T_61 = eq(_T_60, UInt<1>(0h0))
when _T_61 :
node _T_62 = eq(_T_59, UInt<1>(0h0))
when _T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_59, UInt<1>(0h1), "") : assert_7
node _T_63 = not(io.in.a.bits.mask)
node _T_64 = eq(_T_63, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_64, UInt<1>(0h1), "") : assert_8
node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_68, UInt<1>(0h1), "") : assert_9
node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_72 :
node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_74 = and(UInt<1>(0h0), _T_73)
node _T_75 = or(UInt<1>(0h0), _T_74)
node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_78 = and(_T_76, _T_77)
node _T_79 = or(UInt<1>(0h0), _T_78)
node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = and(_T_79, _T_84)
node _T_86 = or(UInt<1>(0h0), _T_85)
node _T_87 = and(_T_75, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_87, UInt<1>(0h1), "") : assert_10
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_102, UInt<1>(0h1), "") : assert_11
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_109, UInt<1>(0h1), "") : assert_13
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_116, UInt<1>(0h1), "") : assert_15
node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_120, UInt<1>(0h1), "") : assert_16
node _T_124 = not(io.in.a.bits.mask)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_125, UInt<1>(0h1), "") : assert_17
node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_130 = asUInt(reset)
node _T_131 = eq(_T_130, UInt<1>(0h0))
when _T_131 :
node _T_132 = eq(_T_129, UInt<1>(0h0))
when _T_132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_129, UInt<1>(0h1), "") : assert_18
node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_133 :
node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = or(UInt<1>(0h0), _T_136)
node _T_138 = asUInt(reset)
node _T_139 = eq(_T_138, UInt<1>(0h0))
when _T_139 :
node _T_140 = eq(_T_137, UInt<1>(0h0))
when _T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_137, UInt<1>(0h1), "") : assert_19
node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_143 = and(_T_141, _T_142)
node _T_144 = or(UInt<1>(0h0), _T_143)
node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = and(_T_144, _T_149)
node _T_151 = or(UInt<1>(0h0), _T_150)
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_151, UInt<1>(0h1), "") : assert_20
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_158 = asUInt(reset)
node _T_159 = eq(_T_158, UInt<1>(0h0))
when _T_159 :
node _T_160 = eq(is_aligned, UInt<1>(0h0))
when _T_160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_162 = asUInt(reset)
node _T_163 = eq(_T_162, UInt<1>(0h0))
when _T_163 :
node _T_164 = eq(_T_161, UInt<1>(0h0))
when _T_164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_161, UInt<1>(0h1), "") : assert_23
node _T_165 = eq(io.in.a.bits.mask, mask)
node _T_166 = asUInt(reset)
node _T_167 = eq(_T_166, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(_T_165, UInt<1>(0h0))
when _T_168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_165, UInt<1>(0h1), "") : assert_24
node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_169, UInt<1>(0h1), "") : assert_25
node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_176 = and(_T_174, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_180 = and(_T_178, _T_179)
node _T_181 = or(UInt<1>(0h0), _T_180)
node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = and(_T_181, _T_186)
node _T_188 = or(UInt<1>(0h0), _T_187)
node _T_189 = and(_T_177, _T_188)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_189, UInt<1>(0h1), "") : assert_26
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(is_aligned, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_200 = asUInt(reset)
node _T_201 = eq(_T_200, UInt<1>(0h0))
when _T_201 :
node _T_202 = eq(_T_199, UInt<1>(0h0))
when _T_202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_199, UInt<1>(0h1), "") : assert_29
node _T_203 = eq(io.in.a.bits.mask, mask)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_203, UInt<1>(0h1), "") : assert_30
node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_207 :
node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_209 = and(UInt<1>(0h0), _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_213 = and(_T_211, _T_212)
node _T_214 = or(UInt<1>(0h0), _T_213)
node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = and(_T_214, _T_219)
node _T_221 = or(UInt<1>(0h0), _T_220)
node _T_222 = and(_T_210, _T_221)
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_T_222, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_222, UInt<1>(0h1), "") : assert_31
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(is_aligned, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_232, UInt<1>(0h1), "") : assert_34
node _T_236 = not(mask)
node _T_237 = and(io.in.a.bits.mask, _T_236)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(_T_238, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_238, UInt<1>(0h1), "") : assert_35
node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_242 :
node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_244 = and(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), _T_244)
node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_248 = cvt(_T_247)
node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_250 = asSInt(_T_249)
node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0)))
node _T_252 = and(_T_246, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_245, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_254, UInt<1>(0h1), "") : assert_36
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_264, UInt<1>(0h1), "") : assert_39
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_268, UInt<1>(0h1), "") : assert_40
node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_272 :
node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_274 = and(UInt<1>(0h0), _T_273)
node _T_275 = or(UInt<1>(0h0), _T_274)
node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = and(_T_276, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = and(_T_275, _T_283)
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_284, UInt<1>(0h1), "") : assert_41
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(is_aligned, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_294, UInt<1>(0h1), "") : assert_44
node _T_298 = eq(io.in.a.bits.mask, mask)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_298, UInt<1>(0h1), "") : assert_45
node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_302 :
node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_304 = and(UInt<1>(0h0), _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_308 = and(_T_306, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = and(_T_309, _T_314)
node _T_316 = or(UInt<1>(0h0), _T_315)
node _T_317 = and(_T_305, _T_316)
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_317, UInt<1>(0h1), "") : assert_46
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(is_aligned, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_327, UInt<1>(0h1), "") : assert_49
node _T_331 = eq(io.in.a.bits.mask, mask)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_331, UInt<1>(0h1), "") : assert_50
node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_336 = asUInt(reset)
node _T_337 = eq(_T_336, UInt<1>(0h0))
when _T_337 :
node _T_338 = eq(_T_335, UInt<1>(0h0))
when _T_338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_335, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_339, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1))
node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_343 :
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_347, UInt<1>(0h1), "") : assert_54
node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_351, UInt<1>(0h1), "") : assert_55
node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_355, UInt<1>(0h1), "") : assert_56
node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_359, UInt<1>(0h1), "") : assert_57
node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_363 :
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(sink_ok, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_370, UInt<1>(0h1), "") : assert_60
node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_374, UInt<1>(0h1), "") : assert_61
node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_378, UInt<1>(0h1), "") : assert_62
node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_382, UInt<1>(0h1), "") : assert_63
node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_387 = or(UInt<1>(0h1), _T_386)
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_387, UInt<1>(0h1), "") : assert_64
node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_391 :
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(sink_ok, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_398, UInt<1>(0h1), "") : assert_67
node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_402, UInt<1>(0h1), "") : assert_68
node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_406, UInt<1>(0h1), "") : assert_69
node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_411 = or(_T_410, io.in.d.bits.corrupt)
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_411, UInt<1>(0h1), "") : assert_70
node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_416 = or(UInt<1>(0h1), _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_416, UInt<1>(0h1), "") : assert_71
node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_420 :
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_424, UInt<1>(0h1), "") : assert_73
node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_428, UInt<1>(0h1), "") : assert_74
node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_433 = or(UInt<1>(0h1), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_433, UInt<1>(0h1), "") : assert_75
node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_437 :
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_441, UInt<1>(0h1), "") : assert_77
node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_446 = or(_T_445, io.in.d.bits.corrupt)
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_446, UInt<1>(0h1), "") : assert_78
node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_451 = or(UInt<1>(0h1), _T_450)
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(_T_451, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_451, UInt<1>(0h1), "") : assert_79
node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_455 :
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_459, UInt<1>(0h1), "") : assert_81
node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_463, UInt<1>(0h1), "") : assert_82
node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_468 = or(UInt<1>(0h1), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_468, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<128>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_472, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<128>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_476, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_480, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_484 = eq(a_first, UInt<1>(0h0))
node _T_485 = and(io.in.a.valid, _T_484)
when _T_485 :
node _T_486 = eq(io.in.a.bits.opcode, opcode)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_486, UInt<1>(0h1), "") : assert_87
node _T_490 = eq(io.in.a.bits.param, param)
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(_T_490, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_490, UInt<1>(0h1), "") : assert_88
node _T_494 = eq(io.in.a.bits.size, size)
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_494, UInt<1>(0h1), "") : assert_89
node _T_498 = eq(io.in.a.bits.source, source)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_498, UInt<1>(0h1), "") : assert_90
node _T_502 = eq(io.in.a.bits.address, address)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_502, UInt<1>(0h1), "") : assert_91
node _T_506 = and(io.in.a.ready, io.in.a.valid)
node _T_507 = and(_T_506, a_first)
when _T_507 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_508 = eq(d_first, UInt<1>(0h0))
node _T_509 = and(io.in.d.valid, _T_508)
when _T_509 :
node _T_510 = eq(io.in.d.bits.opcode, opcode_1)
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_510, UInt<1>(0h1), "") : assert_92
node _T_514 = eq(io.in.d.bits.param, param_1)
node _T_515 = asUInt(reset)
node _T_516 = eq(_T_515, UInt<1>(0h0))
when _T_516 :
node _T_517 = eq(_T_514, UInt<1>(0h0))
when _T_517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_514, UInt<1>(0h1), "") : assert_93
node _T_518 = eq(io.in.d.bits.size, size_1)
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(_T_518, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_518, UInt<1>(0h1), "") : assert_94
node _T_522 = eq(io.in.d.bits.source, source_1)
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_522, UInt<1>(0h1), "") : assert_95
node _T_526 = eq(io.in.d.bits.sink, sink)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_526, UInt<1>(0h1), "") : assert_96
node _T_530 = eq(io.in.d.bits.denied, denied)
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_530, UInt<1>(0h1), "") : assert_97
node _T_534 = and(io.in.d.ready, io.in.d.valid)
node _T_535 = and(_T_534, d_first)
when _T_535 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_536 = and(io.in.a.valid, a_first_1)
node _T_537 = and(_T_536, UInt<1>(0h1))
when _T_537 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_538 = and(io.in.a.ready, io.in.a.valid)
node _T_539 = and(_T_538, a_first_1)
node _T_540 = and(_T_539, UInt<1>(0h1))
when _T_540 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_541 = dshr(inflight, io.in.a.bits.source)
node _T_542 = bits(_T_541, 0, 0)
node _T_543 = eq(_T_542, UInt<1>(0h0))
node _T_544 = asUInt(reset)
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(_T_543, UInt<1>(0h0))
when _T_546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_543, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_551 = and(io.in.d.ready, io.in.d.valid)
node _T_552 = and(_T_551, d_first_1)
node _T_553 = and(_T_552, UInt<1>(0h1))
node _T_554 = eq(d_release_ack, UInt<1>(0h0))
node _T_555 = and(_T_553, _T_554)
when _T_555 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_556 = and(io.in.d.valid, d_first_1)
node _T_557 = and(_T_556, UInt<1>(0h1))
node _T_558 = eq(d_release_ack, UInt<1>(0h0))
node _T_559 = and(_T_557, _T_558)
when _T_559 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_560 = dshr(inflight, io.in.d.bits.source)
node _T_561 = bits(_T_560, 0, 0)
node _T_562 = or(_T_561, same_cycle_resp)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_562, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_568 = or(_T_566, _T_567)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_568, UInt<1>(0h1), "") : assert_100
node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_572, UInt<1>(0h1), "") : assert_101
else :
node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_578 = or(_T_576, _T_577)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_578, UInt<1>(0h1), "") : assert_102
node _T_582 = eq(io.in.d.bits.size, a_size_lookup)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_582, UInt<1>(0h1), "") : assert_103
node _T_586 = and(io.in.d.valid, d_first_1)
node _T_587 = and(_T_586, a_first_1)
node _T_588 = and(_T_587, io.in.a.valid)
node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_590 = and(_T_588, _T_589)
node _T_591 = eq(d_release_ack, UInt<1>(0h0))
node _T_592 = and(_T_590, _T_591)
when _T_592 :
node _T_593 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_594 = or(_T_593, io.in.a.ready)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_594, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_122
node _T_598 = orr(inflight)
node _T_599 = eq(_T_598, UInt<1>(0h0))
node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_601 = or(_T_599, _T_600)
node _T_602 = lt(watchdog, plusarg_reader.out)
node _T_603 = or(_T_601, _T_602)
node _T_604 = asUInt(reset)
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(_T_603, UInt<1>(0h0))
when _T_606 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_603, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_607 = and(io.in.a.ready, io.in.a.valid)
node _T_608 = and(io.in.d.ready, io.in.d.valid)
node _T_609 = or(_T_607, _T_608)
when _T_609 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<128>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<128>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_610 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<128>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_613 = and(_T_611, _T_612)
node _T_614 = and(_T_610, _T_613)
when _T_614 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<128>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_616 = and(_T_615, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<128>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_619 = and(_T_617, _T_618)
node _T_620 = and(_T_616, _T_619)
when _T_620 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<128>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_621 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_622 = bits(_T_621, 0, 0)
node _T_623 = eq(_T_622, UInt<1>(0h0))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_623, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_627 = and(io.in.d.valid, d_first_2)
node _T_628 = and(_T_627, UInt<1>(0h1))
node _T_629 = and(_T_628, d_release_ack_1)
when _T_629 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_630 = and(io.in.d.ready, io.in.d.valid)
node _T_631 = and(_T_630, d_first_2)
node _T_632 = and(_T_631, UInt<1>(0h1))
node _T_633 = and(_T_632, d_release_ack_1)
when _T_633 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_634 = and(io.in.d.valid, d_first_2)
node _T_635 = and(_T_634, UInt<1>(0h1))
node _T_636 = and(_T_635, d_release_ack_1)
when _T_636 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_637 = dshr(inflight_1, io.in.d.bits.source)
node _T_638 = bits(_T_637, 0, 0)
node _T_639 = or(_T_638, same_cycle_resp_1)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_639, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<128>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(_T_643, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_643, UInt<1>(0h1), "") : assert_108
else :
node _T_647 = eq(io.in.d.bits.size, c_size_lookup)
node _T_648 = asUInt(reset)
node _T_649 = eq(_T_648, UInt<1>(0h0))
when _T_649 :
node _T_650 = eq(_T_647, UInt<1>(0h0))
when _T_650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_647, UInt<1>(0h1), "") : assert_109
node _T_651 = and(io.in.d.valid, d_first_2)
node _T_652 = and(_T_651, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<128>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_653 = and(_T_652, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<128>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_655 = and(_T_653, _T_654)
node _T_656 = and(_T_655, d_release_ack_1)
node _T_657 = eq(c_probe_ack, UInt<1>(0h0))
node _T_658 = and(_T_656, _T_657)
when _T_658 :
node _T_659 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<128>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_660 = or(_T_659, _WIRE_23.ready)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_660, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_123
node _T_664 = orr(inflight_1)
node _T_665 = eq(_T_664, UInt<1>(0h0))
node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_667 = or(_T_665, _T_666)
node _T_668 = lt(watchdog_1, plusarg_reader_1.out)
node _T_669 = or(_T_667, _T_668)
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_669, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_674 = and(io.in.d.ready, io.in.d.valid)
node _T_675 = or(_T_673, _T_674)
when _T_675 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_60( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_607; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [127:0] address; // @[Monitor.scala:391:22]
wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module FPUFMAPipe_l3_f16_4 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}
reg valid : UInt<1>, clock
connect valid, io.in.valid
reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
when io.in.valid :
node one = shl(UInt<1>(0h1), 15)
node _zero_T = xor(io.in.bits.in1, io.in.bits.in2)
node _zero_T_1 = shl(UInt<1>(0h1), 16)
node zero = and(_zero_T, _zero_T_1)
connect in, io.in.bits
when io.in.bits.swap23 :
connect in.in2, one
node _T = or(io.in.bits.ren3, io.in.bits.swap23)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
connect in.in3, zero
inst fma of MulAddRecFNPipe_l2_e5_s11_4
connect fma.clock, clock
connect fma.reset, reset
connect fma.io.validin, valid
connect fma.io.op, in.fmaCmd
connect fma.io.roundingMode, in.rm
connect fma.io.detectTininess, UInt<1>(0h1)
connect fma.io.a, in.in1
connect fma.io.b, in.in2
connect fma.io.c, in.in3
wire res : { data : UInt<65>, exc : UInt<5>}
connect res.data, fma.io.out
connect res.exc, fma.io.exceptionFlags
wire io_out_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}
connect io_out_out.valid, fma.io.validout
connect io_out_out.bits, res
connect io.out, io_out_out | module FPUFMAPipe_l3_f16_4( // @[FPU.scala:697:7]
input clock, // @[FPU.scala:697:7]
input reset, // @[FPU.scala:697:7]
input io_in_valid, // @[FPU.scala:702:14]
input io_in_bits_ldst, // @[FPU.scala:702:14]
input io_in_bits_wen, // @[FPU.scala:702:14]
input io_in_bits_ren1, // @[FPU.scala:702:14]
input io_in_bits_ren2, // @[FPU.scala:702:14]
input io_in_bits_ren3, // @[FPU.scala:702:14]
input io_in_bits_swap12, // @[FPU.scala:702:14]
input io_in_bits_swap23, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14]
input io_in_bits_fromint, // @[FPU.scala:702:14]
input io_in_bits_toint, // @[FPU.scala:702:14]
input io_in_bits_fastpipe, // @[FPU.scala:702:14]
input io_in_bits_fma, // @[FPU.scala:702:14]
input io_in_bits_div, // @[FPU.scala:702:14]
input io_in_bits_sqrt, // @[FPU.scala:702:14]
input io_in_bits_wflags, // @[FPU.scala:702:14]
input io_in_bits_vec, // @[FPU.scala:702:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:702:14]
input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:702:14]
input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in1, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in2, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in3, // @[FPU.scala:702:14]
output [64:0] io_out_bits_data, // @[FPU.scala:702:14]
output [4:0] io_out_bits_exc // @[FPU.scala:702:14]
);
wire [64:0] res_data; // @[FPU.scala:728:17]
wire [16:0] _fma_io_out; // @[FPU.scala:719:19]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7]
wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7]
wire [15:0] one = 16'h8000; // @[FPU.scala:710:19]
wire [16:0] _zero_T_1 = 17'h10000; // @[FPU.scala:711:57]
wire io_out_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21]
wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7]
wire io_out_valid; // @[FPU.scala:697:7]
reg valid; // @[FPU.scala:707:22]
reg in_ldst; // @[FPU.scala:708:15]
reg in_wen; // @[FPU.scala:708:15]
reg in_ren1; // @[FPU.scala:708:15]
reg in_ren2; // @[FPU.scala:708:15]
reg in_ren3; // @[FPU.scala:708:15]
reg in_swap12; // @[FPU.scala:708:15]
reg in_swap23; // @[FPU.scala:708:15]
reg [1:0] in_typeTagIn; // @[FPU.scala:708:15]
reg [1:0] in_typeTagOut; // @[FPU.scala:708:15]
reg in_fromint; // @[FPU.scala:708:15]
reg in_toint; // @[FPU.scala:708:15]
reg in_fastpipe; // @[FPU.scala:708:15]
reg in_fma; // @[FPU.scala:708:15]
reg in_div; // @[FPU.scala:708:15]
reg in_sqrt; // @[FPU.scala:708:15]
reg in_wflags; // @[FPU.scala:708:15]
reg in_vec; // @[FPU.scala:708:15]
reg [2:0] in_rm; // @[FPU.scala:708:15]
reg [1:0] in_fmaCmd; // @[FPU.scala:708:15]
reg [1:0] in_typ; // @[FPU.scala:708:15]
reg [1:0] in_fmt; // @[FPU.scala:708:15]
reg [64:0] in_in1; // @[FPU.scala:708:15]
reg [64:0] in_in2; // @[FPU.scala:708:15]
reg [64:0] in_in3; // @[FPU.scala:708:15]
wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32]
wire [64:0] zero = {48'h0, _zero_T[16], 16'h0}; // @[FPU.scala:711:{32,50}]
assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21]
wire [4:0] res_exc; // @[FPU.scala:728:17]
assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21]
assign res_data = {48'h0, _fma_io_out}; // @[FPU.scala:711:50, :719:19, :728:17, :729:12]
assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:697:7]
valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22]
if (io_in_valid_0) begin // @[FPU.scala:697:7]
in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15]
in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15]
in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15]
in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15]
in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15]
in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15]
in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15]
in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15]
in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15]
in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15]
in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15]
in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15]
in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15]
in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15]
in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15]
in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15]
in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15]
in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15]
in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15]
in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15]
in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15]
in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15]
in_in2 <= io_in_bits_swap23_0 ? 65'h8000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}]
in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}]
end
always @(posedge)
MulAddRecFNPipe_l2_e5_s11_4 fma ( // @[FPU.scala:719:19]
.clock (clock),
.reset (reset),
.io_validin (valid), // @[FPU.scala:707:22]
.io_op (in_fmaCmd), // @[FPU.scala:708:15]
.io_a (in_in1[16:0]), // @[FPU.scala:708:15, :724:12]
.io_b (in_in2[16:0]), // @[FPU.scala:708:15, :725:12]
.io_c (in_in3[16:0]), // @[FPU.scala:708:15, :726:12]
.io_roundingMode (in_rm), // @[FPU.scala:708:15]
.io_out (_fma_io_out),
.io_exceptionFlags (res_exc),
.io_validout (io_out_out_valid)
); // @[FPU.scala:719:19]
assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BankedStore :
input clock : Clock
input reset : Reset
output io : { flip sinkC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sinkC_dat : { data : UInt<64>}, flip sinkD_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sinkD_dat : { data : UInt<64>}, flip sourceC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, sourceC_dat : { data : UInt<64>}, flip sourceD_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, sourceD_rdat : { data : UInt<64>}, flip sourceD_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sourceD_wdat : { data : UInt<64>}}
smem cc_banks_0 : UInt<64> [16384]
smem cc_banks_1 : UInt<64> [16384]
smem cc_banks_2 : UInt<64> [16384]
smem cc_banks_3 : UInt<64> [16384]
node sinkC_req_words_0 = bits(io.sinkC_dat.data, 63, 0)
node sinkC_req_a_hi = cat(io.sinkC_adr.bits.way, io.sinkC_adr.bits.set)
node sinkC_req_a = cat(sinkC_req_a_hi, io.sinkC_adr.bits.beat)
wire sinkC_req : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]}
node _sinkC_req_select_T = bits(sinkC_req_a, 1, 0)
node sinkC_req_select_shiftAmount = bits(_sinkC_req_select_T, 1, 0)
node _sinkC_req_select_T_1 = dshl(UInt<1>(0h1), sinkC_req_select_shiftAmount)
node sinkC_req_select = bits(_sinkC_req_select_T_1, 3, 0)
node _sinkC_req_ready_T = bits(sinkC_req.bankSum, 0, 0)
node _sinkC_req_ready_T_1 = and(_sinkC_req_ready_T, io.sinkC_adr.bits.mask)
node _sinkC_req_ready_T_2 = orr(_sinkC_req_ready_T_1)
node _sinkC_req_ready_T_3 = eq(_sinkC_req_ready_T_2, UInt<1>(0h0))
node _sinkC_req_ready_T_4 = bits(sinkC_req.bankSum, 1, 1)
node _sinkC_req_ready_T_5 = and(_sinkC_req_ready_T_4, io.sinkC_adr.bits.mask)
node _sinkC_req_ready_T_6 = orr(_sinkC_req_ready_T_5)
node _sinkC_req_ready_T_7 = eq(_sinkC_req_ready_T_6, UInt<1>(0h0))
node _sinkC_req_ready_T_8 = bits(sinkC_req.bankSum, 2, 2)
node _sinkC_req_ready_T_9 = and(_sinkC_req_ready_T_8, io.sinkC_adr.bits.mask)
node _sinkC_req_ready_T_10 = orr(_sinkC_req_ready_T_9)
node _sinkC_req_ready_T_11 = eq(_sinkC_req_ready_T_10, UInt<1>(0h0))
node _sinkC_req_ready_T_12 = bits(sinkC_req.bankSum, 3, 3)
node _sinkC_req_ready_T_13 = and(_sinkC_req_ready_T_12, io.sinkC_adr.bits.mask)
node _sinkC_req_ready_T_14 = orr(_sinkC_req_ready_T_13)
node _sinkC_req_ready_T_15 = eq(_sinkC_req_ready_T_14, UInt<1>(0h0))
node sinkC_req_ready_lo = cat(_sinkC_req_ready_T_7, _sinkC_req_ready_T_3)
node sinkC_req_ready_hi = cat(_sinkC_req_ready_T_15, _sinkC_req_ready_T_11)
node sinkC_req_ready = cat(sinkC_req_ready_hi, sinkC_req_ready_lo)
node _sinkC_req_io_sinkC_adr_ready_T = bits(sinkC_req_a, 1, 0)
node _sinkC_req_io_sinkC_adr_ready_T_1 = dshr(sinkC_req_ready, _sinkC_req_io_sinkC_adr_ready_T)
node _sinkC_req_io_sinkC_adr_ready_T_2 = bits(_sinkC_req_io_sinkC_adr_ready_T_1, 0, 0)
connect io.sinkC_adr.ready, _sinkC_req_io_sinkC_adr_ready_T_2
connect sinkC_req.wen, UInt<1>(0h1)
node _sinkC_req_out_index_T = shr(sinkC_req_a, 2)
connect sinkC_req.index, _sinkC_req_out_index_T
node _sinkC_req_out_bankSel_T = bits(sinkC_req_select, 0, 0)
node _sinkC_req_out_bankSel_T_1 = bits(sinkC_req_select, 1, 1)
node _sinkC_req_out_bankSel_T_2 = bits(sinkC_req_select, 2, 2)
node _sinkC_req_out_bankSel_T_3 = bits(sinkC_req_select, 3, 3)
node sinkC_req_out_bankSel_lo = cat(_sinkC_req_out_bankSel_T_1, _sinkC_req_out_bankSel_T)
node sinkC_req_out_bankSel_hi = cat(_sinkC_req_out_bankSel_T_3, _sinkC_req_out_bankSel_T_2)
node _sinkC_req_out_bankSel_T_4 = cat(sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo)
node _sinkC_req_out_bankSel_T_5 = bits(io.sinkC_adr.bits.mask, 0, 0)
node _sinkC_req_out_bankSel_T_6 = mux(_sinkC_req_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0))
node _sinkC_req_out_bankSel_T_7 = and(_sinkC_req_out_bankSel_T_4, _sinkC_req_out_bankSel_T_6)
node _sinkC_req_out_bankSel_T_8 = mux(io.sinkC_adr.valid, _sinkC_req_out_bankSel_T_7, UInt<1>(0h0))
connect sinkC_req.bankSel, _sinkC_req_out_bankSel_T_8
node _sinkC_req_out_bankEn_T = bits(sinkC_req_ready, 0, 0)
node _sinkC_req_out_bankEn_T_1 = bits(sinkC_req_ready, 1, 1)
node _sinkC_req_out_bankEn_T_2 = bits(sinkC_req_ready, 2, 2)
node _sinkC_req_out_bankEn_T_3 = bits(sinkC_req_ready, 3, 3)
node sinkC_req_out_bankEn_lo = cat(_sinkC_req_out_bankEn_T_1, _sinkC_req_out_bankEn_T)
node sinkC_req_out_bankEn_hi = cat(_sinkC_req_out_bankEn_T_3, _sinkC_req_out_bankEn_T_2)
node _sinkC_req_out_bankEn_T_4 = cat(sinkC_req_out_bankEn_hi, sinkC_req_out_bankEn_lo)
node _sinkC_req_out_bankEn_T_5 = and(sinkC_req.bankSel, _sinkC_req_out_bankEn_T_4)
node _sinkC_req_out_bankEn_T_6 = mux(io.sinkC_adr.bits.noop, UInt<1>(0h0), _sinkC_req_out_bankEn_T_5)
connect sinkC_req.bankEn, _sinkC_req_out_bankEn_T_6
connect sinkC_req.data[0], sinkC_req_words_0
connect sinkC_req.data[1], sinkC_req_words_0
connect sinkC_req.data[2], sinkC_req_words_0
connect sinkC_req.data[3], sinkC_req_words_0
node sinkD_req_words_0 = bits(io.sinkD_dat.data, 63, 0)
node sinkD_req_a_hi = cat(io.sinkD_adr.bits.way, io.sinkD_adr.bits.set)
node sinkD_req_a = cat(sinkD_req_a_hi, io.sinkD_adr.bits.beat)
wire sinkD_req : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]}
node _sinkD_req_select_T = bits(sinkD_req_a, 1, 0)
node sinkD_req_select_shiftAmount = bits(_sinkD_req_select_T, 1, 0)
node _sinkD_req_select_T_1 = dshl(UInt<1>(0h1), sinkD_req_select_shiftAmount)
node sinkD_req_select = bits(_sinkD_req_select_T_1, 3, 0)
node _sinkD_req_ready_T = bits(sinkD_req.bankSum, 0, 0)
node _sinkD_req_ready_T_1 = and(_sinkD_req_ready_T, io.sinkD_adr.bits.mask)
node _sinkD_req_ready_T_2 = orr(_sinkD_req_ready_T_1)
node _sinkD_req_ready_T_3 = eq(_sinkD_req_ready_T_2, UInt<1>(0h0))
node _sinkD_req_ready_T_4 = bits(sinkD_req.bankSum, 1, 1)
node _sinkD_req_ready_T_5 = and(_sinkD_req_ready_T_4, io.sinkD_adr.bits.mask)
node _sinkD_req_ready_T_6 = orr(_sinkD_req_ready_T_5)
node _sinkD_req_ready_T_7 = eq(_sinkD_req_ready_T_6, UInt<1>(0h0))
node _sinkD_req_ready_T_8 = bits(sinkD_req.bankSum, 2, 2)
node _sinkD_req_ready_T_9 = and(_sinkD_req_ready_T_8, io.sinkD_adr.bits.mask)
node _sinkD_req_ready_T_10 = orr(_sinkD_req_ready_T_9)
node _sinkD_req_ready_T_11 = eq(_sinkD_req_ready_T_10, UInt<1>(0h0))
node _sinkD_req_ready_T_12 = bits(sinkD_req.bankSum, 3, 3)
node _sinkD_req_ready_T_13 = and(_sinkD_req_ready_T_12, io.sinkD_adr.bits.mask)
node _sinkD_req_ready_T_14 = orr(_sinkD_req_ready_T_13)
node _sinkD_req_ready_T_15 = eq(_sinkD_req_ready_T_14, UInt<1>(0h0))
node sinkD_req_ready_lo = cat(_sinkD_req_ready_T_7, _sinkD_req_ready_T_3)
node sinkD_req_ready_hi = cat(_sinkD_req_ready_T_15, _sinkD_req_ready_T_11)
node sinkD_req_ready = cat(sinkD_req_ready_hi, sinkD_req_ready_lo)
node _sinkD_req_io_sinkD_adr_ready_T = bits(sinkD_req_a, 1, 0)
node _sinkD_req_io_sinkD_adr_ready_T_1 = dshr(sinkD_req_ready, _sinkD_req_io_sinkD_adr_ready_T)
node _sinkD_req_io_sinkD_adr_ready_T_2 = bits(_sinkD_req_io_sinkD_adr_ready_T_1, 0, 0)
connect io.sinkD_adr.ready, _sinkD_req_io_sinkD_adr_ready_T_2
connect sinkD_req.wen, UInt<1>(0h1)
node _sinkD_req_out_index_T = shr(sinkD_req_a, 2)
connect sinkD_req.index, _sinkD_req_out_index_T
node _sinkD_req_out_bankSel_T = bits(sinkD_req_select, 0, 0)
node _sinkD_req_out_bankSel_T_1 = bits(sinkD_req_select, 1, 1)
node _sinkD_req_out_bankSel_T_2 = bits(sinkD_req_select, 2, 2)
node _sinkD_req_out_bankSel_T_3 = bits(sinkD_req_select, 3, 3)
node sinkD_req_out_bankSel_lo = cat(_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T)
node sinkD_req_out_bankSel_hi = cat(_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2)
node _sinkD_req_out_bankSel_T_4 = cat(sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo)
node _sinkD_req_out_bankSel_T_5 = bits(io.sinkD_adr.bits.mask, 0, 0)
node _sinkD_req_out_bankSel_T_6 = mux(_sinkD_req_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0))
node _sinkD_req_out_bankSel_T_7 = and(_sinkD_req_out_bankSel_T_4, _sinkD_req_out_bankSel_T_6)
node _sinkD_req_out_bankSel_T_8 = mux(io.sinkD_adr.valid, _sinkD_req_out_bankSel_T_7, UInt<1>(0h0))
connect sinkD_req.bankSel, _sinkD_req_out_bankSel_T_8
node _sinkD_req_out_bankEn_T = bits(sinkD_req_ready, 0, 0)
node _sinkD_req_out_bankEn_T_1 = bits(sinkD_req_ready, 1, 1)
node _sinkD_req_out_bankEn_T_2 = bits(sinkD_req_ready, 2, 2)
node _sinkD_req_out_bankEn_T_3 = bits(sinkD_req_ready, 3, 3)
node sinkD_req_out_bankEn_lo = cat(_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T)
node sinkD_req_out_bankEn_hi = cat(_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2)
node _sinkD_req_out_bankEn_T_4 = cat(sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo)
node _sinkD_req_out_bankEn_T_5 = and(sinkD_req.bankSel, _sinkD_req_out_bankEn_T_4)
node _sinkD_req_out_bankEn_T_6 = mux(io.sinkD_adr.bits.noop, UInt<1>(0h0), _sinkD_req_out_bankEn_T_5)
connect sinkD_req.bankEn, _sinkD_req_out_bankEn_T_6
connect sinkD_req.data[0], sinkD_req_words_0
connect sinkD_req.data[1], sinkD_req_words_0
connect sinkD_req.data[2], sinkD_req_words_0
connect sinkD_req.data[3], sinkD_req_words_0
node sourceC_req_a_hi = cat(io.sourceC_adr.bits.way, io.sourceC_adr.bits.set)
node sourceC_req_a = cat(sourceC_req_a_hi, io.sourceC_adr.bits.beat)
wire sourceC_req : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]}
node _sourceC_req_select_T = bits(sourceC_req_a, 1, 0)
node sourceC_req_select_shiftAmount = bits(_sourceC_req_select_T, 1, 0)
node _sourceC_req_select_T_1 = dshl(UInt<1>(0h1), sourceC_req_select_shiftAmount)
node sourceC_req_select = bits(_sourceC_req_select_T_1, 3, 0)
node _sourceC_req_ready_T = bits(sourceC_req.bankSum, 0, 0)
node _sourceC_req_ready_T_1 = and(_sourceC_req_ready_T, io.sourceC_adr.bits.mask)
node _sourceC_req_ready_T_2 = orr(_sourceC_req_ready_T_1)
node _sourceC_req_ready_T_3 = eq(_sourceC_req_ready_T_2, UInt<1>(0h0))
node _sourceC_req_ready_T_4 = bits(sourceC_req.bankSum, 1, 1)
node _sourceC_req_ready_T_5 = and(_sourceC_req_ready_T_4, io.sourceC_adr.bits.mask)
node _sourceC_req_ready_T_6 = orr(_sourceC_req_ready_T_5)
node _sourceC_req_ready_T_7 = eq(_sourceC_req_ready_T_6, UInt<1>(0h0))
node _sourceC_req_ready_T_8 = bits(sourceC_req.bankSum, 2, 2)
node _sourceC_req_ready_T_9 = and(_sourceC_req_ready_T_8, io.sourceC_adr.bits.mask)
node _sourceC_req_ready_T_10 = orr(_sourceC_req_ready_T_9)
node _sourceC_req_ready_T_11 = eq(_sourceC_req_ready_T_10, UInt<1>(0h0))
node _sourceC_req_ready_T_12 = bits(sourceC_req.bankSum, 3, 3)
node _sourceC_req_ready_T_13 = and(_sourceC_req_ready_T_12, io.sourceC_adr.bits.mask)
node _sourceC_req_ready_T_14 = orr(_sourceC_req_ready_T_13)
node _sourceC_req_ready_T_15 = eq(_sourceC_req_ready_T_14, UInt<1>(0h0))
node sourceC_req_ready_lo = cat(_sourceC_req_ready_T_7, _sourceC_req_ready_T_3)
node sourceC_req_ready_hi = cat(_sourceC_req_ready_T_15, _sourceC_req_ready_T_11)
node sourceC_req_ready = cat(sourceC_req_ready_hi, sourceC_req_ready_lo)
node _sourceC_req_io_sourceC_adr_ready_T = bits(sourceC_req_a, 1, 0)
node _sourceC_req_io_sourceC_adr_ready_T_1 = dshr(sourceC_req_ready, _sourceC_req_io_sourceC_adr_ready_T)
node _sourceC_req_io_sourceC_adr_ready_T_2 = bits(_sourceC_req_io_sourceC_adr_ready_T_1, 0, 0)
connect io.sourceC_adr.ready, _sourceC_req_io_sourceC_adr_ready_T_2
connect sourceC_req.wen, UInt<1>(0h0)
node _sourceC_req_out_index_T = shr(sourceC_req_a, 2)
connect sourceC_req.index, _sourceC_req_out_index_T
node _sourceC_req_out_bankSel_T = bits(sourceC_req_select, 0, 0)
node _sourceC_req_out_bankSel_T_1 = bits(sourceC_req_select, 1, 1)
node _sourceC_req_out_bankSel_T_2 = bits(sourceC_req_select, 2, 2)
node _sourceC_req_out_bankSel_T_3 = bits(sourceC_req_select, 3, 3)
node sourceC_req_out_bankSel_lo = cat(_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T)
node sourceC_req_out_bankSel_hi = cat(_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2)
node _sourceC_req_out_bankSel_T_4 = cat(sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo)
node _sourceC_req_out_bankSel_T_5 = bits(io.sourceC_adr.bits.mask, 0, 0)
node _sourceC_req_out_bankSel_T_6 = mux(_sourceC_req_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0))
node _sourceC_req_out_bankSel_T_7 = and(_sourceC_req_out_bankSel_T_4, _sourceC_req_out_bankSel_T_6)
node _sourceC_req_out_bankSel_T_8 = mux(io.sourceC_adr.valid, _sourceC_req_out_bankSel_T_7, UInt<1>(0h0))
connect sourceC_req.bankSel, _sourceC_req_out_bankSel_T_8
node _sourceC_req_out_bankEn_T = bits(sourceC_req_ready, 0, 0)
node _sourceC_req_out_bankEn_T_1 = bits(sourceC_req_ready, 1, 1)
node _sourceC_req_out_bankEn_T_2 = bits(sourceC_req_ready, 2, 2)
node _sourceC_req_out_bankEn_T_3 = bits(sourceC_req_ready, 3, 3)
node sourceC_req_out_bankEn_lo = cat(_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T)
node sourceC_req_out_bankEn_hi = cat(_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2)
node _sourceC_req_out_bankEn_T_4 = cat(sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo)
node _sourceC_req_out_bankEn_T_5 = and(sourceC_req.bankSel, _sourceC_req_out_bankEn_T_4)
node _sourceC_req_out_bankEn_T_6 = mux(io.sourceC_adr.bits.noop, UInt<1>(0h0), _sourceC_req_out_bankEn_T_5)
connect sourceC_req.bankEn, _sourceC_req_out_bankEn_T_6
connect sourceC_req.data[0], UInt<64>(0h0)
connect sourceC_req.data[1], UInt<64>(0h0)
connect sourceC_req.data[2], UInt<64>(0h0)
connect sourceC_req.data[3], UInt<64>(0h0)
node sourceD_rreq_a_hi = cat(io.sourceD_radr.bits.way, io.sourceD_radr.bits.set)
node sourceD_rreq_a = cat(sourceD_rreq_a_hi, io.sourceD_radr.bits.beat)
wire sourceD_rreq : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]}
node _sourceD_rreq_select_T = bits(sourceD_rreq_a, 1, 0)
node sourceD_rreq_select_shiftAmount = bits(_sourceD_rreq_select_T, 1, 0)
node _sourceD_rreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_rreq_select_shiftAmount)
node sourceD_rreq_select = bits(_sourceD_rreq_select_T_1, 3, 0)
node _sourceD_rreq_ready_T = bits(sourceD_rreq.bankSum, 0, 0)
node _sourceD_rreq_ready_T_1 = and(_sourceD_rreq_ready_T, io.sourceD_radr.bits.mask)
node _sourceD_rreq_ready_T_2 = orr(_sourceD_rreq_ready_T_1)
node _sourceD_rreq_ready_T_3 = eq(_sourceD_rreq_ready_T_2, UInt<1>(0h0))
node _sourceD_rreq_ready_T_4 = bits(sourceD_rreq.bankSum, 1, 1)
node _sourceD_rreq_ready_T_5 = and(_sourceD_rreq_ready_T_4, io.sourceD_radr.bits.mask)
node _sourceD_rreq_ready_T_6 = orr(_sourceD_rreq_ready_T_5)
node _sourceD_rreq_ready_T_7 = eq(_sourceD_rreq_ready_T_6, UInt<1>(0h0))
node _sourceD_rreq_ready_T_8 = bits(sourceD_rreq.bankSum, 2, 2)
node _sourceD_rreq_ready_T_9 = and(_sourceD_rreq_ready_T_8, io.sourceD_radr.bits.mask)
node _sourceD_rreq_ready_T_10 = orr(_sourceD_rreq_ready_T_9)
node _sourceD_rreq_ready_T_11 = eq(_sourceD_rreq_ready_T_10, UInt<1>(0h0))
node _sourceD_rreq_ready_T_12 = bits(sourceD_rreq.bankSum, 3, 3)
node _sourceD_rreq_ready_T_13 = and(_sourceD_rreq_ready_T_12, io.sourceD_radr.bits.mask)
node _sourceD_rreq_ready_T_14 = orr(_sourceD_rreq_ready_T_13)
node _sourceD_rreq_ready_T_15 = eq(_sourceD_rreq_ready_T_14, UInt<1>(0h0))
node sourceD_rreq_ready_lo = cat(_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3)
node sourceD_rreq_ready_hi = cat(_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11)
node sourceD_rreq_ready = cat(sourceD_rreq_ready_hi, sourceD_rreq_ready_lo)
node _sourceD_rreq_io_sourceD_radr_ready_T = bits(sourceD_rreq_a, 1, 0)
node _sourceD_rreq_io_sourceD_radr_ready_T_1 = dshr(sourceD_rreq_ready, _sourceD_rreq_io_sourceD_radr_ready_T)
node _sourceD_rreq_io_sourceD_radr_ready_T_2 = bits(_sourceD_rreq_io_sourceD_radr_ready_T_1, 0, 0)
connect io.sourceD_radr.ready, _sourceD_rreq_io_sourceD_radr_ready_T_2
connect sourceD_rreq.wen, UInt<1>(0h0)
node _sourceD_rreq_out_index_T = shr(sourceD_rreq_a, 2)
connect sourceD_rreq.index, _sourceD_rreq_out_index_T
node _sourceD_rreq_out_bankSel_T = bits(sourceD_rreq_select, 0, 0)
node _sourceD_rreq_out_bankSel_T_1 = bits(sourceD_rreq_select, 1, 1)
node _sourceD_rreq_out_bankSel_T_2 = bits(sourceD_rreq_select, 2, 2)
node _sourceD_rreq_out_bankSel_T_3 = bits(sourceD_rreq_select, 3, 3)
node sourceD_rreq_out_bankSel_lo = cat(_sourceD_rreq_out_bankSel_T_1, _sourceD_rreq_out_bankSel_T)
node sourceD_rreq_out_bankSel_hi = cat(_sourceD_rreq_out_bankSel_T_3, _sourceD_rreq_out_bankSel_T_2)
node _sourceD_rreq_out_bankSel_T_4 = cat(sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo)
node _sourceD_rreq_out_bankSel_T_5 = bits(io.sourceD_radr.bits.mask, 0, 0)
node _sourceD_rreq_out_bankSel_T_6 = mux(_sourceD_rreq_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0))
node _sourceD_rreq_out_bankSel_T_7 = and(_sourceD_rreq_out_bankSel_T_4, _sourceD_rreq_out_bankSel_T_6)
node _sourceD_rreq_out_bankSel_T_8 = mux(io.sourceD_radr.valid, _sourceD_rreq_out_bankSel_T_7, UInt<1>(0h0))
connect sourceD_rreq.bankSel, _sourceD_rreq_out_bankSel_T_8
node _sourceD_rreq_out_bankEn_T = bits(sourceD_rreq_ready, 0, 0)
node _sourceD_rreq_out_bankEn_T_1 = bits(sourceD_rreq_ready, 1, 1)
node _sourceD_rreq_out_bankEn_T_2 = bits(sourceD_rreq_ready, 2, 2)
node _sourceD_rreq_out_bankEn_T_3 = bits(sourceD_rreq_ready, 3, 3)
node sourceD_rreq_out_bankEn_lo = cat(_sourceD_rreq_out_bankEn_T_1, _sourceD_rreq_out_bankEn_T)
node sourceD_rreq_out_bankEn_hi = cat(_sourceD_rreq_out_bankEn_T_3, _sourceD_rreq_out_bankEn_T_2)
node _sourceD_rreq_out_bankEn_T_4 = cat(sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo)
node _sourceD_rreq_out_bankEn_T_5 = and(sourceD_rreq.bankSel, _sourceD_rreq_out_bankEn_T_4)
node _sourceD_rreq_out_bankEn_T_6 = mux(io.sourceD_radr.bits.noop, UInt<1>(0h0), _sourceD_rreq_out_bankEn_T_5)
connect sourceD_rreq.bankEn, _sourceD_rreq_out_bankEn_T_6
connect sourceD_rreq.data[0], UInt<64>(0h0)
connect sourceD_rreq.data[1], UInt<64>(0h0)
connect sourceD_rreq.data[2], UInt<64>(0h0)
connect sourceD_rreq.data[3], UInt<64>(0h0)
node sourceD_wreq_words_0 = bits(io.sourceD_wdat.data, 63, 0)
node sourceD_wreq_a_hi = cat(io.sourceD_wadr.bits.way, io.sourceD_wadr.bits.set)
node sourceD_wreq_a = cat(sourceD_wreq_a_hi, io.sourceD_wadr.bits.beat)
wire sourceD_wreq : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]}
node _sourceD_wreq_select_T = bits(sourceD_wreq_a, 1, 0)
node sourceD_wreq_select_shiftAmount = bits(_sourceD_wreq_select_T, 1, 0)
node _sourceD_wreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_wreq_select_shiftAmount)
node sourceD_wreq_select = bits(_sourceD_wreq_select_T_1, 3, 0)
node _sourceD_wreq_ready_T = bits(sourceD_wreq.bankSum, 0, 0)
node _sourceD_wreq_ready_T_1 = and(_sourceD_wreq_ready_T, io.sourceD_wadr.bits.mask)
node _sourceD_wreq_ready_T_2 = orr(_sourceD_wreq_ready_T_1)
node _sourceD_wreq_ready_T_3 = eq(_sourceD_wreq_ready_T_2, UInt<1>(0h0))
node _sourceD_wreq_ready_T_4 = bits(sourceD_wreq.bankSum, 1, 1)
node _sourceD_wreq_ready_T_5 = and(_sourceD_wreq_ready_T_4, io.sourceD_wadr.bits.mask)
node _sourceD_wreq_ready_T_6 = orr(_sourceD_wreq_ready_T_5)
node _sourceD_wreq_ready_T_7 = eq(_sourceD_wreq_ready_T_6, UInt<1>(0h0))
node _sourceD_wreq_ready_T_8 = bits(sourceD_wreq.bankSum, 2, 2)
node _sourceD_wreq_ready_T_9 = and(_sourceD_wreq_ready_T_8, io.sourceD_wadr.bits.mask)
node _sourceD_wreq_ready_T_10 = orr(_sourceD_wreq_ready_T_9)
node _sourceD_wreq_ready_T_11 = eq(_sourceD_wreq_ready_T_10, UInt<1>(0h0))
node _sourceD_wreq_ready_T_12 = bits(sourceD_wreq.bankSum, 3, 3)
node _sourceD_wreq_ready_T_13 = and(_sourceD_wreq_ready_T_12, io.sourceD_wadr.bits.mask)
node _sourceD_wreq_ready_T_14 = orr(_sourceD_wreq_ready_T_13)
node _sourceD_wreq_ready_T_15 = eq(_sourceD_wreq_ready_T_14, UInt<1>(0h0))
node sourceD_wreq_ready_lo = cat(_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3)
node sourceD_wreq_ready_hi = cat(_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11)
node sourceD_wreq_ready = cat(sourceD_wreq_ready_hi, sourceD_wreq_ready_lo)
node _sourceD_wreq_io_sourceD_wadr_ready_T = bits(sourceD_wreq_a, 1, 0)
node _sourceD_wreq_io_sourceD_wadr_ready_T_1 = dshr(sourceD_wreq_ready, _sourceD_wreq_io_sourceD_wadr_ready_T)
node _sourceD_wreq_io_sourceD_wadr_ready_T_2 = bits(_sourceD_wreq_io_sourceD_wadr_ready_T_1, 0, 0)
connect io.sourceD_wadr.ready, _sourceD_wreq_io_sourceD_wadr_ready_T_2
connect sourceD_wreq.wen, UInt<1>(0h1)
node _sourceD_wreq_out_index_T = shr(sourceD_wreq_a, 2)
connect sourceD_wreq.index, _sourceD_wreq_out_index_T
node _sourceD_wreq_out_bankSel_T = bits(sourceD_wreq_select, 0, 0)
node _sourceD_wreq_out_bankSel_T_1 = bits(sourceD_wreq_select, 1, 1)
node _sourceD_wreq_out_bankSel_T_2 = bits(sourceD_wreq_select, 2, 2)
node _sourceD_wreq_out_bankSel_T_3 = bits(sourceD_wreq_select, 3, 3)
node sourceD_wreq_out_bankSel_lo = cat(_sourceD_wreq_out_bankSel_T_1, _sourceD_wreq_out_bankSel_T)
node sourceD_wreq_out_bankSel_hi = cat(_sourceD_wreq_out_bankSel_T_3, _sourceD_wreq_out_bankSel_T_2)
node _sourceD_wreq_out_bankSel_T_4 = cat(sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo)
node _sourceD_wreq_out_bankSel_T_5 = bits(io.sourceD_wadr.bits.mask, 0, 0)
node _sourceD_wreq_out_bankSel_T_6 = mux(_sourceD_wreq_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0))
node _sourceD_wreq_out_bankSel_T_7 = and(_sourceD_wreq_out_bankSel_T_4, _sourceD_wreq_out_bankSel_T_6)
node _sourceD_wreq_out_bankSel_T_8 = mux(io.sourceD_wadr.valid, _sourceD_wreq_out_bankSel_T_7, UInt<1>(0h0))
connect sourceD_wreq.bankSel, _sourceD_wreq_out_bankSel_T_8
node _sourceD_wreq_out_bankEn_T = bits(sourceD_wreq_ready, 0, 0)
node _sourceD_wreq_out_bankEn_T_1 = bits(sourceD_wreq_ready, 1, 1)
node _sourceD_wreq_out_bankEn_T_2 = bits(sourceD_wreq_ready, 2, 2)
node _sourceD_wreq_out_bankEn_T_3 = bits(sourceD_wreq_ready, 3, 3)
node sourceD_wreq_out_bankEn_lo = cat(_sourceD_wreq_out_bankEn_T_1, _sourceD_wreq_out_bankEn_T)
node sourceD_wreq_out_bankEn_hi = cat(_sourceD_wreq_out_bankEn_T_3, _sourceD_wreq_out_bankEn_T_2)
node _sourceD_wreq_out_bankEn_T_4 = cat(sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo)
node _sourceD_wreq_out_bankEn_T_5 = and(sourceD_wreq.bankSel, _sourceD_wreq_out_bankEn_T_4)
node _sourceD_wreq_out_bankEn_T_6 = mux(io.sourceD_wadr.bits.noop, UInt<1>(0h0), _sourceD_wreq_out_bankEn_T_5)
connect sourceD_wreq.bankEn, _sourceD_wreq_out_bankEn_T_6
connect sourceD_wreq.data[0], sourceD_wreq_words_0
connect sourceD_wreq.data[1], sourceD_wreq_words_0
connect sourceD_wreq.data[2], sourceD_wreq_words_0
connect sourceD_wreq.data[3], sourceD_wreq_words_0
connect sinkC_req.bankSum, UInt<1>(0h0)
node _T = or(sinkC_req.bankSel, UInt<1>(0h0))
connect sourceC_req.bankSum, _T
node _T_1 = or(sourceC_req.bankSel, _T)
connect sinkD_req.bankSum, _T_1
node _T_2 = or(sinkD_req.bankSel, _T_1)
connect sourceD_wreq.bankSum, _T_2
node _T_3 = or(sourceD_wreq.bankSel, _T_2)
connect sourceD_rreq.bankSum, _T_3
node _T_4 = or(sourceD_rreq.bankSel, _T_3)
node _regout_en_T = bits(sinkC_req.bankEn, 0, 0)
node _regout_en_T_1 = bits(sourceC_req.bankEn, 0, 0)
node _regout_en_T_2 = bits(sinkD_req.bankEn, 0, 0)
node _regout_en_T_3 = bits(sourceD_wreq.bankEn, 0, 0)
node _regout_en_T_4 = bits(sourceD_rreq.bankEn, 0, 0)
node _regout_en_T_5 = or(_regout_en_T, _regout_en_T_1)
node _regout_en_T_6 = or(_regout_en_T_5, _regout_en_T_2)
node _regout_en_T_7 = or(_regout_en_T_6, _regout_en_T_3)
node regout_en = or(_regout_en_T_7, _regout_en_T_4)
node regout_sel_0 = bits(sinkC_req.bankSel, 0, 0)
node regout_sel_1 = bits(sourceC_req.bankSel, 0, 0)
node regout_sel_2 = bits(sinkD_req.bankSel, 0, 0)
node regout_sel_3 = bits(sourceD_wreq.bankSel, 0, 0)
node regout_sel_4 = bits(sourceD_rreq.bankSel, 0, 0)
node _regout_wen_T = mux(regout_sel_3, sourceD_wreq.wen, sourceD_rreq.wen)
node _regout_wen_T_1 = mux(regout_sel_2, sinkD_req.wen, _regout_wen_T)
node _regout_wen_T_2 = mux(regout_sel_1, sourceC_req.wen, _regout_wen_T_1)
node regout_wen = mux(regout_sel_0, sinkC_req.wen, _regout_wen_T_2)
node _regout_idx_T = mux(regout_sel_3, sourceD_wreq.index, sourceD_rreq.index)
node _regout_idx_T_1 = mux(regout_sel_2, sinkD_req.index, _regout_idx_T)
node _regout_idx_T_2 = mux(regout_sel_1, sourceC_req.index, _regout_idx_T_1)
node regout_idx = mux(regout_sel_0, sinkC_req.index, _regout_idx_T_2)
node _regout_data_T = mux(regout_sel_3, sourceD_wreq.data[0], sourceD_rreq.data[0])
node _regout_data_T_1 = mux(regout_sel_2, sinkD_req.data[0], _regout_data_T)
node _regout_data_T_2 = mux(regout_sel_1, sourceC_req.data[0], _regout_data_T_1)
node regout_data = mux(regout_sel_0, sinkC_req.data[0], _regout_data_T_2)
node _regout_T = and(regout_wen, regout_en)
when _regout_T :
write mport regout_MPORT = cc_banks_0[regout_idx], clock
connect regout_MPORT, regout_data
node _regout_T_1 = eq(regout_wen, UInt<1>(0h0))
node _regout_T_2 = and(_regout_T_1, regout_en)
wire _regout_WIRE : UInt<14>
invalidate _regout_WIRE
when _regout_T_2 :
connect _regout_WIRE, regout_idx
read mport regout_MPORT_1 = cc_banks_0[_regout_WIRE], clock
node _regout_T_3 = eq(regout_wen, UInt<1>(0h0))
node _regout_T_4 = and(_regout_T_3, regout_en)
reg regout_REG : UInt<1>, clock
connect regout_REG, _regout_T_4
reg regout_r : UInt<64>, clock
when regout_REG :
connect regout_r, regout_MPORT_1
node _regout_en_T_8 = bits(sinkC_req.bankEn, 1, 1)
node _regout_en_T_9 = bits(sourceC_req.bankEn, 1, 1)
node _regout_en_T_10 = bits(sinkD_req.bankEn, 1, 1)
node _regout_en_T_11 = bits(sourceD_wreq.bankEn, 1, 1)
node _regout_en_T_12 = bits(sourceD_rreq.bankEn, 1, 1)
node _regout_en_T_13 = or(_regout_en_T_8, _regout_en_T_9)
node _regout_en_T_14 = or(_regout_en_T_13, _regout_en_T_10)
node _regout_en_T_15 = or(_regout_en_T_14, _regout_en_T_11)
node regout_en_1 = or(_regout_en_T_15, _regout_en_T_12)
node regout_sel_0_1 = bits(sinkC_req.bankSel, 1, 1)
node regout_sel_1_1 = bits(sourceC_req.bankSel, 1, 1)
node regout_sel_2_1 = bits(sinkD_req.bankSel, 1, 1)
node regout_sel_3_1 = bits(sourceD_wreq.bankSel, 1, 1)
node regout_sel_4_1 = bits(sourceD_rreq.bankSel, 1, 1)
node _regout_wen_T_3 = mux(regout_sel_3_1, sourceD_wreq.wen, sourceD_rreq.wen)
node _regout_wen_T_4 = mux(regout_sel_2_1, sinkD_req.wen, _regout_wen_T_3)
node _regout_wen_T_5 = mux(regout_sel_1_1, sourceC_req.wen, _regout_wen_T_4)
node regout_wen_1 = mux(regout_sel_0_1, sinkC_req.wen, _regout_wen_T_5)
node _regout_idx_T_3 = mux(regout_sel_3_1, sourceD_wreq.index, sourceD_rreq.index)
node _regout_idx_T_4 = mux(regout_sel_2_1, sinkD_req.index, _regout_idx_T_3)
node _regout_idx_T_5 = mux(regout_sel_1_1, sourceC_req.index, _regout_idx_T_4)
node regout_idx_1 = mux(regout_sel_0_1, sinkC_req.index, _regout_idx_T_5)
node _regout_data_T_3 = mux(regout_sel_3_1, sourceD_wreq.data[1], sourceD_rreq.data[1])
node _regout_data_T_4 = mux(regout_sel_2_1, sinkD_req.data[1], _regout_data_T_3)
node _regout_data_T_5 = mux(regout_sel_1_1, sourceC_req.data[1], _regout_data_T_4)
node regout_data_1 = mux(regout_sel_0_1, sinkC_req.data[1], _regout_data_T_5)
node _regout_T_5 = and(regout_wen_1, regout_en_1)
when _regout_T_5 :
write mport regout_MPORT_2 = cc_banks_1[regout_idx_1], clock
connect regout_MPORT_2, regout_data_1
node _regout_T_6 = eq(regout_wen_1, UInt<1>(0h0))
node _regout_T_7 = and(_regout_T_6, regout_en_1)
wire _regout_WIRE_1 : UInt<14>
invalidate _regout_WIRE_1
when _regout_T_7 :
connect _regout_WIRE_1, regout_idx_1
read mport regout_MPORT_3 = cc_banks_1[_regout_WIRE_1], clock
node _regout_T_8 = eq(regout_wen_1, UInt<1>(0h0))
node _regout_T_9 = and(_regout_T_8, regout_en_1)
reg regout_REG_1 : UInt<1>, clock
connect regout_REG_1, _regout_T_9
reg regout_r_1 : UInt<64>, clock
when regout_REG_1 :
connect regout_r_1, regout_MPORT_3
node _regout_en_T_16 = bits(sinkC_req.bankEn, 2, 2)
node _regout_en_T_17 = bits(sourceC_req.bankEn, 2, 2)
node _regout_en_T_18 = bits(sinkD_req.bankEn, 2, 2)
node _regout_en_T_19 = bits(sourceD_wreq.bankEn, 2, 2)
node _regout_en_T_20 = bits(sourceD_rreq.bankEn, 2, 2)
node _regout_en_T_21 = or(_regout_en_T_16, _regout_en_T_17)
node _regout_en_T_22 = or(_regout_en_T_21, _regout_en_T_18)
node _regout_en_T_23 = or(_regout_en_T_22, _regout_en_T_19)
node regout_en_2 = or(_regout_en_T_23, _regout_en_T_20)
node regout_sel_0_2 = bits(sinkC_req.bankSel, 2, 2)
node regout_sel_1_2 = bits(sourceC_req.bankSel, 2, 2)
node regout_sel_2_2 = bits(sinkD_req.bankSel, 2, 2)
node regout_sel_3_2 = bits(sourceD_wreq.bankSel, 2, 2)
node regout_sel_4_2 = bits(sourceD_rreq.bankSel, 2, 2)
node _regout_wen_T_6 = mux(regout_sel_3_2, sourceD_wreq.wen, sourceD_rreq.wen)
node _regout_wen_T_7 = mux(regout_sel_2_2, sinkD_req.wen, _regout_wen_T_6)
node _regout_wen_T_8 = mux(regout_sel_1_2, sourceC_req.wen, _regout_wen_T_7)
node regout_wen_2 = mux(regout_sel_0_2, sinkC_req.wen, _regout_wen_T_8)
node _regout_idx_T_6 = mux(regout_sel_3_2, sourceD_wreq.index, sourceD_rreq.index)
node _regout_idx_T_7 = mux(regout_sel_2_2, sinkD_req.index, _regout_idx_T_6)
node _regout_idx_T_8 = mux(regout_sel_1_2, sourceC_req.index, _regout_idx_T_7)
node regout_idx_2 = mux(regout_sel_0_2, sinkC_req.index, _regout_idx_T_8)
node _regout_data_T_6 = mux(regout_sel_3_2, sourceD_wreq.data[2], sourceD_rreq.data[2])
node _regout_data_T_7 = mux(regout_sel_2_2, sinkD_req.data[2], _regout_data_T_6)
node _regout_data_T_8 = mux(regout_sel_1_2, sourceC_req.data[2], _regout_data_T_7)
node regout_data_2 = mux(regout_sel_0_2, sinkC_req.data[2], _regout_data_T_8)
node _regout_T_10 = and(regout_wen_2, regout_en_2)
when _regout_T_10 :
write mport regout_MPORT_4 = cc_banks_2[regout_idx_2], clock
connect regout_MPORT_4, regout_data_2
node _regout_T_11 = eq(regout_wen_2, UInt<1>(0h0))
node _regout_T_12 = and(_regout_T_11, regout_en_2)
wire _regout_WIRE_2 : UInt<14>
invalidate _regout_WIRE_2
when _regout_T_12 :
connect _regout_WIRE_2, regout_idx_2
read mport regout_MPORT_5 = cc_banks_2[_regout_WIRE_2], clock
node _regout_T_13 = eq(regout_wen_2, UInt<1>(0h0))
node _regout_T_14 = and(_regout_T_13, regout_en_2)
reg regout_REG_2 : UInt<1>, clock
connect regout_REG_2, _regout_T_14
reg regout_r_2 : UInt<64>, clock
when regout_REG_2 :
connect regout_r_2, regout_MPORT_5
node _regout_en_T_24 = bits(sinkC_req.bankEn, 3, 3)
node _regout_en_T_25 = bits(sourceC_req.bankEn, 3, 3)
node _regout_en_T_26 = bits(sinkD_req.bankEn, 3, 3)
node _regout_en_T_27 = bits(sourceD_wreq.bankEn, 3, 3)
node _regout_en_T_28 = bits(sourceD_rreq.bankEn, 3, 3)
node _regout_en_T_29 = or(_regout_en_T_24, _regout_en_T_25)
node _regout_en_T_30 = or(_regout_en_T_29, _regout_en_T_26)
node _regout_en_T_31 = or(_regout_en_T_30, _regout_en_T_27)
node regout_en_3 = or(_regout_en_T_31, _regout_en_T_28)
node regout_sel_0_3 = bits(sinkC_req.bankSel, 3, 3)
node regout_sel_1_3 = bits(sourceC_req.bankSel, 3, 3)
node regout_sel_2_3 = bits(sinkD_req.bankSel, 3, 3)
node regout_sel_3_3 = bits(sourceD_wreq.bankSel, 3, 3)
node regout_sel_4_3 = bits(sourceD_rreq.bankSel, 3, 3)
node _regout_wen_T_9 = mux(regout_sel_3_3, sourceD_wreq.wen, sourceD_rreq.wen)
node _regout_wen_T_10 = mux(regout_sel_2_3, sinkD_req.wen, _regout_wen_T_9)
node _regout_wen_T_11 = mux(regout_sel_1_3, sourceC_req.wen, _regout_wen_T_10)
node regout_wen_3 = mux(regout_sel_0_3, sinkC_req.wen, _regout_wen_T_11)
node _regout_idx_T_9 = mux(regout_sel_3_3, sourceD_wreq.index, sourceD_rreq.index)
node _regout_idx_T_10 = mux(regout_sel_2_3, sinkD_req.index, _regout_idx_T_9)
node _regout_idx_T_11 = mux(regout_sel_1_3, sourceC_req.index, _regout_idx_T_10)
node regout_idx_3 = mux(regout_sel_0_3, sinkC_req.index, _regout_idx_T_11)
node _regout_data_T_9 = mux(regout_sel_3_3, sourceD_wreq.data[3], sourceD_rreq.data[3])
node _regout_data_T_10 = mux(regout_sel_2_3, sinkD_req.data[3], _regout_data_T_9)
node _regout_data_T_11 = mux(regout_sel_1_3, sourceC_req.data[3], _regout_data_T_10)
node regout_data_3 = mux(regout_sel_0_3, sinkC_req.data[3], _regout_data_T_11)
node _regout_T_15 = and(regout_wen_3, regout_en_3)
when _regout_T_15 :
write mport regout_MPORT_6 = cc_banks_3[regout_idx_3], clock
connect regout_MPORT_6, regout_data_3
node _regout_T_16 = eq(regout_wen_3, UInt<1>(0h0))
node _regout_T_17 = and(_regout_T_16, regout_en_3)
wire _regout_WIRE_3 : UInt<14>
invalidate _regout_WIRE_3
when _regout_T_17 :
connect _regout_WIRE_3, regout_idx_3
read mport regout_MPORT_7 = cc_banks_3[_regout_WIRE_3], clock
node _regout_T_18 = eq(regout_wen_3, UInt<1>(0h0))
node _regout_T_19 = and(_regout_T_18, regout_en_3)
reg regout_REG_3 : UInt<1>, clock
connect regout_REG_3, _regout_T_19
reg regout_r_3 : UInt<64>, clock
when regout_REG_3 :
connect regout_r_3, regout_MPORT_7
wire regout : UInt<64>[4]
connect regout[0], regout_r
connect regout[1], regout_r_1
connect regout[2], regout_r_2
connect regout[3], regout_r_3
reg regsel_sourceC_REG : UInt, clock
connect regsel_sourceC_REG, sourceC_req.bankEn
reg regsel_sourceC : UInt, clock
connect regsel_sourceC, regsel_sourceC_REG
reg regsel_sourceD_REG : UInt, clock
connect regsel_sourceD_REG, sourceD_rreq.bankEn
reg regsel_sourceD : UInt, clock
connect regsel_sourceD, regsel_sourceD_REG
node _decodeC_T = bits(regsel_sourceC, 0, 0)
node _decodeC_T_1 = mux(_decodeC_T, regout[0], UInt<1>(0h0))
node _decodeC_T_2 = bits(regsel_sourceC, 1, 1)
node _decodeC_T_3 = mux(_decodeC_T_2, regout[1], UInt<1>(0h0))
node _decodeC_T_4 = bits(regsel_sourceC, 2, 2)
node _decodeC_T_5 = mux(_decodeC_T_4, regout[2], UInt<1>(0h0))
node _decodeC_T_6 = bits(regsel_sourceC, 3, 3)
node _decodeC_T_7 = mux(_decodeC_T_6, regout[3], UInt<1>(0h0))
node _decodeC_T_8 = or(_decodeC_T_1, _decodeC_T_3)
node _decodeC_T_9 = or(_decodeC_T_8, _decodeC_T_5)
node decodeC_0 = or(_decodeC_T_9, _decodeC_T_7)
connect io.sourceC_dat.data, decodeC_0
node _decodeD_T = bits(regsel_sourceD, 0, 0)
node _decodeD_T_1 = mux(_decodeD_T, regout[0], UInt<1>(0h0))
node _decodeD_T_2 = bits(regsel_sourceD, 1, 1)
node _decodeD_T_3 = mux(_decodeD_T_2, regout[1], UInt<1>(0h0))
node _decodeD_T_4 = bits(regsel_sourceD, 2, 2)
node _decodeD_T_5 = mux(_decodeD_T_4, regout[2], UInt<1>(0h0))
node _decodeD_T_6 = bits(regsel_sourceD, 3, 3)
node _decodeD_T_7 = mux(_decodeD_T_6, regout[3], UInt<1>(0h0))
node _decodeD_T_8 = or(_decodeD_T_1, _decodeD_T_3)
node _decodeD_T_9 = or(_decodeD_T_8, _decodeD_T_5)
node decodeD_0 = or(_decodeD_T_9, _decodeD_T_7)
connect io.sourceD_rdat.data, decodeD_0 | module BankedStore( // @[BankedStore.scala:59:7]
input clock, // @[BankedStore.scala:59:7]
input reset, // @[BankedStore.scala:59:7]
output io_sinkC_adr_ready, // @[BankedStore.scala:61:14]
input io_sinkC_adr_valid, // @[BankedStore.scala:61:14]
input io_sinkC_adr_bits_noop, // @[BankedStore.scala:61:14]
input [2:0] io_sinkC_adr_bits_way, // @[BankedStore.scala:61:14]
input [9:0] io_sinkC_adr_bits_set, // @[BankedStore.scala:61:14]
input [2:0] io_sinkC_adr_bits_beat, // @[BankedStore.scala:61:14]
input io_sinkC_adr_bits_mask, // @[BankedStore.scala:61:14]
input [63:0] io_sinkC_dat_data, // @[BankedStore.scala:61:14]
output io_sinkD_adr_ready, // @[BankedStore.scala:61:14]
input io_sinkD_adr_valid, // @[BankedStore.scala:61:14]
input io_sinkD_adr_bits_noop, // @[BankedStore.scala:61:14]
input [2:0] io_sinkD_adr_bits_way, // @[BankedStore.scala:61:14]
input [9:0] io_sinkD_adr_bits_set, // @[BankedStore.scala:61:14]
input [2:0] io_sinkD_adr_bits_beat, // @[BankedStore.scala:61:14]
input [63:0] io_sinkD_dat_data, // @[BankedStore.scala:61:14]
output io_sourceC_adr_ready, // @[BankedStore.scala:61:14]
input io_sourceC_adr_valid, // @[BankedStore.scala:61:14]
input [2:0] io_sourceC_adr_bits_way, // @[BankedStore.scala:61:14]
input [9:0] io_sourceC_adr_bits_set, // @[BankedStore.scala:61:14]
input [2:0] io_sourceC_adr_bits_beat, // @[BankedStore.scala:61:14]
output [63:0] io_sourceC_dat_data, // @[BankedStore.scala:61:14]
output io_sourceD_radr_ready, // @[BankedStore.scala:61:14]
input io_sourceD_radr_valid, // @[BankedStore.scala:61:14]
input [2:0] io_sourceD_radr_bits_way, // @[BankedStore.scala:61:14]
input [9:0] io_sourceD_radr_bits_set, // @[BankedStore.scala:61:14]
input [2:0] io_sourceD_radr_bits_beat, // @[BankedStore.scala:61:14]
input io_sourceD_radr_bits_mask, // @[BankedStore.scala:61:14]
output [63:0] io_sourceD_rdat_data, // @[BankedStore.scala:61:14]
output io_sourceD_wadr_ready, // @[BankedStore.scala:61:14]
input io_sourceD_wadr_valid, // @[BankedStore.scala:61:14]
input [2:0] io_sourceD_wadr_bits_way, // @[BankedStore.scala:61:14]
input [9:0] io_sourceD_wadr_bits_set, // @[BankedStore.scala:61:14]
input [2:0] io_sourceD_wadr_bits_beat, // @[BankedStore.scala:61:14]
input io_sourceD_wadr_bits_mask, // @[BankedStore.scala:61:14]
input [63:0] io_sourceD_wdat_data // @[BankedStore.scala:61:14]
);
wire [3:0] sinkC_req_bankSel; // @[BankedStore.scala:128:19]
wire [63:0] _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [63:0] _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [63:0] _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [63:0] _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire io_sinkC_adr_valid_0 = io_sinkC_adr_valid; // @[BankedStore.scala:59:7]
wire io_sinkC_adr_bits_noop_0 = io_sinkC_adr_bits_noop; // @[BankedStore.scala:59:7]
wire [2:0] io_sinkC_adr_bits_way_0 = io_sinkC_adr_bits_way; // @[BankedStore.scala:59:7]
wire [9:0] io_sinkC_adr_bits_set_0 = io_sinkC_adr_bits_set; // @[BankedStore.scala:59:7]
wire [2:0] io_sinkC_adr_bits_beat_0 = io_sinkC_adr_bits_beat; // @[BankedStore.scala:59:7]
wire io_sinkC_adr_bits_mask_0 = io_sinkC_adr_bits_mask; // @[BankedStore.scala:59:7]
wire [63:0] io_sinkC_dat_data_0 = io_sinkC_dat_data; // @[BankedStore.scala:59:7]
wire io_sinkD_adr_valid_0 = io_sinkD_adr_valid; // @[BankedStore.scala:59:7]
wire io_sinkD_adr_bits_noop_0 = io_sinkD_adr_bits_noop; // @[BankedStore.scala:59:7]
wire [2:0] io_sinkD_adr_bits_way_0 = io_sinkD_adr_bits_way; // @[BankedStore.scala:59:7]
wire [9:0] io_sinkD_adr_bits_set_0 = io_sinkD_adr_bits_set; // @[BankedStore.scala:59:7]
wire [2:0] io_sinkD_adr_bits_beat_0 = io_sinkD_adr_bits_beat; // @[BankedStore.scala:59:7]
wire [63:0] io_sinkD_dat_data_0 = io_sinkD_dat_data; // @[BankedStore.scala:59:7]
wire io_sourceC_adr_valid_0 = io_sourceC_adr_valid; // @[BankedStore.scala:59:7]
wire [2:0] io_sourceC_adr_bits_way_0 = io_sourceC_adr_bits_way; // @[BankedStore.scala:59:7]
wire [9:0] io_sourceC_adr_bits_set_0 = io_sourceC_adr_bits_set; // @[BankedStore.scala:59:7]
wire [2:0] io_sourceC_adr_bits_beat_0 = io_sourceC_adr_bits_beat; // @[BankedStore.scala:59:7]
wire io_sourceD_radr_valid_0 = io_sourceD_radr_valid; // @[BankedStore.scala:59:7]
wire [2:0] io_sourceD_radr_bits_way_0 = io_sourceD_radr_bits_way; // @[BankedStore.scala:59:7]
wire [9:0] io_sourceD_radr_bits_set_0 = io_sourceD_radr_bits_set; // @[BankedStore.scala:59:7]
wire [2:0] io_sourceD_radr_bits_beat_0 = io_sourceD_radr_bits_beat; // @[BankedStore.scala:59:7]
wire io_sourceD_radr_bits_mask_0 = io_sourceD_radr_bits_mask; // @[BankedStore.scala:59:7]
wire io_sourceD_wadr_valid_0 = io_sourceD_wadr_valid; // @[BankedStore.scala:59:7]
wire [2:0] io_sourceD_wadr_bits_way_0 = io_sourceD_wadr_bits_way; // @[BankedStore.scala:59:7]
wire [9:0] io_sourceD_wadr_bits_set_0 = io_sourceD_wadr_bits_set; // @[BankedStore.scala:59:7]
wire [2:0] io_sourceD_wadr_bits_beat_0 = io_sourceD_wadr_bits_beat; // @[BankedStore.scala:59:7]
wire io_sourceD_wadr_bits_mask_0 = io_sourceD_wadr_bits_mask; // @[BankedStore.scala:59:7]
wire [63:0] io_sourceD_wdat_data_0 = io_sourceD_wdat_data; // @[BankedStore.scala:59:7]
wire [3:0] sinkC_req_bankSum = 4'h0; // @[BankedStore.scala:128:19]
wire [1:0] sinkC_req_ready_lo = 2'h3; // @[BankedStore.scala:131:21, :137:72]
wire [1:0] sinkC_req_ready_hi = 2'h3; // @[BankedStore.scala:131:21, :137:72]
wire [1:0] sinkC_req_out_bankEn_lo = 2'h3; // @[BankedStore.scala:131:21, :137:72]
wire [1:0] sinkC_req_out_bankEn_hi = 2'h3; // @[BankedStore.scala:131:21, :137:72]
wire [3:0] sinkC_req_ready = 4'hF; // @[BankedStore.scala:131:21]
wire [3:0] _sinkC_req_out_bankEn_T_4 = 4'hF; // @[BankedStore.scala:137:72]
wire [3:0] _sinkD_req_out_bankSel_T_6 = 4'hF; // @[BankedStore.scala:136:71]
wire [3:0] _sourceC_req_out_bankSel_T_6 = 4'hF; // @[BankedStore.scala:136:71]
wire [63:0] sourceC_req_data_0 = 64'h0; // @[BankedStore.scala:128:19]
wire [63:0] sourceC_req_data_1 = 64'h0; // @[BankedStore.scala:128:19]
wire [63:0] sourceC_req_data_2 = 64'h0; // @[BankedStore.scala:128:19]
wire [63:0] sourceC_req_data_3 = 64'h0; // @[BankedStore.scala:128:19]
wire [63:0] sourceD_rreq_data_0 = 64'h0; // @[BankedStore.scala:128:19]
wire [63:0] sourceD_rreq_data_1 = 64'h0; // @[BankedStore.scala:128:19]
wire [63:0] sourceD_rreq_data_2 = 64'h0; // @[BankedStore.scala:128:19]
wire [63:0] sourceD_rreq_data_3 = 64'h0; // @[BankedStore.scala:128:19]
wire io_sourceC_adr_bits_noop = 1'h0; // @[BankedStore.scala:59:7]
wire io_sourceD_radr_bits_noop = 1'h0; // @[BankedStore.scala:59:7]
wire io_sourceD_wadr_bits_noop = 1'h0; // @[BankedStore.scala:59:7]
wire _sinkC_req_ready_T = 1'h0; // @[BankedStore.scala:131:71]
wire _sinkC_req_ready_T_1 = 1'h0; // @[BankedStore.scala:131:96]
wire _sinkC_req_ready_T_2 = 1'h0; // @[BankedStore.scala:131:101]
wire _sinkC_req_ready_T_4 = 1'h0; // @[BankedStore.scala:131:71]
wire _sinkC_req_ready_T_5 = 1'h0; // @[BankedStore.scala:131:96]
wire _sinkC_req_ready_T_6 = 1'h0; // @[BankedStore.scala:131:101]
wire _sinkC_req_ready_T_8 = 1'h0; // @[BankedStore.scala:131:71]
wire _sinkC_req_ready_T_9 = 1'h0; // @[BankedStore.scala:131:96]
wire _sinkC_req_ready_T_10 = 1'h0; // @[BankedStore.scala:131:101]
wire _sinkC_req_ready_T_12 = 1'h0; // @[BankedStore.scala:131:71]
wire _sinkC_req_ready_T_13 = 1'h0; // @[BankedStore.scala:131:96]
wire _sinkC_req_ready_T_14 = 1'h0; // @[BankedStore.scala:131:101]
wire sourceC_req_wen = 1'h0; // @[BankedStore.scala:128:19]
wire sourceD_rreq_wen = 1'h0; // @[BankedStore.scala:128:19]
wire io_sinkD_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7]
wire io_sourceC_adr_bits_mask = 1'h1; // @[BankedStore.scala:59:7]
wire sinkC_req_wen = 1'h1; // @[BankedStore.scala:128:19]
wire _sinkC_req_ready_T_3 = 1'h1; // @[BankedStore.scala:131:58]
wire _sinkC_req_ready_T_7 = 1'h1; // @[BankedStore.scala:131:58]
wire _sinkC_req_ready_T_11 = 1'h1; // @[BankedStore.scala:131:58]
wire _sinkC_req_ready_T_15 = 1'h1; // @[BankedStore.scala:131:58]
wire _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:132:21]
wire _sinkC_req_out_bankEn_T = 1'h1; // @[BankedStore.scala:137:72]
wire _sinkC_req_out_bankEn_T_1 = 1'h1; // @[BankedStore.scala:137:72]
wire _sinkC_req_out_bankEn_T_2 = 1'h1; // @[BankedStore.scala:137:72]
wire _sinkC_req_out_bankEn_T_3 = 1'h1; // @[BankedStore.scala:137:72]
wire sinkD_req_wen = 1'h1; // @[BankedStore.scala:128:19]
wire _sinkD_req_out_bankSel_T_5 = 1'h1; // @[BankedStore.scala:136:71]
wire _sourceC_req_out_bankSel_T_5 = 1'h1; // @[BankedStore.scala:136:71]
wire sourceD_wreq_wen = 1'h1; // @[BankedStore.scala:128:19]
wire _sinkC_req_out_bankSel_T_5 = io_sinkC_adr_bits_mask_0; // @[BankedStore.scala:59:7, :136:71]
wire [63:0] sinkC_req_words_0 = io_sinkC_dat_data_0; // @[BankedStore.scala:59:7, :123:19]
wire _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:132:21]
wire [63:0] sinkD_req_words_0 = io_sinkD_dat_data_0; // @[BankedStore.scala:59:7, :123:19]
wire _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:132:21]
wire [63:0] decodeC_0; // @[BankedStore.scala:180:85]
wire _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:132:21]
wire _sourceD_rreq_out_bankSel_T_5 = io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :136:71]
wire [63:0] decodeD_0; // @[BankedStore.scala:187:85]
wire _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:132:21]
wire _sourceD_wreq_out_bankSel_T_5 = io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :136:71]
wire [63:0] sourceD_wreq_words_0 = io_sourceD_wdat_data_0; // @[BankedStore.scala:59:7, :123:19]
wire io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7]
wire io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7]
wire io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7]
wire [63:0] io_sourceC_dat_data_0; // @[BankedStore.scala:59:7]
wire io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7]
wire [63:0] io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7]
wire io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7]
wire [13:0] regout_idx; // @[Mux.scala:50:70]
wire _regout_T; // @[BankedStore.scala:171:15]
wire [13:0] _regout_WIRE; // @[BankedStore.scala:172:21]
wire _regout_T_2; // @[BankedStore.scala:172:32]
wire [13:0] regout_idx_1; // @[Mux.scala:50:70]
wire _regout_T_5; // @[BankedStore.scala:171:15]
wire [13:0] _regout_WIRE_1; // @[BankedStore.scala:172:21]
wire _regout_T_7; // @[BankedStore.scala:172:32]
wire [13:0] regout_idx_2; // @[Mux.scala:50:70]
wire _regout_T_10; // @[BankedStore.scala:171:15]
wire [13:0] _regout_WIRE_2; // @[BankedStore.scala:172:21]
wire _regout_T_12; // @[BankedStore.scala:172:32]
wire [13:0] regout_idx_3; // @[Mux.scala:50:70]
wire _regout_T_15; // @[BankedStore.scala:171:15]
wire [13:0] _regout_WIRE_3; // @[BankedStore.scala:172:21]
wire _regout_T_17; // @[BankedStore.scala:172:32]
wire [63:0] sinkC_req_data_0 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sinkC_req_data_1 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sinkC_req_data_2 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sinkC_req_data_3 = sinkC_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [12:0] sinkC_req_a_hi = {io_sinkC_adr_bits_way_0, io_sinkC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91]
wire [15:0] sinkC_req_a = {sinkC_req_a_hi, io_sinkC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91]
wire [13:0] _sinkC_req_out_index_T; // @[BankedStore.scala:135:23]
wire [3:0] _sinkC_req_out_bankSel_T_8; // @[BankedStore.scala:136:24]
wire [3:0] _sinkC_req_out_bankEn_T_5 = sinkC_req_bankSel; // @[BankedStore.scala:128:19, :137:55]
wire [3:0] sourceC_req_bankSum = sinkC_req_bankSel; // @[BankedStore.scala:128:19]
wire [3:0] _sinkC_req_out_bankEn_T_6; // @[BankedStore.scala:137:24]
wire [13:0] sinkC_req_index; // @[BankedStore.scala:128:19]
wire [3:0] sinkC_req_bankEn; // @[BankedStore.scala:128:19]
wire [1:0] _sinkC_req_select_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28]
wire [1:0] _sinkC_req_io_sinkC_adr_ready_T = sinkC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23]
wire [1:0] sinkC_req_select_shiftAmount = _sinkC_req_select_T; // @[OneHot.scala:64:49]
wire [3:0] _sinkC_req_select_T_1 = 4'h1 << sinkC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] sinkC_req_select = _sinkC_req_select_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] _sinkC_req_io_sinkC_adr_ready_T_1 = 4'hF >> _sinkC_req_io_sinkC_adr_ready_T; // @[BankedStore.scala:132:{21,23}]
assign _sinkC_req_io_sinkC_adr_ready_T_2 = _sinkC_req_io_sinkC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21]
assign io_sinkC_adr_ready_0 = _sinkC_req_io_sinkC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21]
assign _sinkC_req_out_index_T = sinkC_req_a[15:2]; // @[BankedStore.scala:126:91, :135:23]
assign sinkC_req_index = _sinkC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23]
wire _sinkC_req_out_bankSel_T = sinkC_req_select[0]; // @[OneHot.scala:65:27]
wire _sinkC_req_out_bankSel_T_1 = sinkC_req_select[1]; // @[OneHot.scala:65:27]
wire _sinkC_req_out_bankSel_T_2 = sinkC_req_select[2]; // @[OneHot.scala:65:27]
wire _sinkC_req_out_bankSel_T_3 = sinkC_req_select[3]; // @[OneHot.scala:65:27]
wire [1:0] sinkC_req_out_bankSel_lo = {_sinkC_req_out_bankSel_T_1, _sinkC_req_out_bankSel_T}; // @[BankedStore.scala:136:49]
wire [1:0] sinkC_req_out_bankSel_hi = {_sinkC_req_out_bankSel_T_3, _sinkC_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49]
wire [3:0] _sinkC_req_out_bankSel_T_4 = {sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49]
wire [3:0] _sinkC_req_out_bankSel_T_6 = {4{_sinkC_req_out_bankSel_T_5}}; // @[BankedStore.scala:136:71]
wire [3:0] _sinkC_req_out_bankSel_T_7 = _sinkC_req_out_bankSel_T_4 & _sinkC_req_out_bankSel_T_6; // @[BankedStore.scala:136:{49,65,71}]
assign _sinkC_req_out_bankSel_T_8 = io_sinkC_adr_valid_0 ? _sinkC_req_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala:59:7, :136:{24,65}]
assign sinkC_req_bankSel = _sinkC_req_out_bankSel_T_8; // @[BankedStore.scala:128:19, :136:24]
assign _sinkC_req_out_bankEn_T_6 = io_sinkC_adr_bits_noop_0 ? 4'h0 : _sinkC_req_out_bankEn_T_5; // @[BankedStore.scala:59:7, :137:{24,55}]
assign sinkC_req_bankEn = _sinkC_req_out_bankEn_T_6; // @[BankedStore.scala:128:19, :137:24]
wire [63:0] sinkD_req_data_0 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sinkD_req_data_1 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sinkD_req_data_2 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sinkD_req_data_3 = sinkD_req_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [12:0] sinkD_req_a_hi = {io_sinkD_adr_bits_way_0, io_sinkD_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91]
wire [15:0] sinkD_req_a = {sinkD_req_a_hi, io_sinkD_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91]
wire [13:0] _sinkD_req_out_index_T; // @[BankedStore.scala:135:23]
wire [3:0] _sinkD_req_out_bankSel_T_8; // @[BankedStore.scala:136:24]
wire [3:0] _sinkD_req_out_bankEn_T_6; // @[BankedStore.scala:137:24]
wire [13:0] sinkD_req_index; // @[BankedStore.scala:128:19]
wire [3:0] sinkD_req_bankSel; // @[BankedStore.scala:128:19]
wire [3:0] sinkD_req_bankSum; // @[BankedStore.scala:128:19]
wire [3:0] sinkD_req_bankEn; // @[BankedStore.scala:128:19]
wire [1:0] _sinkD_req_select_T = sinkD_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28]
wire [1:0] _sinkD_req_io_sinkD_adr_ready_T = sinkD_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23]
wire [1:0] sinkD_req_select_shiftAmount = _sinkD_req_select_T; // @[OneHot.scala:64:49]
wire [3:0] _sinkD_req_select_T_1 = 4'h1 << sinkD_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] sinkD_req_select = _sinkD_req_select_T_1; // @[OneHot.scala:65:{12,27}]
wire _sinkD_req_ready_T = sinkD_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71]
wire _sinkD_req_ready_T_1 = _sinkD_req_ready_T; // @[BankedStore.scala:131:{71,96}]
wire _sinkD_req_ready_T_2 = _sinkD_req_ready_T_1; // @[BankedStore.scala:131:{96,101}]
wire _sinkD_req_ready_T_3 = ~_sinkD_req_ready_T_2; // @[BankedStore.scala:131:{58,101}]
wire _sinkD_req_ready_T_4 = sinkD_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71]
wire _sinkD_req_ready_T_5 = _sinkD_req_ready_T_4; // @[BankedStore.scala:131:{71,96}]
wire _sinkD_req_ready_T_6 = _sinkD_req_ready_T_5; // @[BankedStore.scala:131:{96,101}]
wire _sinkD_req_ready_T_7 = ~_sinkD_req_ready_T_6; // @[BankedStore.scala:131:{58,101}]
wire _sinkD_req_ready_T_8 = sinkD_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71]
wire _sinkD_req_ready_T_9 = _sinkD_req_ready_T_8; // @[BankedStore.scala:131:{71,96}]
wire _sinkD_req_ready_T_10 = _sinkD_req_ready_T_9; // @[BankedStore.scala:131:{96,101}]
wire _sinkD_req_ready_T_11 = ~_sinkD_req_ready_T_10; // @[BankedStore.scala:131:{58,101}]
wire _sinkD_req_ready_T_12 = sinkD_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71]
wire _sinkD_req_ready_T_13 = _sinkD_req_ready_T_12; // @[BankedStore.scala:131:{71,96}]
wire _sinkD_req_ready_T_14 = _sinkD_req_ready_T_13; // @[BankedStore.scala:131:{96,101}]
wire _sinkD_req_ready_T_15 = ~_sinkD_req_ready_T_14; // @[BankedStore.scala:131:{58,101}]
wire [1:0] sinkD_req_ready_lo = {_sinkD_req_ready_T_7, _sinkD_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}]
wire [1:0] sinkD_req_ready_hi = {_sinkD_req_ready_T_15, _sinkD_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}]
wire [3:0] sinkD_req_ready = {sinkD_req_ready_hi, sinkD_req_ready_lo}; // @[BankedStore.scala:131:21]
wire [3:0] _sinkD_req_io_sinkD_adr_ready_T_1 = sinkD_req_ready >> _sinkD_req_io_sinkD_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}]
assign _sinkD_req_io_sinkD_adr_ready_T_2 = _sinkD_req_io_sinkD_adr_ready_T_1[0]; // @[BankedStore.scala:132:21]
assign io_sinkD_adr_ready_0 = _sinkD_req_io_sinkD_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21]
assign _sinkD_req_out_index_T = sinkD_req_a[15:2]; // @[BankedStore.scala:126:91, :135:23]
assign sinkD_req_index = _sinkD_req_out_index_T; // @[BankedStore.scala:128:19, :135:23]
wire _sinkD_req_out_bankSel_T = sinkD_req_select[0]; // @[OneHot.scala:65:27]
wire _sinkD_req_out_bankSel_T_1 = sinkD_req_select[1]; // @[OneHot.scala:65:27]
wire _sinkD_req_out_bankSel_T_2 = sinkD_req_select[2]; // @[OneHot.scala:65:27]
wire _sinkD_req_out_bankSel_T_3 = sinkD_req_select[3]; // @[OneHot.scala:65:27]
wire [1:0] sinkD_req_out_bankSel_lo = {_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T}; // @[BankedStore.scala:136:49]
wire [1:0] sinkD_req_out_bankSel_hi = {_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49]
wire [3:0] _sinkD_req_out_bankSel_T_4 = {sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo}; // @[BankedStore.scala:136:49]
wire [3:0] _sinkD_req_out_bankSel_T_7 = _sinkD_req_out_bankSel_T_4; // @[BankedStore.scala:136:{49,65}]
assign _sinkD_req_out_bankSel_T_8 = io_sinkD_adr_valid_0 ? _sinkD_req_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala:59:7, :136:{24,65}]
assign sinkD_req_bankSel = _sinkD_req_out_bankSel_T_8; // @[BankedStore.scala:128:19, :136:24]
wire _sinkD_req_out_bankEn_T = sinkD_req_ready[0]; // @[BankedStore.scala:131:21, :137:72]
wire _sinkD_req_out_bankEn_T_1 = sinkD_req_ready[1]; // @[BankedStore.scala:131:21, :137:72]
wire _sinkD_req_out_bankEn_T_2 = sinkD_req_ready[2]; // @[BankedStore.scala:131:21, :137:72]
wire _sinkD_req_out_bankEn_T_3 = sinkD_req_ready[3]; // @[BankedStore.scala:131:21, :137:72]
wire [1:0] sinkD_req_out_bankEn_lo = {_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T}; // @[BankedStore.scala:137:72]
wire [1:0] sinkD_req_out_bankEn_hi = {_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72]
wire [3:0] _sinkD_req_out_bankEn_T_4 = {sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo}; // @[BankedStore.scala:137:72]
wire [3:0] _sinkD_req_out_bankEn_T_5 = sinkD_req_bankSel & _sinkD_req_out_bankEn_T_4; // @[BankedStore.scala:128:19, :137:{55,72}]
assign _sinkD_req_out_bankEn_T_6 = io_sinkD_adr_bits_noop_0 ? 4'h0 : _sinkD_req_out_bankEn_T_5; // @[BankedStore.scala:59:7, :137:{24,55}]
assign sinkD_req_bankEn = _sinkD_req_out_bankEn_T_6; // @[BankedStore.scala:128:19, :137:24]
wire [12:0] sourceC_req_a_hi = {io_sourceC_adr_bits_way_0, io_sourceC_adr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91]
wire [15:0] sourceC_req_a = {sourceC_req_a_hi, io_sourceC_adr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91]
wire [13:0] _sourceC_req_out_index_T; // @[BankedStore.scala:135:23]
wire [3:0] _sourceC_req_out_bankSel_T_8; // @[BankedStore.scala:136:24]
wire [3:0] _sourceC_req_out_bankEn_T_6; // @[BankedStore.scala:137:24]
wire [13:0] sourceC_req_index; // @[BankedStore.scala:128:19]
wire [3:0] sourceC_req_bankSel; // @[BankedStore.scala:128:19]
wire [3:0] sourceC_req_bankEn; // @[BankedStore.scala:128:19]
wire [1:0] _sourceC_req_select_T = sourceC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28]
wire [1:0] _sourceC_req_io_sourceC_adr_ready_T = sourceC_req_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23]
wire [1:0] sourceC_req_select_shiftAmount = _sourceC_req_select_T; // @[OneHot.scala:64:49]
wire [3:0] _sourceC_req_select_T_1 = 4'h1 << sourceC_req_select_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] sourceC_req_select = _sourceC_req_select_T_1; // @[OneHot.scala:65:{12,27}]
wire _sourceC_req_ready_T = sourceC_req_bankSum[0]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceC_req_ready_T_1 = _sourceC_req_ready_T; // @[BankedStore.scala:131:{71,96}]
wire _sourceC_req_ready_T_2 = _sourceC_req_ready_T_1; // @[BankedStore.scala:131:{96,101}]
wire _sourceC_req_ready_T_3 = ~_sourceC_req_ready_T_2; // @[BankedStore.scala:131:{58,101}]
wire _sourceC_req_ready_T_4 = sourceC_req_bankSum[1]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceC_req_ready_T_5 = _sourceC_req_ready_T_4; // @[BankedStore.scala:131:{71,96}]
wire _sourceC_req_ready_T_6 = _sourceC_req_ready_T_5; // @[BankedStore.scala:131:{96,101}]
wire _sourceC_req_ready_T_7 = ~_sourceC_req_ready_T_6; // @[BankedStore.scala:131:{58,101}]
wire _sourceC_req_ready_T_8 = sourceC_req_bankSum[2]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceC_req_ready_T_9 = _sourceC_req_ready_T_8; // @[BankedStore.scala:131:{71,96}]
wire _sourceC_req_ready_T_10 = _sourceC_req_ready_T_9; // @[BankedStore.scala:131:{96,101}]
wire _sourceC_req_ready_T_11 = ~_sourceC_req_ready_T_10; // @[BankedStore.scala:131:{58,101}]
wire _sourceC_req_ready_T_12 = sourceC_req_bankSum[3]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceC_req_ready_T_13 = _sourceC_req_ready_T_12; // @[BankedStore.scala:131:{71,96}]
wire _sourceC_req_ready_T_14 = _sourceC_req_ready_T_13; // @[BankedStore.scala:131:{96,101}]
wire _sourceC_req_ready_T_15 = ~_sourceC_req_ready_T_14; // @[BankedStore.scala:131:{58,101}]
wire [1:0] sourceC_req_ready_lo = {_sourceC_req_ready_T_7, _sourceC_req_ready_T_3}; // @[BankedStore.scala:131:{21,58}]
wire [1:0] sourceC_req_ready_hi = {_sourceC_req_ready_T_15, _sourceC_req_ready_T_11}; // @[BankedStore.scala:131:{21,58}]
wire [3:0] sourceC_req_ready = {sourceC_req_ready_hi, sourceC_req_ready_lo}; // @[BankedStore.scala:131:21]
wire [3:0] _sourceC_req_io_sourceC_adr_ready_T_1 = sourceC_req_ready >> _sourceC_req_io_sourceC_adr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}]
assign _sourceC_req_io_sourceC_adr_ready_T_2 = _sourceC_req_io_sourceC_adr_ready_T_1[0]; // @[BankedStore.scala:132:21]
assign io_sourceC_adr_ready_0 = _sourceC_req_io_sourceC_adr_ready_T_2; // @[BankedStore.scala:59:7, :132:21]
assign _sourceC_req_out_index_T = sourceC_req_a[15:2]; // @[BankedStore.scala:126:91, :135:23]
assign sourceC_req_index = _sourceC_req_out_index_T; // @[BankedStore.scala:128:19, :135:23]
wire _sourceC_req_out_bankSel_T = sourceC_req_select[0]; // @[OneHot.scala:65:27]
wire _sourceC_req_out_bankSel_T_1 = sourceC_req_select[1]; // @[OneHot.scala:65:27]
wire _sourceC_req_out_bankSel_T_2 = sourceC_req_select[2]; // @[OneHot.scala:65:27]
wire _sourceC_req_out_bankSel_T_3 = sourceC_req_select[3]; // @[OneHot.scala:65:27]
wire [1:0] sourceC_req_out_bankSel_lo = {_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T}; // @[BankedStore.scala:136:49]
wire [1:0] sourceC_req_out_bankSel_hi = {_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2}; // @[BankedStore.scala:136:49]
wire [3:0] _sourceC_req_out_bankSel_T_4 = {sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo}; // @[BankedStore.scala:136:49]
wire [3:0] _sourceC_req_out_bankSel_T_7 = _sourceC_req_out_bankSel_T_4; // @[BankedStore.scala:136:{49,65}]
assign _sourceC_req_out_bankSel_T_8 = io_sourceC_adr_valid_0 ? _sourceC_req_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala:59:7, :136:{24,65}]
assign sourceC_req_bankSel = _sourceC_req_out_bankSel_T_8; // @[BankedStore.scala:128:19, :136:24]
wire _sourceC_req_out_bankEn_T = sourceC_req_ready[0]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceC_req_out_bankEn_T_1 = sourceC_req_ready[1]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceC_req_out_bankEn_T_2 = sourceC_req_ready[2]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceC_req_out_bankEn_T_3 = sourceC_req_ready[3]; // @[BankedStore.scala:131:21, :137:72]
wire [1:0] sourceC_req_out_bankEn_lo = {_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T}; // @[BankedStore.scala:137:72]
wire [1:0] sourceC_req_out_bankEn_hi = {_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2}; // @[BankedStore.scala:137:72]
wire [3:0] _sourceC_req_out_bankEn_T_4 = {sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo}; // @[BankedStore.scala:137:72]
wire [3:0] _sourceC_req_out_bankEn_T_5 = sourceC_req_bankSel & _sourceC_req_out_bankEn_T_4; // @[BankedStore.scala:128:19, :137:{55,72}]
assign _sourceC_req_out_bankEn_T_6 = _sourceC_req_out_bankEn_T_5; // @[BankedStore.scala:137:{24,55}]
assign sourceC_req_bankEn = _sourceC_req_out_bankEn_T_6; // @[BankedStore.scala:128:19, :137:24]
wire [12:0] sourceD_rreq_a_hi = {io_sourceD_radr_bits_way_0, io_sourceD_radr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91]
wire [15:0] sourceD_rreq_a = {sourceD_rreq_a_hi, io_sourceD_radr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91]
wire [13:0] _sourceD_rreq_out_index_T; // @[BankedStore.scala:135:23]
wire [3:0] _sourceD_rreq_out_bankSel_T_8; // @[BankedStore.scala:136:24]
wire [3:0] _sourceD_rreq_out_bankEn_T_6; // @[BankedStore.scala:137:24]
wire [13:0] sourceD_rreq_index; // @[BankedStore.scala:128:19]
wire [3:0] sourceD_rreq_bankSel; // @[BankedStore.scala:128:19]
wire [3:0] sourceD_rreq_bankSum; // @[BankedStore.scala:128:19]
wire [3:0] sourceD_rreq_bankEn; // @[BankedStore.scala:128:19]
wire [1:0] _sourceD_rreq_select_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28]
wire [1:0] _sourceD_rreq_io_sourceD_radr_ready_T = sourceD_rreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23]
wire [1:0] sourceD_rreq_select_shiftAmount = _sourceD_rreq_select_T; // @[OneHot.scala:64:49]
wire [3:0] _sourceD_rreq_select_T_1 = 4'h1 << sourceD_rreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] sourceD_rreq_select = _sourceD_rreq_select_T_1; // @[OneHot.scala:65:{12,27}]
wire _sourceD_rreq_ready_T = sourceD_rreq_bankSum[0]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_rreq_ready_T_1 = _sourceD_rreq_ready_T & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_rreq_ready_T_2 = _sourceD_rreq_ready_T_1; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_rreq_ready_T_3 = ~_sourceD_rreq_ready_T_2; // @[BankedStore.scala:131:{58,101}]
wire _sourceD_rreq_ready_T_4 = sourceD_rreq_bankSum[1]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_rreq_ready_T_5 = _sourceD_rreq_ready_T_4 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_rreq_ready_T_6 = _sourceD_rreq_ready_T_5; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_rreq_ready_T_7 = ~_sourceD_rreq_ready_T_6; // @[BankedStore.scala:131:{58,101}]
wire _sourceD_rreq_ready_T_8 = sourceD_rreq_bankSum[2]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_rreq_ready_T_9 = _sourceD_rreq_ready_T_8 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_rreq_ready_T_10 = _sourceD_rreq_ready_T_9; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_rreq_ready_T_11 = ~_sourceD_rreq_ready_T_10; // @[BankedStore.scala:131:{58,101}]
wire _sourceD_rreq_ready_T_12 = sourceD_rreq_bankSum[3]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_rreq_ready_T_13 = _sourceD_rreq_ready_T_12 & io_sourceD_radr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_rreq_ready_T_14 = _sourceD_rreq_ready_T_13; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_rreq_ready_T_15 = ~_sourceD_rreq_ready_T_14; // @[BankedStore.scala:131:{58,101}]
wire [1:0] sourceD_rreq_ready_lo = {_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}]
wire [1:0] sourceD_rreq_ready_hi = {_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}]
wire [3:0] sourceD_rreq_ready = {sourceD_rreq_ready_hi, sourceD_rreq_ready_lo}; // @[BankedStore.scala:131:21]
wire [3:0] _sourceD_rreq_io_sourceD_radr_ready_T_1 = sourceD_rreq_ready >> _sourceD_rreq_io_sourceD_radr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}]
assign _sourceD_rreq_io_sourceD_radr_ready_T_2 = _sourceD_rreq_io_sourceD_radr_ready_T_1[0]; // @[BankedStore.scala:132:21]
assign io_sourceD_radr_ready_0 = _sourceD_rreq_io_sourceD_radr_ready_T_2; // @[BankedStore.scala:59:7, :132:21]
assign _sourceD_rreq_out_index_T = sourceD_rreq_a[15:2]; // @[BankedStore.scala:126:91, :135:23]
assign sourceD_rreq_index = _sourceD_rreq_out_index_T; // @[BankedStore.scala:128:19, :135:23]
wire _sourceD_rreq_out_bankSel_T = sourceD_rreq_select[0]; // @[OneHot.scala:65:27]
wire _sourceD_rreq_out_bankSel_T_1 = sourceD_rreq_select[1]; // @[OneHot.scala:65:27]
wire _sourceD_rreq_out_bankSel_T_2 = sourceD_rreq_select[2]; // @[OneHot.scala:65:27]
wire _sourceD_rreq_out_bankSel_T_3 = sourceD_rreq_select[3]; // @[OneHot.scala:65:27]
wire [1:0] sourceD_rreq_out_bankSel_lo = {_sourceD_rreq_out_bankSel_T_1, _sourceD_rreq_out_bankSel_T}; // @[BankedStore.scala:136:49]
wire [1:0] sourceD_rreq_out_bankSel_hi = {_sourceD_rreq_out_bankSel_T_3, _sourceD_rreq_out_bankSel_T_2}; // @[BankedStore.scala:136:49]
wire [3:0] _sourceD_rreq_out_bankSel_T_4 = {sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo}; // @[BankedStore.scala:136:49]
wire [3:0] _sourceD_rreq_out_bankSel_T_6 = {4{_sourceD_rreq_out_bankSel_T_5}}; // @[BankedStore.scala:136:71]
wire [3:0] _sourceD_rreq_out_bankSel_T_7 = _sourceD_rreq_out_bankSel_T_4 & _sourceD_rreq_out_bankSel_T_6; // @[BankedStore.scala:136:{49,65,71}]
assign _sourceD_rreq_out_bankSel_T_8 = io_sourceD_radr_valid_0 ? _sourceD_rreq_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala:59:7, :136:{24,65}]
assign sourceD_rreq_bankSel = _sourceD_rreq_out_bankSel_T_8; // @[BankedStore.scala:128:19, :136:24]
wire _sourceD_rreq_out_bankEn_T = sourceD_rreq_ready[0]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceD_rreq_out_bankEn_T_1 = sourceD_rreq_ready[1]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceD_rreq_out_bankEn_T_2 = sourceD_rreq_ready[2]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceD_rreq_out_bankEn_T_3 = sourceD_rreq_ready[3]; // @[BankedStore.scala:131:21, :137:72]
wire [1:0] sourceD_rreq_out_bankEn_lo = {_sourceD_rreq_out_bankEn_T_1, _sourceD_rreq_out_bankEn_T}; // @[BankedStore.scala:137:72]
wire [1:0] sourceD_rreq_out_bankEn_hi = {_sourceD_rreq_out_bankEn_T_3, _sourceD_rreq_out_bankEn_T_2}; // @[BankedStore.scala:137:72]
wire [3:0] _sourceD_rreq_out_bankEn_T_4 = {sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo}; // @[BankedStore.scala:137:72]
wire [3:0] _sourceD_rreq_out_bankEn_T_5 = sourceD_rreq_bankSel & _sourceD_rreq_out_bankEn_T_4; // @[BankedStore.scala:128:19, :137:{55,72}]
assign _sourceD_rreq_out_bankEn_T_6 = _sourceD_rreq_out_bankEn_T_5; // @[BankedStore.scala:137:{24,55}]
assign sourceD_rreq_bankEn = _sourceD_rreq_out_bankEn_T_6; // @[BankedStore.scala:128:19, :137:24]
wire [63:0] sourceD_wreq_data_0 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sourceD_wreq_data_1 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sourceD_wreq_data_2 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [63:0] sourceD_wreq_data_3 = sourceD_wreq_words_0; // @[BankedStore.scala:123:19, :128:19]
wire [12:0] sourceD_wreq_a_hi = {io_sourceD_wadr_bits_way_0, io_sourceD_wadr_bits_set_0}; // @[BankedStore.scala:59:7, :126:91]
wire [15:0] sourceD_wreq_a = {sourceD_wreq_a_hi, io_sourceD_wadr_bits_beat_0}; // @[BankedStore.scala:59:7, :126:91]
wire [13:0] _sourceD_wreq_out_index_T; // @[BankedStore.scala:135:23]
wire [3:0] _sourceD_wreq_out_bankSel_T_8; // @[BankedStore.scala:136:24]
wire [3:0] _sourceD_wreq_out_bankEn_T_6; // @[BankedStore.scala:137:24]
wire [13:0] sourceD_wreq_index; // @[BankedStore.scala:128:19]
wire [3:0] sourceD_wreq_bankSel; // @[BankedStore.scala:128:19]
wire [3:0] sourceD_wreq_bankSum; // @[BankedStore.scala:128:19]
wire [3:0] sourceD_wreq_bankEn; // @[BankedStore.scala:128:19]
wire [1:0] _sourceD_wreq_select_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28]
wire [1:0] _sourceD_wreq_io_sourceD_wadr_ready_T = sourceD_wreq_a[1:0]; // @[BankedStore.scala:126:91, :130:28, :132:23]
wire [1:0] sourceD_wreq_select_shiftAmount = _sourceD_wreq_select_T; // @[OneHot.scala:64:49]
wire [3:0] _sourceD_wreq_select_T_1 = 4'h1 << sourceD_wreq_select_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] sourceD_wreq_select = _sourceD_wreq_select_T_1; // @[OneHot.scala:65:{12,27}]
wire _sourceD_wreq_ready_T = sourceD_wreq_bankSum[0]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_wreq_ready_T_1 = _sourceD_wreq_ready_T & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_wreq_ready_T_2 = _sourceD_wreq_ready_T_1; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_wreq_ready_T_3 = ~_sourceD_wreq_ready_T_2; // @[BankedStore.scala:131:{58,101}]
wire _sourceD_wreq_ready_T_4 = sourceD_wreq_bankSum[1]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_wreq_ready_T_5 = _sourceD_wreq_ready_T_4 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_wreq_ready_T_6 = _sourceD_wreq_ready_T_5; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_wreq_ready_T_7 = ~_sourceD_wreq_ready_T_6; // @[BankedStore.scala:131:{58,101}]
wire _sourceD_wreq_ready_T_8 = sourceD_wreq_bankSum[2]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_wreq_ready_T_9 = _sourceD_wreq_ready_T_8 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_wreq_ready_T_10 = _sourceD_wreq_ready_T_9; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_wreq_ready_T_11 = ~_sourceD_wreq_ready_T_10; // @[BankedStore.scala:131:{58,101}]
wire _sourceD_wreq_ready_T_12 = sourceD_wreq_bankSum[3]; // @[BankedStore.scala:128:19, :131:71]
wire _sourceD_wreq_ready_T_13 = _sourceD_wreq_ready_T_12 & io_sourceD_wadr_bits_mask_0; // @[BankedStore.scala:59:7, :131:{71,96}]
wire _sourceD_wreq_ready_T_14 = _sourceD_wreq_ready_T_13; // @[BankedStore.scala:131:{96,101}]
wire _sourceD_wreq_ready_T_15 = ~_sourceD_wreq_ready_T_14; // @[BankedStore.scala:131:{58,101}]
wire [1:0] sourceD_wreq_ready_lo = {_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3}; // @[BankedStore.scala:131:{21,58}]
wire [1:0] sourceD_wreq_ready_hi = {_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11}; // @[BankedStore.scala:131:{21,58}]
wire [3:0] sourceD_wreq_ready = {sourceD_wreq_ready_hi, sourceD_wreq_ready_lo}; // @[BankedStore.scala:131:21]
wire [3:0] _sourceD_wreq_io_sourceD_wadr_ready_T_1 = sourceD_wreq_ready >> _sourceD_wreq_io_sourceD_wadr_ready_T; // @[BankedStore.scala:131:21, :132:{21,23}]
assign _sourceD_wreq_io_sourceD_wadr_ready_T_2 = _sourceD_wreq_io_sourceD_wadr_ready_T_1[0]; // @[BankedStore.scala:132:21]
assign io_sourceD_wadr_ready_0 = _sourceD_wreq_io_sourceD_wadr_ready_T_2; // @[BankedStore.scala:59:7, :132:21]
assign _sourceD_wreq_out_index_T = sourceD_wreq_a[15:2]; // @[BankedStore.scala:126:91, :135:23]
assign sourceD_wreq_index = _sourceD_wreq_out_index_T; // @[BankedStore.scala:128:19, :135:23]
wire _sourceD_wreq_out_bankSel_T = sourceD_wreq_select[0]; // @[OneHot.scala:65:27]
wire _sourceD_wreq_out_bankSel_T_1 = sourceD_wreq_select[1]; // @[OneHot.scala:65:27]
wire _sourceD_wreq_out_bankSel_T_2 = sourceD_wreq_select[2]; // @[OneHot.scala:65:27]
wire _sourceD_wreq_out_bankSel_T_3 = sourceD_wreq_select[3]; // @[OneHot.scala:65:27]
wire [1:0] sourceD_wreq_out_bankSel_lo = {_sourceD_wreq_out_bankSel_T_1, _sourceD_wreq_out_bankSel_T}; // @[BankedStore.scala:136:49]
wire [1:0] sourceD_wreq_out_bankSel_hi = {_sourceD_wreq_out_bankSel_T_3, _sourceD_wreq_out_bankSel_T_2}; // @[BankedStore.scala:136:49]
wire [3:0] _sourceD_wreq_out_bankSel_T_4 = {sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo}; // @[BankedStore.scala:136:49]
wire [3:0] _sourceD_wreq_out_bankSel_T_6 = {4{_sourceD_wreq_out_bankSel_T_5}}; // @[BankedStore.scala:136:71]
wire [3:0] _sourceD_wreq_out_bankSel_T_7 = _sourceD_wreq_out_bankSel_T_4 & _sourceD_wreq_out_bankSel_T_6; // @[BankedStore.scala:136:{49,65,71}]
assign _sourceD_wreq_out_bankSel_T_8 = io_sourceD_wadr_valid_0 ? _sourceD_wreq_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala:59:7, :136:{24,65}]
assign sourceD_wreq_bankSel = _sourceD_wreq_out_bankSel_T_8; // @[BankedStore.scala:128:19, :136:24]
wire _sourceD_wreq_out_bankEn_T = sourceD_wreq_ready[0]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceD_wreq_out_bankEn_T_1 = sourceD_wreq_ready[1]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceD_wreq_out_bankEn_T_2 = sourceD_wreq_ready[2]; // @[BankedStore.scala:131:21, :137:72]
wire _sourceD_wreq_out_bankEn_T_3 = sourceD_wreq_ready[3]; // @[BankedStore.scala:131:21, :137:72]
wire [1:0] sourceD_wreq_out_bankEn_lo = {_sourceD_wreq_out_bankEn_T_1, _sourceD_wreq_out_bankEn_T}; // @[BankedStore.scala:137:72]
wire [1:0] sourceD_wreq_out_bankEn_hi = {_sourceD_wreq_out_bankEn_T_3, _sourceD_wreq_out_bankEn_T_2}; // @[BankedStore.scala:137:72]
wire [3:0] _sourceD_wreq_out_bankEn_T_4 = {sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo}; // @[BankedStore.scala:137:72]
wire [3:0] _sourceD_wreq_out_bankEn_T_5 = sourceD_wreq_bankSel & _sourceD_wreq_out_bankEn_T_4; // @[BankedStore.scala:128:19, :137:{55,72}]
assign _sourceD_wreq_out_bankEn_T_6 = _sourceD_wreq_out_bankEn_T_5; // @[BankedStore.scala:137:{24,55}]
assign sourceD_wreq_bankEn = _sourceD_wreq_out_bankEn_T_6; // @[BankedStore.scala:128:19, :137:24]
assign sinkD_req_bankSum = sourceC_req_bankSel | sinkC_req_bankSel; // @[BankedStore.scala:128:19, :161:17]
assign sourceD_wreq_bankSum = sinkD_req_bankSel | sinkD_req_bankSum; // @[BankedStore.scala:128:19, :161:17]
assign sourceD_rreq_bankSum = sourceD_wreq_bankSel | sourceD_wreq_bankSum; // @[BankedStore.scala:128:19, :161:17]
wire _regout_en_T = sinkC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_1 = sourceC_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_2 = sinkD_req_bankEn[0]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_3 = sourceD_wreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_4 = sourceD_rreq_bankEn[0]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_5 = _regout_en_T | _regout_en_T_1; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_6 = _regout_en_T_5 | _regout_en_T_2; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_7 = _regout_en_T_6 | _regout_en_T_3; // @[BankedStore.scala:165:{32,45}]
wire regout_en = _regout_en_T_7 | _regout_en_T_4; // @[BankedStore.scala:165:{32,45}]
wire regout_sel_0 = sinkC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_1 = sourceC_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_2 = sinkD_req_bankSel[0]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_3 = sourceD_wreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T = regout_sel_3; // @[Mux.scala:50:70]
wire regout_sel_4 = sourceD_rreq_bankSel[0]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T_1 = regout_sel_2 | _regout_wen_T; // @[Mux.scala:50:70]
wire _regout_wen_T_2 = ~regout_sel_1 & _regout_wen_T_1; // @[Mux.scala:50:70]
wire regout_wen = regout_sel_0 | _regout_wen_T_2; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T = regout_sel_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_1 = regout_sel_2 ? sinkD_req_index : _regout_idx_T; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_2 = regout_sel_1 ? sourceC_req_index : _regout_idx_T_1; // @[Mux.scala:50:70]
assign regout_idx = regout_sel_0 ? sinkC_req_index : _regout_idx_T_2; // @[Mux.scala:50:70]
assign _regout_WIRE = regout_idx; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T = regout_sel_3 ? sourceD_wreq_data_0 : 64'h0; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_1 = regout_sel_2 ? sinkD_req_data_0 : _regout_data_T; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_2 = regout_sel_1 ? 64'h0 : _regout_data_T_1; // @[Mux.scala:50:70]
wire [63:0] regout_data = regout_sel_0 ? sinkC_req_data_0 : _regout_data_T_2; // @[Mux.scala:50:70]
assign _regout_T = regout_wen & regout_en; // @[Mux.scala:50:70]
wire _regout_T_1 = ~regout_wen; // @[Mux.scala:50:70]
assign _regout_T_2 = _regout_T_1 & regout_en; // @[BankedStore.scala:165:45, :172:{27,32}]
wire _regout_T_3 = ~regout_wen; // @[Mux.scala:50:70]
wire _regout_T_4 = _regout_T_3 & regout_en; // @[BankedStore.scala:165:45, :172:{48,53}]
reg regout_REG; // @[BankedStore.scala:172:47]
reg [63:0] regout_r; // @[BankedStore.scala:172:14]
wire [63:0] regout_0 = regout_r; // @[BankedStore.scala:164:23, :172:14]
wire _regout_en_T_8 = sinkC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_9 = sourceC_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_10 = sinkD_req_bankEn[1]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_11 = sourceD_wreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_12 = sourceD_rreq_bankEn[1]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_13 = _regout_en_T_8 | _regout_en_T_9; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_14 = _regout_en_T_13 | _regout_en_T_10; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_15 = _regout_en_T_14 | _regout_en_T_11; // @[BankedStore.scala:165:{32,45}]
wire regout_en_1 = _regout_en_T_15 | _regout_en_T_12; // @[BankedStore.scala:165:{32,45}]
wire regout_sel_0_1 = sinkC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_1_1 = sourceC_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_2_1 = sinkD_req_bankSel[1]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_3_1 = sourceD_wreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T_3 = regout_sel_3_1; // @[Mux.scala:50:70]
wire regout_sel_4_1 = sourceD_rreq_bankSel[1]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T_4 = regout_sel_2_1 | _regout_wen_T_3; // @[Mux.scala:50:70]
wire _regout_wen_T_5 = ~regout_sel_1_1 & _regout_wen_T_4; // @[Mux.scala:50:70]
wire regout_wen_1 = regout_sel_0_1 | _regout_wen_T_5; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_3 = regout_sel_3_1 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_4 = regout_sel_2_1 ? sinkD_req_index : _regout_idx_T_3; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_5 = regout_sel_1_1 ? sourceC_req_index : _regout_idx_T_4; // @[Mux.scala:50:70]
assign regout_idx_1 = regout_sel_0_1 ? sinkC_req_index : _regout_idx_T_5; // @[Mux.scala:50:70]
assign _regout_WIRE_1 = regout_idx_1; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_3 = regout_sel_3_1 ? sourceD_wreq_data_1 : 64'h0; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_4 = regout_sel_2_1 ? sinkD_req_data_1 : _regout_data_T_3; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_5 = regout_sel_1_1 ? 64'h0 : _regout_data_T_4; // @[Mux.scala:50:70]
wire [63:0] regout_data_1 = regout_sel_0_1 ? sinkC_req_data_1 : _regout_data_T_5; // @[Mux.scala:50:70]
assign _regout_T_5 = regout_wen_1 & regout_en_1; // @[Mux.scala:50:70]
wire _regout_T_6 = ~regout_wen_1; // @[Mux.scala:50:70]
assign _regout_T_7 = _regout_T_6 & regout_en_1; // @[BankedStore.scala:165:45, :172:{27,32}]
wire _regout_T_8 = ~regout_wen_1; // @[Mux.scala:50:70]
wire _regout_T_9 = _regout_T_8 & regout_en_1; // @[BankedStore.scala:165:45, :172:{48,53}]
reg regout_REG_1; // @[BankedStore.scala:172:47]
reg [63:0] regout_r_1; // @[BankedStore.scala:172:14]
wire [63:0] regout_1 = regout_r_1; // @[BankedStore.scala:164:23, :172:14]
wire _regout_en_T_16 = sinkC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_17 = sourceC_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_18 = sinkD_req_bankEn[2]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_19 = sourceD_wreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_20 = sourceD_rreq_bankEn[2]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_21 = _regout_en_T_16 | _regout_en_T_17; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_22 = _regout_en_T_21 | _regout_en_T_18; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_23 = _regout_en_T_22 | _regout_en_T_19; // @[BankedStore.scala:165:{32,45}]
wire regout_en_2 = _regout_en_T_23 | _regout_en_T_20; // @[BankedStore.scala:165:{32,45}]
wire regout_sel_0_2 = sinkC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_1_2 = sourceC_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_2_2 = sinkD_req_bankSel[2]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_3_2 = sourceD_wreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T_6 = regout_sel_3_2; // @[Mux.scala:50:70]
wire regout_sel_4_2 = sourceD_rreq_bankSel[2]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T_7 = regout_sel_2_2 | _regout_wen_T_6; // @[Mux.scala:50:70]
wire _regout_wen_T_8 = ~regout_sel_1_2 & _regout_wen_T_7; // @[Mux.scala:50:70]
wire regout_wen_2 = regout_sel_0_2 | _regout_wen_T_8; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_6 = regout_sel_3_2 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_7 = regout_sel_2_2 ? sinkD_req_index : _regout_idx_T_6; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_8 = regout_sel_1_2 ? sourceC_req_index : _regout_idx_T_7; // @[Mux.scala:50:70]
assign regout_idx_2 = regout_sel_0_2 ? sinkC_req_index : _regout_idx_T_8; // @[Mux.scala:50:70]
assign _regout_WIRE_2 = regout_idx_2; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_6 = regout_sel_3_2 ? sourceD_wreq_data_2 : 64'h0; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_7 = regout_sel_2_2 ? sinkD_req_data_2 : _regout_data_T_6; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_8 = regout_sel_1_2 ? 64'h0 : _regout_data_T_7; // @[Mux.scala:50:70]
wire [63:0] regout_data_2 = regout_sel_0_2 ? sinkC_req_data_2 : _regout_data_T_8; // @[Mux.scala:50:70]
assign _regout_T_10 = regout_wen_2 & regout_en_2; // @[Mux.scala:50:70]
wire _regout_T_11 = ~regout_wen_2; // @[Mux.scala:50:70]
assign _regout_T_12 = _regout_T_11 & regout_en_2; // @[BankedStore.scala:165:45, :172:{27,32}]
wire _regout_T_13 = ~regout_wen_2; // @[Mux.scala:50:70]
wire _regout_T_14 = _regout_T_13 & regout_en_2; // @[BankedStore.scala:165:45, :172:{48,53}]
reg regout_REG_2; // @[BankedStore.scala:172:47]
reg [63:0] regout_r_2; // @[BankedStore.scala:172:14]
wire [63:0] regout_2 = regout_r_2; // @[BankedStore.scala:164:23, :172:14]
wire _regout_en_T_24 = sinkC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_25 = sourceC_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_26 = sinkD_req_bankEn[3]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_27 = sourceD_wreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_28 = sourceD_rreq_bankEn[3]; // @[BankedStore.scala:128:19, :165:32]
wire _regout_en_T_29 = _regout_en_T_24 | _regout_en_T_25; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_30 = _regout_en_T_29 | _regout_en_T_26; // @[BankedStore.scala:165:{32,45}]
wire _regout_en_T_31 = _regout_en_T_30 | _regout_en_T_27; // @[BankedStore.scala:165:{32,45}]
wire regout_en_3 = _regout_en_T_31 | _regout_en_T_28; // @[BankedStore.scala:165:{32,45}]
wire regout_sel_0_3 = sinkC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_1_3 = sourceC_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_2_3 = sinkD_req_bankSel[3]; // @[BankedStore.scala:128:19, :166:33]
wire regout_sel_3_3 = sourceD_wreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T_9 = regout_sel_3_3; // @[Mux.scala:50:70]
wire regout_sel_4_3 = sourceD_rreq_bankSel[3]; // @[BankedStore.scala:128:19, :166:33]
wire _regout_wen_T_10 = regout_sel_2_3 | _regout_wen_T_9; // @[Mux.scala:50:70]
wire _regout_wen_T_11 = ~regout_sel_1_3 & _regout_wen_T_10; // @[Mux.scala:50:70]
wire regout_wen_3 = regout_sel_0_3 | _regout_wen_T_11; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_9 = regout_sel_3_3 ? sourceD_wreq_index : sourceD_rreq_index; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_10 = regout_sel_2_3 ? sinkD_req_index : _regout_idx_T_9; // @[Mux.scala:50:70]
wire [13:0] _regout_idx_T_11 = regout_sel_1_3 ? sourceC_req_index : _regout_idx_T_10; // @[Mux.scala:50:70]
assign regout_idx_3 = regout_sel_0_3 ? sinkC_req_index : _regout_idx_T_11; // @[Mux.scala:50:70]
assign _regout_WIRE_3 = regout_idx_3; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_9 = regout_sel_3_3 ? sourceD_wreq_data_3 : 64'h0; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_10 = regout_sel_2_3 ? sinkD_req_data_3 : _regout_data_T_9; // @[Mux.scala:50:70]
wire [63:0] _regout_data_T_11 = regout_sel_1_3 ? 64'h0 : _regout_data_T_10; // @[Mux.scala:50:70]
wire [63:0] regout_data_3 = regout_sel_0_3 ? sinkC_req_data_3 : _regout_data_T_11; // @[Mux.scala:50:70]
assign _regout_T_15 = regout_wen_3 & regout_en_3; // @[Mux.scala:50:70]
wire _regout_T_16 = ~regout_wen_3; // @[Mux.scala:50:70]
assign _regout_T_17 = _regout_T_16 & regout_en_3; // @[BankedStore.scala:165:45, :172:{27,32}]
wire _regout_T_18 = ~regout_wen_3; // @[Mux.scala:50:70]
wire _regout_T_19 = _regout_T_18 & regout_en_3; // @[BankedStore.scala:165:45, :172:{48,53}]
reg regout_REG_3; // @[BankedStore.scala:172:47]
reg [63:0] regout_r_3; // @[BankedStore.scala:172:14]
wire [63:0] regout_3 = regout_r_3; // @[BankedStore.scala:164:23, :172:14]
reg [3:0] regsel_sourceC_REG; // @[BankedStore.scala:175:39]
reg [3:0] regsel_sourceC; // @[BankedStore.scala:175:31]
reg [3:0] regsel_sourceD_REG; // @[BankedStore.scala:176:39]
reg [3:0] regsel_sourceD; // @[BankedStore.scala:176:31]
wire _decodeC_T = regsel_sourceC[0]; // @[BankedStore.scala:175:31, :179:38]
wire [63:0] _decodeC_T_1 = _decodeC_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}]
wire _decodeC_T_2 = regsel_sourceC[1]; // @[BankedStore.scala:175:31, :179:38]
wire [63:0] _decodeC_T_3 = _decodeC_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}]
wire _decodeC_T_4 = regsel_sourceC[2]; // @[BankedStore.scala:175:31, :179:38]
wire [63:0] _decodeC_T_5 = _decodeC_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}]
wire _decodeC_T_6 = regsel_sourceC[3]; // @[BankedStore.scala:175:31, :179:38]
wire [63:0] _decodeC_T_7 = _decodeC_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :179:{23,38}]
wire [63:0] _decodeC_T_8 = _decodeC_T_1 | _decodeC_T_3; // @[BankedStore.scala:179:23, :180:85]
wire [63:0] _decodeC_T_9 = _decodeC_T_8 | _decodeC_T_5; // @[BankedStore.scala:179:23, :180:85]
assign decodeC_0 = _decodeC_T_9 | _decodeC_T_7; // @[BankedStore.scala:179:23, :180:85]
assign io_sourceC_dat_data_0 = decodeC_0; // @[BankedStore.scala:59:7, :180:85]
wire _decodeD_T = regsel_sourceD[0]; // @[BankedStore.scala:176:31, :186:38]
wire [63:0] _decodeD_T_1 = _decodeD_T ? regout_0 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}]
wire _decodeD_T_2 = regsel_sourceD[1]; // @[BankedStore.scala:176:31, :186:38]
wire [63:0] _decodeD_T_3 = _decodeD_T_2 ? regout_1 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}]
wire _decodeD_T_4 = regsel_sourceD[2]; // @[BankedStore.scala:176:31, :186:38]
wire [63:0] _decodeD_T_5 = _decodeD_T_4 ? regout_2 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}]
wire _decodeD_T_6 = regsel_sourceD[3]; // @[BankedStore.scala:176:31, :186:38]
wire [63:0] _decodeD_T_7 = _decodeD_T_6 ? regout_3 : 64'h0; // @[BankedStore.scala:164:23, :186:{23,38}]
wire [63:0] _decodeD_T_8 = _decodeD_T_1 | _decodeD_T_3; // @[BankedStore.scala:186:23, :187:85]
wire [63:0] _decodeD_T_9 = _decodeD_T_8 | _decodeD_T_5; // @[BankedStore.scala:186:23, :187:85]
assign decodeD_0 = _decodeD_T_9 | _decodeD_T_7; // @[BankedStore.scala:186:23, :187:85]
assign io_sourceD_rdat_data_0 = decodeD_0; // @[BankedStore.scala:59:7, :187:85]
always @(posedge clock) begin // @[BankedStore.scala:59:7]
regout_REG <= _regout_T_4; // @[BankedStore.scala:172:{47,53}]
if (regout_REG) // @[BankedStore.scala:172:47]
regout_r <= _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26]
regout_REG_1 <= _regout_T_9; // @[BankedStore.scala:172:{47,53}]
if (regout_REG_1) // @[BankedStore.scala:172:47]
regout_r_1 <= _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26]
regout_REG_2 <= _regout_T_14; // @[BankedStore.scala:172:{47,53}]
if (regout_REG_2) // @[BankedStore.scala:172:47]
regout_r_2 <= _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26]
regout_REG_3 <= _regout_T_19; // @[BankedStore.scala:172:{47,53}]
if (regout_REG_3) // @[BankedStore.scala:172:47]
regout_r_3 <= _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26]
regsel_sourceC_REG <= sourceC_req_bankEn; // @[BankedStore.scala:128:19, :175:39]
regsel_sourceC <= regsel_sourceC_REG; // @[BankedStore.scala:175:{31,39}]
regsel_sourceD_REG <= sourceD_rreq_bankEn; // @[BankedStore.scala:128:19, :176:39]
regsel_sourceD <= regsel_sourceD_REG; // @[BankedStore.scala:176:{31,39}]
always @(posedge)
cc_banks_0 cc_banks_0 ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (_regout_T ? regout_idx : _regout_WIRE), // @[Mux.scala:50:70]
.RW0_en (_regout_T_2 | _regout_T), // @[DescribedSRAM.scala:17:26]
.RW0_clk (clock),
.RW0_wmode (regout_wen), // @[Mux.scala:50:70]
.RW0_wdata (regout_data), // @[Mux.scala:50:70]
.RW0_rdata (_cc_banks_0_RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
cc_banks_1 cc_banks_1 ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (_regout_T_5 ? regout_idx_1 : _regout_WIRE_1), // @[Mux.scala:50:70]
.RW0_en (_regout_T_7 | _regout_T_5), // @[DescribedSRAM.scala:17:26]
.RW0_clk (clock),
.RW0_wmode (regout_wen_1), // @[Mux.scala:50:70]
.RW0_wdata (regout_data_1), // @[Mux.scala:50:70]
.RW0_rdata (_cc_banks_1_RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
cc_banks_2 cc_banks_2 ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (_regout_T_10 ? regout_idx_2 : _regout_WIRE_2), // @[Mux.scala:50:70]
.RW0_en (_regout_T_12 | _regout_T_10), // @[DescribedSRAM.scala:17:26]
.RW0_clk (clock),
.RW0_wmode (regout_wen_2), // @[Mux.scala:50:70]
.RW0_wdata (regout_data_2), // @[Mux.scala:50:70]
.RW0_rdata (_cc_banks_2_RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
cc_banks_3 cc_banks_3 ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (_regout_T_15 ? regout_idx_3 : _regout_WIRE_3), // @[Mux.scala:50:70]
.RW0_en (_regout_T_17 | _regout_T_15), // @[DescribedSRAM.scala:17:26]
.RW0_clk (clock),
.RW0_wmode (regout_wen_3), // @[Mux.scala:50:70]
.RW0_wdata (regout_data_3), // @[Mux.scala:50:70]
.RW0_rdata (_cc_banks_3_RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
assign io_sinkC_adr_ready = io_sinkC_adr_ready_0; // @[BankedStore.scala:59:7]
assign io_sinkD_adr_ready = io_sinkD_adr_ready_0; // @[BankedStore.scala:59:7]
assign io_sourceC_adr_ready = io_sourceC_adr_ready_0; // @[BankedStore.scala:59:7]
assign io_sourceC_dat_data = io_sourceC_dat_data_0; // @[BankedStore.scala:59:7]
assign io_sourceD_radr_ready = io_sourceD_radr_ready_0; // @[BankedStore.scala:59:7]
assign io_sourceD_rdat_data = io_sourceD_rdat_data_0; // @[BankedStore.scala:59:7]
assign io_sourceD_wadr_ready = io_sourceD_wadr_ready_0; // @[BankedStore.scala:59:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_108 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_108( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_180 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_258 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_478
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_258( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_478 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop :
output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}}
output psd : { }
output resetctrl : { flip hartIsInReset : UInt<1>[1]}
output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}
output mem_tl : { }
output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}}
output mmio_axi4 : { }
input l2_frontend_bus_axi4 : { }
input custom_boot : UInt<1>
output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock}
output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>}
output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>}
output clock_tap : Clock
input interrupts : UInt<0>
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst ibus of ClockSinkDomain
inst sbus of SystemBus
inst pbus of PeripheryBus_pbus
inst fbus of FrontBus
inst cbus of PeripheryBus_cbus
inst mbus of MemoryBus
inst coh_wrapper of CoherenceManagerWrapper
inst tile_prci_domain of TilePRCIDomain
inst xbar of IntXbar_i1_o1_1
inst xbar_1 of IntXbar_i1_o1_2
inst xbar_2 of IntXbar_i1_o1_3
inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1
inst broadcast of BundleBridgeNexus_UInt32_1
inst clint_domain of CLINTClockSinkDomain
inst plic_domain of PLICClockSinkDomain
inst tlDM of TLDebugModule
inst debugCustomXbarOpt of DebugCustomXbar
inst nexus of BundleBridgeNexus_TraceBundle
inst nexus_1 of BundleBridgeNexus_TraceCoreInterface
inst bootrom_domain of BootROMClockSinkDomain
inst bank of ScratchpadBank
inst serial_tl_domain of SerialTL0ClockSinkDomain
inst uartClockDomainWrapper of TLUARTClockSinkDomain
inst intsink of IntSyncSyncCrossingSink_n1x1_5
inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain
inst aggregator of ClockGroupAggregator_allClocks
inst clockNamePrefixer of ClockGroupParameterModifier
inst frequencySpecifier of ClockGroupParameterModifier_1
inst clockGroupCombiner of ClockGroupCombiner
inst clockTapNode of ClockGroup_6
inst globalNoCDomain of ClockSinkDomain_1
inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8
wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}
invalidate allClockGroupsNodeOut.member.sbus_0.reset
invalidate allClockGroupsNodeOut.member.sbus_0.clock
invalidate allClockGroupsNodeOut.member.sbus_1.reset
invalidate allClockGroupsNodeOut.member.sbus_1.clock
wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset
invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock
wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset
invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock
wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset
invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock
wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset
invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock
wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset
invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock
wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}
invalidate allClockGroupsNodeIn.member.sbus_0.reset
invalidate allClockGroupsNodeIn.member.sbus_0.clock
invalidate allClockGroupsNodeIn.member.sbus_1.reset
invalidate allClockGroupsNodeIn.member.sbus_1.clock
wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset
invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock
wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset
invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock
wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset
invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock
wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset
invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock
wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset
invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock
connect allClockGroupsNodeOut, allClockGroupsNodeIn
connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn
connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1
connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2
connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3
connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4
wire tileHaltSinkNodeIn : UInt<1>[1]
invalidate tileHaltSinkNodeIn[0]
wire tileWFISinkNodeIn : UInt<1>[1]
invalidate tileWFISinkNodeIn[0]
wire tileCeaseSinkNodeIn : UInt<1>[1]
invalidate tileCeaseSinkNodeIn[0]
wire domainIn : { clock : Clock, reset : Reset}
invalidate domainIn.reset
invalidate domainIn.clock
wire debugNodesOut : { sync : UInt<1>[1]}
invalidate debugNodesOut.sync[0]
wire debugNodesIn : { sync : UInt<1>[1]}
invalidate debugNodesIn.sync[0]
connect debugNodesOut, debugNodesIn
wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}
invalidate traceCoreNodesIn.cause
invalidate traceCoreNodesIn.tval
invalidate traceCoreNodesIn.priv
invalidate traceCoreNodesIn.group[0].ilastsize
invalidate traceCoreNodesIn.group[0].itype
invalidate traceCoreNodesIn.group[0].iaddr
invalidate traceCoreNodesIn.group[0].iretire
wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[2], time : UInt<64>}
invalidate traceNodesIn.time
invalidate traceNodesIn.insns[0].tval
invalidate traceNodesIn.insns[0].cause
invalidate traceNodesIn.insns[0].interrupt
invalidate traceNodesIn.insns[0].exception
invalidate traceNodesIn.insns[0].priv
invalidate traceNodesIn.insns[0].insn
invalidate traceNodesIn.insns[0].iaddr
invalidate traceNodesIn.insns[0].valid
invalidate traceNodesIn.insns[1].tval
invalidate traceNodesIn.insns[1].cause
invalidate traceNodesIn.insns[1].interrupt
invalidate traceNodesIn.insns[1].exception
invalidate traceNodesIn.insns[1].priv
invalidate traceNodesIn.insns[1].insn
invalidate traceNodesIn.insns[1].iaddr
invalidate traceNodesIn.insns[1].valid
wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}
invalidate memAXI4NodeIn.r.bits.last
invalidate memAXI4NodeIn.r.bits.resp
invalidate memAXI4NodeIn.r.bits.data
invalidate memAXI4NodeIn.r.bits.id
invalidate memAXI4NodeIn.r.valid
invalidate memAXI4NodeIn.r.ready
invalidate memAXI4NodeIn.ar.bits.qos
invalidate memAXI4NodeIn.ar.bits.prot
invalidate memAXI4NodeIn.ar.bits.cache
invalidate memAXI4NodeIn.ar.bits.lock
invalidate memAXI4NodeIn.ar.bits.burst
invalidate memAXI4NodeIn.ar.bits.size
invalidate memAXI4NodeIn.ar.bits.len
invalidate memAXI4NodeIn.ar.bits.addr
invalidate memAXI4NodeIn.ar.bits.id
invalidate memAXI4NodeIn.ar.valid
invalidate memAXI4NodeIn.ar.ready
invalidate memAXI4NodeIn.b.bits.resp
invalidate memAXI4NodeIn.b.bits.id
invalidate memAXI4NodeIn.b.valid
invalidate memAXI4NodeIn.b.ready
invalidate memAXI4NodeIn.w.bits.last
invalidate memAXI4NodeIn.w.bits.strb
invalidate memAXI4NodeIn.w.bits.data
invalidate memAXI4NodeIn.w.valid
invalidate memAXI4NodeIn.w.ready
invalidate memAXI4NodeIn.aw.bits.qos
invalidate memAXI4NodeIn.aw.bits.prot
invalidate memAXI4NodeIn.aw.bits.cache
invalidate memAXI4NodeIn.aw.bits.lock
invalidate memAXI4NodeIn.aw.bits.burst
invalidate memAXI4NodeIn.aw.bits.size
invalidate memAXI4NodeIn.aw.bits.len
invalidate memAXI4NodeIn.aw.bits.addr
invalidate memAXI4NodeIn.aw.bits.id
invalidate memAXI4NodeIn.aw.valid
invalidate memAXI4NodeIn.aw.ready
wire bootROMResetVectorSourceNodeOut : UInt<32>
invalidate bootROMResetVectorSourceNodeOut
wire intXingOut : { sync : UInt<1>[1]}
invalidate intXingOut.sync[0]
wire intXingIn : { sync : UInt<1>[1]}
invalidate intXingIn.sync[0]
connect intXingOut, intXingIn
wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>}
invalidate ioNodeIn.rxd
invalidate ioNodeIn.txd
wire clockTapIn : { clock : Clock, reset : Reset}
invalidate clockTapIn.reset
invalidate clockTapIn.clock
connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0]
connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut
connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut
connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1
connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2
connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3
connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4
connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out
connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0
connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1
connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2
connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out
connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out
connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0
connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1
connect domainIn, cbus.auto.fixedClockNode_anon_out_2
connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3
connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4
connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0
connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out
connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out
connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out
connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out
connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out
connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out
connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_shuttle_tile_trace_source_out
connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_shuttle_tile_trace_core_source_out
connect tileHaltSinkNodeIn, xbar.auto.anon_out
connect tileWFISinkNodeIn, xbar_1.auto.anon_out
connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out
connect tile_prci_domain.auto.element_reset_domain_shuttle_tile_hartid_in, tileHartIdNexusNode.auto.out
connect tile_prci_domain.auto.element_reset_domain_shuttle_tile_reset_vector_in, broadcast.auto.out
connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out
connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out
connect debugNodesIn, tlDM.auto.dmOuter_int_out
connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out
connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out
connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out
connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0]
connect sbus.auto.coupler_from_shuttle_tile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out
connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0]
connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1]
connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0]
connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0]
connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0]
connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0]
connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0]
connect traceNodesIn, nexus.auto.out
connect traceCoreNodesIn, nexus_1.auto.out
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r
connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits
connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b
connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits
connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready
connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits
connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready
connect broadcast.auto.in, bootROMResetVectorSourceNodeOut
connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out
connect bank.auto.xbar_anon_in, mbus.auto.buffer_out
connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out
connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd
connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd
connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out
connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0]
connect intsink.auto.in.sync[0], intXingOut.sync[0]
connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out
connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out
connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0
connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1
connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2
connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3
connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4
connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5
connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0
connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1
connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2
connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3
connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4
connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5
connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out
connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out
connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out
connect clockTapIn, clockTapNode.auto.out
connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5
connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1
connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in
connect tlDM.io.tl_reset, domainIn.reset
connect tlDM.io.tl_clock, domainIn.clock
connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0]
connect tlDM.io.debug_reset, debug.reset
connect tlDM.io.debug_clock, debug.clock
connect debug.ndreset, tlDM.io.ctrl.ndreset
connect debug.dmactive, tlDM.io.ctrl.dmactive
connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck
connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0)
inst dtm of DebugTransportModuleJTAG
connect dtm.io.jtag, debug.systemjtag.jtag
connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK
connect dtm.io.jtag_reset, debug.systemjtag.reset
connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id
connect dtm.io.jtag_part_number, debug.systemjtag.part_number
connect dtm.io.jtag_version, debug.systemjtag.version
connect dtm.rf_reset, debug.systemjtag.reset
connect tlDM.io.dmi.dmi, dtm.io.dmi
connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK
connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset
connect mem_axi4.`0`, memAXI4NodeIn
connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000)
connect cbus.custom_boot, custom_boot
connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in
connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits
connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid
connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready
connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in
connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug
connect uart_0, ioNodeIn
connect clock_tap, clockTapIn.clock
regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0)
wire int_rtc_tick : UInt<1>
connect int_rtc_tick, UInt<1>(0h0)
when UInt<1>(0h1) :
node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7))
node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1))
node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1)
connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1
when int_rtc_tick_wrap_wrap :
connect int_rtc_tick_c_value, UInt<1>(0h0)
connect int_rtc_tick, int_rtc_tick_wrap_wrap
connect clint_domain.tick, int_rtc_tick
extmodule GenericDigitalInIOCell :
input pad : UInt<1>
output i : UInt<1>
input ie : UInt<1>
defname = GenericDigitalInIOCell
extmodule GenericDigitalOutIOCell :
output pad : UInt<1>
input o : UInt<1>
input oe : UInt<1>
defname = GenericDigitalOutIOCell
extmodule GenericDigitalInIOCell_1 :
input pad : UInt<1>
output i : UInt<1>
input ie : UInt<1>
defname = GenericDigitalInIOCell | module DigitalTop( // @[DigitalTop.scala:47:7]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25]
input debug_clock, // @[Periphery.scala:125:19]
input debug_reset, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19]
output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19]
input debug_systemjtag_reset, // @[Periphery.scala:125:19]
output debug_dmactive, // @[Periphery.scala:125:19]
input debug_dmactiveAck, // @[Periphery.scala:125:19]
input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21]
output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21]
output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21]
output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21]
input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21]
output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21]
output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21]
output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21]
input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21]
input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21]
input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21]
input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21]
output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21]
output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21]
output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21]
output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21]
input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21]
input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21]
input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21]
input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21]
input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21]
input custom_boot, // @[CustomBootPin.scala:73:27]
output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24]
input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24]
output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24]
output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24]
output uart_0_txd, // @[BundleBridgeSink.scala:25:19]
input uart_0_rxd, // @[BundleBridgeSink.scala:25:19]
output clock_tap // @[CanHaveClockTap.scala:23:23]
);
wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_out_insns_1_tval; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_out_insns_1_cause; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_1_interrupt; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_1_exception; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_auto_out_insns_1_priv; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_out_insns_1_insn; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_out_insns_1_iaddr; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_1_valid; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_out_insns_0_tval; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_out_insns_0_cause; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_exception; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_auto_out_insns_0_priv; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_out_insns_0_insn; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_out_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_valid; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_in_insns_1_tval; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_in_insns_1_cause; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_1_interrupt; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_1_exception; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_auto_in_insns_1_priv; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_in_insns_1_insn; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_in_insns_1_iaddr; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_1_valid; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_in_insns_0_tval; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_in_insns_0_cause; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_0_interrupt; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_0_exception; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_auto_in_insns_0_priv; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_in_insns_0_insn; // @[BundleBridgeNexus.scala:20:9]
wire [39:0] nexus_auto_in_insns_0_iaddr; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_0_valid; // @[BundleBridgeNexus.scala:20:9]
wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21]
wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21]
wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21]
wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21]
wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44]
wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44]
wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44]
wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44]
wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44]
wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38]
wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38]
wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38]
wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38]
wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28]
wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28]
wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28]
wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28]
wire [3:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28]
wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28]
wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28]
wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28]
wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26]
wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26]
wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26]
wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26]
wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26]
wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28]
wire _clint_domain_clock; // @[BusWrapper.scala:89:28]
wire _clint_domain_reset; // @[BusWrapper.scala:89:28]
wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38]
wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38]
wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38]
wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31]
wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [10:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26]
wire [3:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26]
wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26]
wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26]
wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26]
wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26]
wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26]
wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26]
wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26]
wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26]
wire [3:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26]
wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26]
wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26]
wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26]
wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26]
wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26]
wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26]
wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26]
wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7]
wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7]
wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7]
wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7]
wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7]
wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7]
wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7]
wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7]
wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7]
wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7]
wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7]
wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7]
wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7]
wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7]
wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7]
wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17]
wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17]
wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17]
wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire tileWFISinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17]
wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17]
wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17]
wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17]
wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17]
wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17]
wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17]
wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17]
wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17]
wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17]
wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17]
wire ioNodeIn_txd; // @[MixedNode.scala:551:17]
wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17]
wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7]
wire debug_ndreset; // @[DigitalTop.scala:47:7]
wire debug_dmactive_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7]
wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7]
wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7]
wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7]
wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7]
wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7]
wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7]
wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7]
wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7]
wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7]
wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7]
wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7]
wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7]
wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7]
wire uart_0_txd_0; // @[DigitalTop.scala:47:7]
wire clockTapIn_clock; // @[MixedNode.scala:551:17]
wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9]
wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9]
wire ibus_childClock; // @[LazyModuleImp.scala:155:31]
wire ibus_childReset; // @[LazyModuleImp.scala:158:31]
assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_0_valid = nexus_auto_in_insns_0_valid; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeIn_insns_0_iaddr = nexus_auto_in_insns_0_iaddr; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeIn_insns_0_insn = nexus_auto_in_insns_0_insn; // @[MixedNode.scala:551:17]
wire [2:0] nexus_nodeIn_insns_0_priv = nexus_auto_in_insns_0_priv; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_0_exception = nexus_auto_in_insns_0_exception; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_0_interrupt = nexus_auto_in_insns_0_interrupt; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeIn_insns_0_cause = nexus_auto_in_insns_0_cause; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeIn_insns_0_tval = nexus_auto_in_insns_0_tval; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_1_valid = nexus_auto_in_insns_1_valid; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeIn_insns_1_iaddr = nexus_auto_in_insns_1_iaddr; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeIn_insns_1_insn = nexus_auto_in_insns_1_insn; // @[MixedNode.scala:551:17]
wire [2:0] nexus_nodeIn_insns_1_priv = nexus_auto_in_insns_1_priv; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_1_exception = nexus_auto_in_insns_1_exception; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_1_interrupt = nexus_auto_in_insns_1_interrupt; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeIn_insns_1_cause = nexus_auto_in_insns_1_cause; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeIn_insns_1_tval = nexus_auto_in_insns_1_tval; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17]
wire [39:0] nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17]
wire traceNodesIn_insns_0_valid = nexus_auto_out_insns_0_valid; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17]
wire [39:0] traceNodesIn_insns_0_iaddr = nexus_auto_out_insns_0_iaddr; // @[MixedNode.scala:551:17]
wire [2:0] nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17]
wire [31:0] traceNodesIn_insns_0_insn = nexus_auto_out_insns_0_insn; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17]
wire [2:0] traceNodesIn_insns_0_priv = nexus_auto_out_insns_0_priv; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17]
wire traceNodesIn_insns_0_exception = nexus_auto_out_insns_0_exception; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17]
wire traceNodesIn_insns_0_interrupt = nexus_auto_out_insns_0_interrupt; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17]
wire [63:0] traceNodesIn_insns_0_cause = nexus_auto_out_insns_0_cause; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_1_valid; // @[MixedNode.scala:542:17]
wire [39:0] traceNodesIn_insns_0_tval = nexus_auto_out_insns_0_tval; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeOut_insns_1_iaddr; // @[MixedNode.scala:542:17]
wire traceNodesIn_insns_1_valid = nexus_auto_out_insns_1_valid; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeOut_insns_1_insn; // @[MixedNode.scala:542:17]
wire [39:0] traceNodesIn_insns_1_iaddr = nexus_auto_out_insns_1_iaddr; // @[MixedNode.scala:551:17]
wire [2:0] nexus_nodeOut_insns_1_priv; // @[MixedNode.scala:542:17]
wire [31:0] traceNodesIn_insns_1_insn = nexus_auto_out_insns_1_insn; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_1_exception; // @[MixedNode.scala:542:17]
wire [2:0] traceNodesIn_insns_1_priv = nexus_auto_out_insns_1_priv; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_1_interrupt; // @[MixedNode.scala:542:17]
wire traceNodesIn_insns_1_exception = nexus_auto_out_insns_1_exception; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeOut_insns_1_cause; // @[MixedNode.scala:542:17]
wire traceNodesIn_insns_1_interrupt = nexus_auto_out_insns_1_interrupt; // @[MixedNode.scala:551:17]
wire [39:0] nexus_nodeOut_insns_1_tval; // @[MixedNode.scala:542:17]
wire [63:0] traceNodesIn_insns_1_cause = nexus_auto_out_insns_1_cause; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17]
wire [39:0] traceNodesIn_insns_1_tval = nexus_auto_out_insns_1_tval; // @[MixedNode.scala:551:17]
wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17]
assign nexus_nodeOut_insns_0_valid = nexus_nodeIn_insns_0_valid; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_0_iaddr = nexus_nodeIn_insns_0_iaddr; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_0_insn = nexus_nodeIn_insns_0_insn; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_0_priv = nexus_nodeIn_insns_0_priv; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_0_exception = nexus_nodeIn_insns_0_exception; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_0_interrupt = nexus_nodeIn_insns_0_interrupt; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_0_cause = nexus_nodeIn_insns_0_cause; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_0_tval = nexus_nodeIn_insns_0_tval; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_valid = nexus_nodeIn_insns_1_valid; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_iaddr = nexus_nodeIn_insns_1_iaddr; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_insn = nexus_nodeIn_insns_1_insn; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_priv = nexus_nodeIn_insns_1_priv; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_exception = nexus_nodeIn_insns_1_exception; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_interrupt = nexus_nodeIn_insns_1_interrupt; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_cause = nexus_nodeIn_insns_1_cause; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_insns_1_tval = nexus_nodeIn_insns_1_tval; // @[MixedNode.scala:542:17, :551:17]
assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17]
assign nexus_auto_out_insns_0_valid = nexus_nodeOut_insns_0_valid; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_0_iaddr = nexus_nodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_0_insn = nexus_nodeOut_insns_0_insn; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_0_priv = nexus_nodeOut_insns_0_priv; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_0_exception = nexus_nodeOut_insns_0_exception; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_0_interrupt = nexus_nodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_0_cause = nexus_nodeOut_insns_0_cause; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_0_tval = nexus_nodeOut_insns_0_tval; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_valid = nexus_nodeOut_insns_1_valid; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_iaddr = nexus_nodeOut_insns_1_iaddr; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_insn = nexus_nodeOut_insns_1_insn; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_priv = nexus_nodeOut_insns_1_priv; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_exception = nexus_nodeOut_insns_1_exception; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_interrupt = nexus_nodeOut_insns_1_interrupt; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_cause = nexus_nodeOut_insns_1_cause; // @[MixedNode.scala:542:17]
assign nexus_auto_out_insns_1_tval = nexus_nodeOut_insns_1_tval; // @[MixedNode.scala:542:17]
assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17]
wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17]
assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17]
assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17]
assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17]
assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
wire domainIn_clock; // @[MixedNode.scala:551:17]
wire domainIn_reset; // @[MixedNode.scala:551:17]
wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17]
wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17]
assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17]
assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17]
assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17]
assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17]
assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17]
assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17]
reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40]
wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24]
wire int_rtc_tick; // @[Counter.scala:117:24]
assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24]
assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24]
wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24]
wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24]
always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28]
if (_clint_domain_reset) // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40]
else // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
always @(posedge)
IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27]
.auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_0 (ibus_auto_int_bus_anon_out_0)
); // @[InterruptBus.scala:19:27]
SystemBus sbus ( // @[SystemBus.scala:31:26]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_ready (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_ready),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_valid (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_valid),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_param (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_param),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_address (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_address),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_ready (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_ready),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_valid (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_valid),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_opcode (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_opcode),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_param (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_param),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_size (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_size),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_source (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_source),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_sink (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_sink),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_denied (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_denied),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_data (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_data),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_corrupt),
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), // @[HasTiles.scala:163:38]
.auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), // @[HasTiles.scala:163:38]
.auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data),
.auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt),
.auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready),
.auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data),
.auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt),
.auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready),
.auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid),
.auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink),
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready),
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock),
.auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset),
.auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock),
.auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset),
.auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock),
.auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset),
.auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock),
.auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset)
); // @[SystemBus.scala:31:26]
PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26]
.auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt),
.auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready),
.auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44]
.auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock),
.auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset),
.auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17]
.auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt)
); // @[PeripheryBus.scala:37:26]
FrontBus fbus ( // @[FrontBus.scala:23:26]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt),
.auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready),
.auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt),
.auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock),
.auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset),
.auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17]
.auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid),
.auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode),
.auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param),
.auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size),
.auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source),
.auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address),
.auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask),
.auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data),
.auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt),
.auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready),
.auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26]
); // @[FrontBus.scala:23:26]
PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26]
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt),
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready),
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready),
.auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready),
.auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26]
.auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready),
.auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready),
.auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data),
.auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt),
.auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready),
.auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31]
.auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0),
.auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0),
.auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock),
.auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset),
.auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock),
.auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset),
.auto_fixedClockNode_anon_out_2_clock (domainIn_clock),
.auto_fixedClockNode_anon_out_2_reset (domainIn_reset),
.auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock),
.auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset),
.auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock),
.auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset),
.auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17]
.auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt),
.custom_boot (custom_boot)
); // @[PeripheryBus.scala:37:26]
MemoryBus mbus ( // @[MemoryBus.scala:30:26]
.auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28]
.auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt),
.auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready),
.auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28]
.auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready),
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17]
.auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17]
.auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0),
.auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0),
.auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock),
.auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset),
.auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17]
.auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31]
.auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt)
); // @[MemoryBus.scala:30:26]
CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31]
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26]
.auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26]
.auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready),
.auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid),
.auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param),
.auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address),
.auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready),
.auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid),
.auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode),
.auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param),
.auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size),
.auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source),
.auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink),
.auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied),
.auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data),
.auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt),
.auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26]
.auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26]
.auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready),
.auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid),
.auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode),
.auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size),
.auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source),
.auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data),
.auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26]
.auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26]
); // @[BankedCoherenceParams.scala:56:31]
TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38]
.auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17]
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_valid (nexus_auto_in_insns_0_valid),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_iaddr (nexus_auto_in_insns_0_iaddr),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_insn (nexus_auto_in_insns_0_insn),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_priv (nexus_auto_in_insns_0_priv),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_exception (nexus_auto_in_insns_0_exception),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_interrupt (nexus_auto_in_insns_0_interrupt),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_cause (nexus_auto_in_insns_0_cause),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_0_tval (nexus_auto_in_insns_0_tval),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_valid (nexus_auto_in_insns_1_valid),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_iaddr (nexus_auto_in_insns_1_iaddr),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_insn (nexus_auto_in_insns_1_insn),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_priv (nexus_auto_in_insns_1_priv),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_exception (nexus_auto_in_insns_1_exception),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_interrupt (nexus_auto_in_insns_1_interrupt),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_cause (nexus_auto_in_insns_1_cause),
.auto_element_reset_domain_shuttle_tile_trace_source_out_insns_1_tval (nexus_auto_in_insns_1_tval),
.auto_element_reset_domain_shuttle_tile_trace_source_out_time (nexus_auto_in_time),
.auto_element_reset_domain_shuttle_tile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39]
.auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28]
.auto_tl_master_clock_xing_out_a_ready (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_a_ready), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid),
.auto_tl_master_clock_xing_out_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode),
.auto_tl_master_clock_xing_out_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param),
.auto_tl_master_clock_xing_out_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size),
.auto_tl_master_clock_xing_out_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source),
.auto_tl_master_clock_xing_out_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address),
.auto_tl_master_clock_xing_out_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask),
.auto_tl_master_clock_xing_out_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data),
.auto_tl_master_clock_xing_out_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt),
.auto_tl_master_clock_xing_out_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready),
.auto_tl_master_clock_xing_out_b_valid (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_valid), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_b_bits_param (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_param), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_b_bits_address (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_b_bits_address), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_c_ready (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_c_ready), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid),
.auto_tl_master_clock_xing_out_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode),
.auto_tl_master_clock_xing_out_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param),
.auto_tl_master_clock_xing_out_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size),
.auto_tl_master_clock_xing_out_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source),
.auto_tl_master_clock_xing_out_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address),
.auto_tl_master_clock_xing_out_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data),
.auto_tl_master_clock_xing_out_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt),
.auto_tl_master_clock_xing_out_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready),
.auto_tl_master_clock_xing_out_d_valid (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_valid), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_opcode (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_param (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_param), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_size (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_size), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_source (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_source), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_sink (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_sink), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_denied (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_denied), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_data (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_data), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_shuttle_tile_tl_master_clock_xing_in_d_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid),
.auto_tl_master_clock_xing_out_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink),
.auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26]
.auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26]
); // @[HasTiles.scala:163:38]
IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26]
IntXbar_i1_o1_2 xbar_1 (); // @[Xbar.scala:52:26]
IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26]
BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39]
.auto_out (_tileHartIdNexusNode_auto_out)
); // @[HasTiles.scala:75:39]
CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28]
.auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready),
.auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid),
.auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode),
.auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size),
.auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source),
.auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data),
.auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0),
.auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26]
.tick (int_rtc_tick), // @[Counter.scala:117:24]
.clock (_clint_domain_clock),
.reset (_clint_domain_reset)
); // @[BusWrapper.scala:89:28]
PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28]
.auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9]
.auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready),
.auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid),
.auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode),
.auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size),
.auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source),
.auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data),
.auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0),
.auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
TLDebugModule tlDM ( // @[Periphery.scala:88:26]
.auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data),
.auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready),
.auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready),
.auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid),
.auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode),
.auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size),
.auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source),
.auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data),
.auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0),
.io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7]
.io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7]
.io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17]
.io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17]
.io_ctrl_ndreset (debug_ndreset),
.io_ctrl_dmactive (debug_dmactive_0),
.io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7]
.io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready),
.io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21]
.io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21]
.io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid),
.io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data),
.io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp),
.io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7]
.io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7]
); // @[Periphery.scala:88:26]
DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75]
BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28]
.auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready),
.auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid),
.auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size),
.auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source),
.auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
ScratchpadBank bank ( // @[Scratchpad.scala:65:28]
.auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready),
.auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26]
.auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid),
.auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode),
.auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param),
.auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size),
.auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source),
.auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink),
.auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied),
.auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data),
.auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt),
.auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26]
.auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26]
); // @[Scratchpad.scala:65:28]
SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38]
.auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid),
.auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode),
.auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param),
.auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size),
.auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source),
.auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address),
.auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask),
.auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data),
.auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt),
.auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready),
.auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26]
.auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26]
.serial_tl_0_in_ready (serial_tl_0_in_ready_0),
.serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_out_valid (serial_tl_0_out_valid_0),
.serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0),
.serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy),
.serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy)
); // @[PeripheryTLSerial.scala:116:38]
TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44]
.auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0),
.auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready),
.auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid),
.auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode),
.auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size),
.auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source),
.auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data),
.auto_uart_0_io_out_txd (ioNodeIn_txd),
.auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17]
.auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26]
); // @[UART.scala:270:44]
IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (ibus_auto_int_bus_anon_in_0)
); // @[Crossing.scala:109:29]
ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28]
.auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7]
.auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7]
.auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock),
.auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset),
.auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready),
.auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid),
.auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode),
.auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size),
.auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source),
.auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30]
.auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock),
.auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset),
.auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock),
.auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset),
.auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock),
.auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset),
.auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock),
.auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset),
.auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock),
.auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset),
.auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock),
.auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset),
.auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock),
.auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset)
); // @[HasChipyardPRCI.scala:51:30]
ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15]
.auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28]
.auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28]
.auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock),
.auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset),
.auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock),
.auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset),
.auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset)
); // @[ClockGroupCombiner.scala:19:15]
ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40]
.auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26]
.auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26]
); // @[GlobalNoC.scala:45:40]
BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44]
DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21]
.io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7]
.io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26]
.io_dmi_req_valid (_dtm_io_dmi_req_valid),
.io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr),
.io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data),
.io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op),
.io_dmi_resp_ready (_dtm_io_dmi_resp_ready),
.io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26]
.io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26]
.io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26]
.io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7]
.io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7]
.io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0),
.io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven),
.rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7]
); // @[Periphery.scala:166:21]
assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7]
assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7]
assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7]
assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7]
assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain :
output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_spike_tile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_spike_tile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<58>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<58>}[1], time : UInt<64>}, flip element_reset_domain_spike_tile_reset_vector_in : UInt<32>, flip element_reset_domain_spike_tile_hartid_in : UInt<1>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst element_reset_domain of HierarchicalElementResetDomain
inst clockNode of FixedClockBroadcast_1_1
inst buffer of TLBuffer_a32d64s2k3z4c_2
connect buffer.clock, childClock
connect buffer.reset, childReset
inst buffer_1 of TLBuffer_2
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst intsink of IntSyncAsyncCrossingSink_n1x1
connect intsink.clock, childClock
connect intsink.reset, childReset
inst intsink_1 of IntSyncSyncCrossingSink_n1x2
inst intsink_2 of IntSyncSyncCrossingSink_n1x1
inst intsink_3 of IntSyncSyncCrossingSink_n1x1_1
inst intsink_4 of IntSyncSyncCrossingSink_n1x1_2
inst intsource of IntSyncCrossingSource_n1x1
connect intsource.clock, childClock
connect intsource.reset, childReset
inst intsink_5 of IntSyncSyncCrossingSink_n1x1_3
inst intsource_1 of IntSyncCrossingSource_n1x1_1
connect intsource_1.clock, childClock
connect intsource_1.reset, childReset
inst intsink_6 of IntSyncSyncCrossingSink_n1x1_4
inst intsource_2 of IntSyncCrossingSource_n1x1_2
connect intsource_2.clock, childClock
connect intsource_2.reset, childReset
wire tapClockNodeOut : { clock : Clock, reset : Reset}
invalidate tapClockNodeOut.reset
invalidate tapClockNodeOut.clock
wire tapClockNodeIn : { clock : Clock, reset : Reset}
invalidate tapClockNodeIn.reset
invalidate tapClockNodeIn.clock
connect tapClockNodeOut, tapClockNodeIn
wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlMasterClockXingOut.e.bits.sink
invalidate tlMasterClockXingOut.e.valid
invalidate tlMasterClockXingOut.e.ready
invalidate tlMasterClockXingOut.d.bits.corrupt
invalidate tlMasterClockXingOut.d.bits.data
invalidate tlMasterClockXingOut.d.bits.denied
invalidate tlMasterClockXingOut.d.bits.sink
invalidate tlMasterClockXingOut.d.bits.source
invalidate tlMasterClockXingOut.d.bits.size
invalidate tlMasterClockXingOut.d.bits.param
invalidate tlMasterClockXingOut.d.bits.opcode
invalidate tlMasterClockXingOut.d.valid
invalidate tlMasterClockXingOut.d.ready
invalidate tlMasterClockXingOut.c.bits.corrupt
invalidate tlMasterClockXingOut.c.bits.data
invalidate tlMasterClockXingOut.c.bits.address
invalidate tlMasterClockXingOut.c.bits.source
invalidate tlMasterClockXingOut.c.bits.size
invalidate tlMasterClockXingOut.c.bits.param
invalidate tlMasterClockXingOut.c.bits.opcode
invalidate tlMasterClockXingOut.c.valid
invalidate tlMasterClockXingOut.c.ready
invalidate tlMasterClockXingOut.b.bits.corrupt
invalidate tlMasterClockXingOut.b.bits.data
invalidate tlMasterClockXingOut.b.bits.mask
invalidate tlMasterClockXingOut.b.bits.address
invalidate tlMasterClockXingOut.b.bits.source
invalidate tlMasterClockXingOut.b.bits.size
invalidate tlMasterClockXingOut.b.bits.param
invalidate tlMasterClockXingOut.b.bits.opcode
invalidate tlMasterClockXingOut.b.valid
invalidate tlMasterClockXingOut.b.ready
invalidate tlMasterClockXingOut.a.bits.corrupt
invalidate tlMasterClockXingOut.a.bits.data
invalidate tlMasterClockXingOut.a.bits.mask
invalidate tlMasterClockXingOut.a.bits.address
invalidate tlMasterClockXingOut.a.bits.source
invalidate tlMasterClockXingOut.a.bits.size
invalidate tlMasterClockXingOut.a.bits.param
invalidate tlMasterClockXingOut.a.bits.opcode
invalidate tlMasterClockXingOut.a.valid
invalidate tlMasterClockXingOut.a.ready
wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate tlMasterClockXingIn.e.bits.sink
invalidate tlMasterClockXingIn.e.valid
invalidate tlMasterClockXingIn.e.ready
invalidate tlMasterClockXingIn.d.bits.corrupt
invalidate tlMasterClockXingIn.d.bits.data
invalidate tlMasterClockXingIn.d.bits.denied
invalidate tlMasterClockXingIn.d.bits.sink
invalidate tlMasterClockXingIn.d.bits.source
invalidate tlMasterClockXingIn.d.bits.size
invalidate tlMasterClockXingIn.d.bits.param
invalidate tlMasterClockXingIn.d.bits.opcode
invalidate tlMasterClockXingIn.d.valid
invalidate tlMasterClockXingIn.d.ready
invalidate tlMasterClockXingIn.c.bits.corrupt
invalidate tlMasterClockXingIn.c.bits.data
invalidate tlMasterClockXingIn.c.bits.address
invalidate tlMasterClockXingIn.c.bits.source
invalidate tlMasterClockXingIn.c.bits.size
invalidate tlMasterClockXingIn.c.bits.param
invalidate tlMasterClockXingIn.c.bits.opcode
invalidate tlMasterClockXingIn.c.valid
invalidate tlMasterClockXingIn.c.ready
invalidate tlMasterClockXingIn.b.bits.corrupt
invalidate tlMasterClockXingIn.b.bits.data
invalidate tlMasterClockXingIn.b.bits.mask
invalidate tlMasterClockXingIn.b.bits.address
invalidate tlMasterClockXingIn.b.bits.source
invalidate tlMasterClockXingIn.b.bits.size
invalidate tlMasterClockXingIn.b.bits.param
invalidate tlMasterClockXingIn.b.bits.opcode
invalidate tlMasterClockXingIn.b.valid
invalidate tlMasterClockXingIn.b.ready
invalidate tlMasterClockXingIn.a.bits.corrupt
invalidate tlMasterClockXingIn.a.bits.data
invalidate tlMasterClockXingIn.a.bits.mask
invalidate tlMasterClockXingIn.a.bits.address
invalidate tlMasterClockXingIn.a.bits.source
invalidate tlMasterClockXingIn.a.bits.size
invalidate tlMasterClockXingIn.a.bits.param
invalidate tlMasterClockXingIn.a.bits.opcode
invalidate tlMasterClockXingIn.a.valid
invalidate tlMasterClockXingIn.a.ready
connect tlMasterClockXingOut, tlMasterClockXingIn
wire intInClockXingOut : { sync : UInt<1>[2]}
invalidate intInClockXingOut.sync[0]
invalidate intInClockXingOut.sync[1]
wire intInClockXingIn : { sync : UInt<1>[2]}
invalidate intInClockXingIn.sync[0]
invalidate intInClockXingIn.sync[1]
connect intInClockXingOut, intInClockXingIn
wire intInClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_1.sync[0]
wire intInClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_1.sync[0]
connect intInClockXingOut_1, intInClockXingIn_1
wire intInClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_2.sync[0]
wire intInClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_2.sync[0]
connect intInClockXingOut_2, intInClockXingIn_2
wire intOutClockXingOut : { sync : UInt<1>[1]}
invalidate intOutClockXingOut.sync[0]
wire intOutClockXingIn : { sync : UInt<1>[1]}
invalidate intOutClockXingIn.sync[0]
connect intOutClockXingOut, intOutClockXingIn
wire intOutClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_1.sync[0]
wire intOutClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_1.sync[0]
connect intOutClockXingOut_1, intOutClockXingIn_1
wire intOutClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_2.sync[0]
wire intOutClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_2.sync[0]
connect intOutClockXingOut_2, intOutClockXingIn_2
wire intOutClockXingOut_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_3.sync[0]
wire intOutClockXingIn_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_3.sync[0]
connect intOutClockXingOut_3, intOutClockXingIn_3
wire intOutClockXingOut_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_4.sync[0]
wire intOutClockXingIn_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_4.sync[0]
connect intOutClockXingOut_4, intOutClockXingIn_4
wire intOutClockXingOut_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_5.sync[0]
wire intOutClockXingIn_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_5.sync[0]
connect intOutClockXingOut_5, intOutClockXingIn_5
connect clockNode.auto.anon_in, tapClockNodeOut
connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out
connect intsource.auto.in[0], element_reset_domain.auto.spike_tile_halt_out[0]
connect intsource_2.auto.in[0], element_reset_domain.auto.spike_tile_cease_out[0]
connect intsource_1.auto.in[0], element_reset_domain.auto.spike_tile_wfi_out[0]
connect buffer.auto.in, element_reset_domain.auto.spike_tile_buffer_out
connect tlMasterClockXingIn.e.bits, buffer.auto.out.e.bits
connect tlMasterClockXingIn.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, tlMasterClockXingIn.e.ready
connect buffer.auto.out.d, tlMasterClockXingIn.d
connect tlMasterClockXingIn.c.bits, buffer.auto.out.c.bits
connect tlMasterClockXingIn.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, tlMasterClockXingIn.c.ready
connect buffer.auto.out.b, tlMasterClockXingIn.b
connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits
connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready
connect element_reset_domain.auto.spike_tile_int_local_in_0[0], intsink.auto.out[0]
connect element_reset_domain.auto.spike_tile_int_local_in_1[0], intsink_1.auto.out[0]
connect element_reset_domain.auto.spike_tile_int_local_in_1[1], intsink_1.auto.out[1]
connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0]
connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1]
connect element_reset_domain.auto.spike_tile_int_local_in_2[0], intsink_2.auto.out[0]
connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0]
connect element_reset_domain.auto.spike_tile_int_local_in_3[0], intsink_3.auto.out[0]
connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0]
connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0]
connect intOutClockXingIn, intOutClockXingOut_1
connect intOutClockXingIn_1, intsource.auto.out
connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0]
connect intOutClockXingIn_2, intOutClockXingOut_3
connect intOutClockXingIn_3, intsource_1.auto.out
connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0]
connect intOutClockXingIn_4, intOutClockXingOut_5
connect intOutClockXingIn_5, intsource_2.auto.out
connect tapClockNodeIn, auto.tap_clock_in
connect auto.tl_master_clock_xing_out, tlMasterClockXingOut
connect intInClockXingIn, auto.int_in_clock_xing_in_0
connect intInClockXingIn_1, auto.int_in_clock_xing_in_1
connect intInClockXingIn_2, auto.int_in_clock_xing_in_2
connect element_reset_domain.auto.spike_tile_hartid_in, auto.element_reset_domain_spike_tile_hartid_in
connect element_reset_domain.auto.spike_tile_reset_vector_in, auto.element_reset_domain_spike_tile_reset_vector_in
connect auto.element_reset_domain_spike_tile_trace_source_out.time, element_reset_domain.auto.spike_tile_trace_source_out.time
connect auto.element_reset_domain_spike_tile_trace_source_out.insns, element_reset_domain.auto.spike_tile_trace_source_out.insns
connect auto.element_reset_domain_spike_tile_trace_core_source_out.cause, element_reset_domain.auto.spike_tile_trace_core_source_out.cause
connect auto.element_reset_domain_spike_tile_trace_core_source_out.tval, element_reset_domain.auto.spike_tile_trace_core_source_out.tval
connect auto.element_reset_domain_spike_tile_trace_core_source_out.priv, element_reset_domain.auto.spike_tile_trace_core_source_out.priv
connect auto.element_reset_domain_spike_tile_trace_core_source_out.group, element_reset_domain.auto.spike_tile_trace_core_source_out.group
connect intsink.auto.in.sync[0], auto.intsink_in.sync[0]
connect auto.intsink_out_0, intsink_4.auto.out
connect auto.intsink_out_1, intsink_5.auto.out
connect auto.intsink_out_2, intsink_6.auto.out
connect childClock, tapClockNodeIn.clock
connect childReset, tapClockNodeIn.reset
connect clock, tapClockNodeIn.clock
connect reset, tapClockNodeIn.reset | module TilePRCIDomain( // @[ClockDomain.scala:14:9]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_element_reset_domain_spike_tile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_spike_tile_hartid_in_0 = auto_element_reset_domain_spike_tile_hartid_in; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_spike_tile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_spike_tile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_spike_tile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_spike_tile_trace_source_out_insns_0_insn = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_trace_source_out_insns_0_insn = 32'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_spike_tile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_spike_tile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_spike_tile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_spike_tile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [57:0] auto_element_reset_domain_spike_tile_trace_source_out_insns_0_iaddr = 58'h0; // @[ClockDomain.scala:14:9]
wire [57:0] auto_element_reset_domain_spike_tile_trace_source_out_insns_0_tval = 58'h0; // @[ClockDomain.scala:14:9]
wire [57:0] element_reset_domain_auto_spike_tile_trace_source_out_insns_0_iaddr = 58'h0; // @[ClockDomain.scala:14:9]
wire [57:0] element_reset_domain_auto_spike_tile_trace_source_out_insns_0_tval = 58'h0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_spike_tile_trace_source_out_insns_0_priv = 3'h0; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_trace_source_out_insns_0_priv = 3'h0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_spike_tile_trace_source_out_insns_0_cause = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_spike_tile_trace_source_out_time = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_spike_tile_trace_source_out_insns_0_cause = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_spike_tile_trace_source_out_time = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [31:0] auto_element_reset_domain_spike_tile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [3:0] auto_tl_master_clock_xing_out_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [1:0] auto_tl_master_clock_xing_out_b_bits_source = 2'h1; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_source = 2'h1; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingIn_b_bits_source = 2'h1; // @[MixedNode.scala:551:17]
wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] tlMasterClockXingIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire auto_tl_master_clock_xing_out_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire tlMasterClockXingIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_1_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_spike_tile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_spike_tile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_spike_tile_trace_source_out_insns_0_valid = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_spike_tile_trace_source_out_insns_0_exception = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_spike_tile_trace_source_out_insns_0_interrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire element_reset_domain_auto_spike_tile_wfi_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_trace_source_out_insns_0_valid = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_trace_source_out_insns_0_exception = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_trace_source_out_insns_0_interrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_2_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_2_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_3_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_3_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire element_reset_domain_auto_spike_tile_hartid_in = auto_element_reset_domain_spike_tile_hartid_in_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_spike_tile_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_spike_tile_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_spike_tile_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_spike_tile_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_a_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_spike_tile_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_spike_tile_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_spike_tile_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] element_reset_domain_auto_spike_tile_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_spike_tile_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_b_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_spike_tile_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_spike_tile_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_spike_tile_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_spike_tile_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_c_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_spike_tile_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_spike_tile_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_spike_tile_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_spike_tile_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_d_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_spike_tile_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_e_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_buffer_out_e_valid; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_int_local_in_3_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_int_local_in_2_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_int_local_in_1_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_int_local_in_1_1; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_spike_tile_int_local_in_0_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31]
wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31]
assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17]
wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9]
assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9]
assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
SpikeTile element_reset_domain_spike_tile ( // @[HasTiles.scala:164:59]
.clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31]
.reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_out_a_ready (element_reset_domain_auto_spike_tile_buffer_out_a_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_a_valid (element_reset_domain_auto_spike_tile_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param (element_reset_domain_auto_spike_tile_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size (element_reset_domain_auto_spike_tile_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source (element_reset_domain_auto_spike_tile_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address (element_reset_domain_auto_spike_tile_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask (element_reset_domain_auto_spike_tile_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data (element_reset_domain_auto_spike_tile_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_a_bits_corrupt),
.auto_buffer_out_b_ready (element_reset_domain_auto_spike_tile_buffer_out_b_ready),
.auto_buffer_out_b_valid (element_reset_domain_auto_spike_tile_buffer_out_b_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_param (element_reset_domain_auto_spike_tile_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_size (element_reset_domain_auto_spike_tile_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_source (element_reset_domain_auto_spike_tile_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_address (element_reset_domain_auto_spike_tile_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_mask (element_reset_domain_auto_spike_tile_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_data (element_reset_domain_auto_spike_tile_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_ready (element_reset_domain_auto_spike_tile_buffer_out_c_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_c_valid (element_reset_domain_auto_spike_tile_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param (element_reset_domain_auto_spike_tile_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size (element_reset_domain_auto_spike_tile_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source (element_reset_domain_auto_spike_tile_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address (element_reset_domain_auto_spike_tile_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data (element_reset_domain_auto_spike_tile_buffer_out_c_bits_data),
.auto_buffer_out_c_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_c_bits_corrupt),
.auto_buffer_out_d_ready (element_reset_domain_auto_spike_tile_buffer_out_d_ready),
.auto_buffer_out_d_valid (element_reset_domain_auto_spike_tile_buffer_out_d_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_param (element_reset_domain_auto_spike_tile_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_size (element_reset_domain_auto_spike_tile_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_source (element_reset_domain_auto_spike_tile_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_sink (element_reset_domain_auto_spike_tile_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_denied (element_reset_domain_auto_spike_tile_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_data (element_reset_domain_auto_spike_tile_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_ready (element_reset_domain_auto_spike_tile_buffer_out_e_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_e_valid (element_reset_domain_auto_spike_tile_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink (element_reset_domain_auto_spike_tile_buffer_out_e_bits_sink),
.auto_int_local_in_3_0 (element_reset_domain_auto_spike_tile_int_local_in_3_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_2_0 (element_reset_domain_auto_spike_tile_int_local_in_2_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_0 (element_reset_domain_auto_spike_tile_int_local_in_1_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_1 (element_reset_domain_auto_spike_tile_int_local_in_1_1), // @[ClockDomain.scala:14:9]
.auto_int_local_in_0_0 (element_reset_domain_auto_spike_tile_int_local_in_0_0), // @[ClockDomain.scala:14:9]
.auto_hartid_in (element_reset_domain_auto_spike_tile_hartid_in) // @[ClockDomain.scala:14:9]
); // @[HasTiles.scala:164:59]
TLBuffer_a32d64s2k3z4c_2 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (element_reset_domain_auto_spike_tile_buffer_out_a_ready),
.auto_in_a_valid (element_reset_domain_auto_spike_tile_buffer_out_a_valid), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_param (element_reset_domain_auto_spike_tile_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_size (element_reset_domain_auto_spike_tile_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_source (element_reset_domain_auto_spike_tile_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_address (element_reset_domain_auto_spike_tile_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_mask (element_reset_domain_auto_spike_tile_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_data (element_reset_domain_auto_spike_tile_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_a_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_a_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_in_b_ready (element_reset_domain_auto_spike_tile_buffer_out_b_ready), // @[ClockDomain.scala:14:9]
.auto_in_b_valid (element_reset_domain_auto_spike_tile_buffer_out_b_valid),
.auto_in_b_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_b_bits_opcode),
.auto_in_b_bits_param (element_reset_domain_auto_spike_tile_buffer_out_b_bits_param),
.auto_in_b_bits_size (element_reset_domain_auto_spike_tile_buffer_out_b_bits_size),
.auto_in_b_bits_source (element_reset_domain_auto_spike_tile_buffer_out_b_bits_source),
.auto_in_b_bits_address (element_reset_domain_auto_spike_tile_buffer_out_b_bits_address),
.auto_in_b_bits_mask (element_reset_domain_auto_spike_tile_buffer_out_b_bits_mask),
.auto_in_b_bits_data (element_reset_domain_auto_spike_tile_buffer_out_b_bits_data),
.auto_in_b_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_b_bits_corrupt),
.auto_in_c_ready (element_reset_domain_auto_spike_tile_buffer_out_c_ready),
.auto_in_c_valid (element_reset_domain_auto_spike_tile_buffer_out_c_valid), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_param (element_reset_domain_auto_spike_tile_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_size (element_reset_domain_auto_spike_tile_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_source (element_reset_domain_auto_spike_tile_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_address (element_reset_domain_auto_spike_tile_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_data (element_reset_domain_auto_spike_tile_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_c_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_c_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_in_d_ready (element_reset_domain_auto_spike_tile_buffer_out_d_ready), // @[ClockDomain.scala:14:9]
.auto_in_d_valid (element_reset_domain_auto_spike_tile_buffer_out_d_valid),
.auto_in_d_bits_opcode (element_reset_domain_auto_spike_tile_buffer_out_d_bits_opcode),
.auto_in_d_bits_param (element_reset_domain_auto_spike_tile_buffer_out_d_bits_param),
.auto_in_d_bits_size (element_reset_domain_auto_spike_tile_buffer_out_d_bits_size),
.auto_in_d_bits_source (element_reset_domain_auto_spike_tile_buffer_out_d_bits_source),
.auto_in_d_bits_sink (element_reset_domain_auto_spike_tile_buffer_out_d_bits_sink),
.auto_in_d_bits_denied (element_reset_domain_auto_spike_tile_buffer_out_d_bits_denied),
.auto_in_d_bits_data (element_reset_domain_auto_spike_tile_buffer_out_d_bits_data),
.auto_in_d_bits_corrupt (element_reset_domain_auto_spike_tile_buffer_out_d_bits_corrupt),
.auto_in_e_ready (element_reset_domain_auto_spike_tile_buffer_out_e_ready),
.auto_in_e_valid (element_reset_domain_auto_spike_tile_buffer_out_e_valid), // @[ClockDomain.scala:14:9]
.auto_in_e_bits_sink (element_reset_domain_auto_spike_tile_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9]
.auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlMasterClockXingIn_a_valid),
.auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode),
.auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param),
.auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size),
.auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source),
.auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address),
.auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask),
.auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data),
.auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt),
.auto_out_b_ready (tlMasterClockXingIn_b_ready),
.auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17]
.auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17]
.auto_out_c_valid (tlMasterClockXingIn_c_valid),
.auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode),
.auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param),
.auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size),
.auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source),
.auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address),
.auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data),
.auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt),
.auto_out_d_ready (tlMasterClockXingIn_d_ready),
.auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_e_valid (tlMasterClockXingIn_e_valid),
.auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink)
); // @[Buffer.scala:75:28]
TLBuffer_2 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9]
.auto_out_0 (element_reset_domain_auto_spike_tile_int_local_in_0_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_spike_tile_int_local_in_1_0),
.auto_out_1 (element_reset_domain_auto_spike_tile_int_local_in_1_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_spike_tile_int_local_in_2_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_1 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_spike_tile_int_local_in_3_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_2 intsink_4 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_3 intsink_5 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_1 intsource_1 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_4 intsink_6 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_2 intsource_2 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_66 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = or(_T_667, _T_672)
node _T_709 = or(_T_708, _T_677)
node _T_710 = or(_T_709, _T_682)
node _T_711 = or(_T_710, _T_687)
node _T_712 = or(_T_711, _T_692)
node _T_713 = or(_T_712, _T_697)
node _T_714 = or(_T_713, _T_702)
node _T_715 = or(_T_714, _T_707)
node _T_716 = and(_T_662, _T_715)
node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_716)
node _T_725 = or(_T_724, _T_723)
node _T_726 = and(_T_658, _T_725)
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_726, UInt<1>(0h1), "") : assert_36
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_736, UInt<1>(0h1), "") : assert_39
node _T_740 = eq(io.in.a.bits.mask, mask)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_740, UInt<1>(0h1), "") : assert_40
node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_753 = and(_T_751, _T_752)
node _T_754 = or(UInt<1>(0h0), _T_753)
node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_759, _T_764)
node _T_801 = or(_T_800, _T_769)
node _T_802 = or(_T_801, _T_774)
node _T_803 = or(_T_802, _T_779)
node _T_804 = or(_T_803, _T_784)
node _T_805 = or(_T_804, _T_789)
node _T_806 = or(_T_805, _T_794)
node _T_807 = or(_T_806, _T_799)
node _T_808 = and(_T_754, _T_807)
node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = and(_T_809, _T_814)
node _T_816 = or(UInt<1>(0h0), _T_808)
node _T_817 = or(_T_816, _T_815)
node _T_818 = and(_T_750, _T_817)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_818, UInt<1>(0h1), "") : assert_41
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(is_aligned, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_828, UInt<1>(0h1), "") : assert_44
node _T_832 = eq(io.in.a.bits.mask, mask)
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_832, UInt<1>(0h1), "") : assert_45
node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_836 :
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = or(_T_858, _T_863)
node _T_890 = or(_T_889, _T_868)
node _T_891 = or(_T_890, _T_873)
node _T_892 = or(_T_891, _T_878)
node _T_893 = or(_T_892, _T_883)
node _T_894 = or(_T_893, _T_888)
node _T_895 = and(_T_853, _T_894)
node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_898 = and(_T_896, _T_897)
node _T_899 = or(UInt<1>(0h0), _T_898)
node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_901 = cvt(_T_900)
node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000)))
node _T_903 = asSInt(_T_902)
node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0)))
node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_906 = cvt(_T_905)
node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000)))
node _T_908 = asSInt(_T_907)
node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0)))
node _T_910 = or(_T_904, _T_909)
node _T_911 = and(_T_899, _T_910)
node _T_912 = or(UInt<1>(0h0), _T_852)
node _T_913 = or(_T_912, _T_895)
node _T_914 = or(_T_913, _T_911)
node _T_915 = and(_T_842, _T_914)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_915, UInt<1>(0h1), "") : assert_46
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(is_aligned, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_925, UInt<1>(0h1), "") : assert_49
node _T_929 = eq(io.in.a.bits.mask, mask)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_929, UInt<1>(0h1), "") : assert_50
node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_933, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_937, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_941 :
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_945, UInt<1>(0h1), "") : assert_54
node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_949, UInt<1>(0h1), "") : assert_55
node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_953, UInt<1>(0h1), "") : assert_56
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_957, UInt<1>(0h1), "") : assert_57
node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_961 :
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(sink_ok, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_968, UInt<1>(0h1), "") : assert_60
node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_972, UInt<1>(0h1), "") : assert_61
node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_976, UInt<1>(0h1), "") : assert_62
node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_980, UInt<1>(0h1), "") : assert_63
node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_985 = or(UInt<1>(0h1), _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_985, UInt<1>(0h1), "") : assert_64
node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_989 :
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(sink_ok, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_T_996, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_996, UInt<1>(0h1), "") : assert_67
node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68
node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69
node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1009 = or(_T_1008, io.in.d.bits.corrupt)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70
node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1014 = or(UInt<1>(0h1), _T_1013)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71
node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73
node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74
node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1031 = or(UInt<1>(0h1), _T_1030)
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75
node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1035 :
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77
node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1044 = or(_T_1043, io.in.d.bits.corrupt)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78
node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1049 = or(UInt<1>(0h1), _T_1048)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79
node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1053 :
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81
node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82
node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1066 = or(UInt<1>(0h1), _T_1065)
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1082 = eq(a_first, UInt<1>(0h0))
node _T_1083 = and(io.in.a.valid, _T_1082)
when _T_1083 :
node _T_1084 = eq(io.in.a.bits.opcode, opcode)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87
node _T_1088 = eq(io.in.a.bits.param, param)
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88
node _T_1092 = eq(io.in.a.bits.size, size)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89
node _T_1096 = eq(io.in.a.bits.source, source)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90
node _T_1100 = eq(io.in.a.bits.address, address)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91
node _T_1104 = and(io.in.a.ready, io.in.a.valid)
node _T_1105 = and(_T_1104, a_first)
when _T_1105 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1106 = eq(d_first, UInt<1>(0h0))
node _T_1107 = and(io.in.d.valid, _T_1106)
when _T_1107 :
node _T_1108 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92
node _T_1112 = eq(io.in.d.bits.param, param_1)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93
node _T_1116 = eq(io.in.d.bits.size, size_1)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94
node _T_1120 = eq(io.in.d.bits.source, source_1)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95
node _T_1124 = eq(io.in.d.bits.sink, sink)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96
node _T_1128 = eq(io.in.d.bits.denied, denied)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97
node _T_1132 = and(io.in.d.ready, io.in.d.valid)
node _T_1133 = and(_T_1132, d_first)
when _T_1133 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1134 = and(io.in.a.valid, a_first_1)
node _T_1135 = and(_T_1134, UInt<1>(0h1))
when _T_1135 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1136 = and(io.in.a.ready, io.in.a.valid)
node _T_1137 = and(_T_1136, a_first_1)
node _T_1138 = and(_T_1137, UInt<1>(0h1))
when _T_1138 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1139 = dshr(inflight, io.in.a.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1145 = and(io.in.d.valid, d_first_1)
node _T_1146 = and(_T_1145, UInt<1>(0h1))
node _T_1147 = eq(d_release_ack, UInt<1>(0h0))
node _T_1148 = and(_T_1146, _T_1147)
when _T_1148 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1149 = and(io.in.d.ready, io.in.d.valid)
node _T_1150 = and(_T_1149, d_first_1)
node _T_1151 = and(_T_1150, UInt<1>(0h1))
node _T_1152 = eq(d_release_ack, UInt<1>(0h0))
node _T_1153 = and(_T_1151, _T_1152)
when _T_1153 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1154 = and(io.in.d.valid, d_first_1)
node _T_1155 = and(_T_1154, UInt<1>(0h1))
node _T_1156 = eq(d_release_ack, UInt<1>(0h0))
node _T_1157 = and(_T_1155, _T_1156)
when _T_1157 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1158 = dshr(inflight, io.in.d.bits.source)
node _T_1159 = bits(_T_1158, 0, 0)
node _T_1160 = or(_T_1159, same_cycle_resp)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1166 = or(_T_1164, _T_1165)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100
node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101
else :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102
node _T_1180 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103
node _T_1184 = and(io.in.d.valid, d_first_1)
node _T_1185 = and(_T_1184, a_first_1)
node _T_1186 = and(_T_1185, io.in.a.valid)
node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(d_release_ack, UInt<1>(0h0))
node _T_1190 = and(_T_1188, _T_1189)
when _T_1190 :
node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1192 = or(_T_1191, io.in.a.ready)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104
node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1197 = orr(a_set_wo_ready)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = or(_T_1196, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_139
node _T_1203 = orr(inflight)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1206 = or(_T_1204, _T_1205)
node _T_1207 = lt(watchdog, plusarg_reader.out)
node _T_1208 = or(_T_1206, _T_1207)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1212 = and(io.in.a.ready, io.in.a.valid)
node _T_1213 = and(io.in.d.ready, io.in.d.valid)
node _T_1214 = or(_T_1212, _T_1213)
when _T_1214 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1215 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1218 = and(_T_1216, _T_1217)
node _T_1219 = and(_T_1215, _T_1218)
when _T_1219 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1221 = and(_T_1220, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1224 = and(_T_1222, _T_1223)
node _T_1225 = and(_T_1221, _T_1224)
when _T_1225 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1227 = bits(_T_1226, 0, 0)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1232 = and(io.in.d.valid, d_first_2)
node _T_1233 = and(_T_1232, UInt<1>(0h1))
node _T_1234 = and(_T_1233, d_release_ack_1)
when _T_1234 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1235 = and(io.in.d.ready, io.in.d.valid)
node _T_1236 = and(_T_1235, d_first_2)
node _T_1237 = and(_T_1236, UInt<1>(0h1))
node _T_1238 = and(_T_1237, d_release_ack_1)
when _T_1238 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1239 = and(io.in.d.valid, d_first_2)
node _T_1240 = and(_T_1239, UInt<1>(0h1))
node _T_1241 = and(_T_1240, d_release_ack_1)
when _T_1241 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1242 = dshr(inflight_1, io.in.d.bits.source)
node _T_1243 = bits(_T_1242, 0, 0)
node _T_1244 = or(_T_1243, same_cycle_resp_1)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109
else :
node _T_1252 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110
node _T_1256 = and(io.in.d.valid, d_first_2)
node _T_1257 = and(_T_1256, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1258 = and(_T_1257, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1260 = and(_T_1258, _T_1259)
node _T_1261 = and(_T_1260, d_release_ack_1)
node _T_1262 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1263 = and(_T_1261, _T_1262)
when _T_1263 :
node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1265 = or(_T_1264, _WIRE_23.ready)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111
node _T_1269 = orr(c_set_wo_ready)
when _T_1269 :
node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_140
node _T_1274 = orr(inflight_1)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1277 = or(_T_1275, _T_1276)
node _T_1278 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1279 = or(_T_1277, _T_1278)
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1284 = and(io.in.d.ready, io.in.d.valid)
node _T_1285 = or(_T_1283, _T_1284)
when _T_1285 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_66( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_103 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_103( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_87 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_175
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_176
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_87( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ZstdMatchFinderLitLenInjector :
input clock : Clock
input reset : Reset
output io : { flip memwrites_in : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>, is_copy : UInt<1>, length_header : UInt<1>, is_dummy : UInt<1>}}, seq_memwrites_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>, is_copy : UInt<1>, length_header : UInt<1>, is_dummy : UInt<1>}}, lit_memwrites_out : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>, validbytes : UInt<6>, end_of_message : UInt<1>, is_copy : UInt<1>, length_header : UInt<1>, is_dummy : UInt<1>}}}
regreset track_blocks : UInt<64>, clock, reset, UInt<64>(0h0)
inst incoming_writes_Q of Queue4_CompressWriterBundle
connect incoming_writes_Q.clock, clock
connect incoming_writes_Q.reset, reset
connect incoming_writes_Q.io.enq, io.memwrites_in
node _T = and(io.memwrites_in.ready, io.memwrites_in.valid)
when _T :
regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1))
node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1)
connect loginfo_cycles, _loginfo_cycles_T_1
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "LLInjector-IO_MEMWRITE_FIRE\n") : printf_1
regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1))
node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1)
connect loginfo_cycles_1, _loginfo_cycles_T_3
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "data: 0x%x, validbytes: %d, is_copy: %d, EOM: %d\n", io.memwrites_in.bits.data, io.memwrites_in.bits.validbytes, io.memwrites_in.bits.is_copy, io.memwrites_in.bits.end_of_message) : printf_3
regreset lit_len_so_far : UInt<64>, clock, reset, UInt<64>(0h0)
node _copy_length_T = bits(incoming_writes_Q.io.deq.bits.data, 127, 64)
node _copy_length_T_1 = sub(_copy_length_T, UInt<2>(0h3))
node copy_length = tail(_copy_length_T_1, 1)
node _copy_offset_T = bits(incoming_writes_Q.io.deq.bits.data, 63, 0)
node _copy_offset_T_1 = add(_copy_offset_T, UInt<2>(0h3))
node copy_offset = tail(_copy_offset_T_1, 1)
node _sequence_T = bits(copy_offset, 31, 0)
node _sequence_T_1 = bits(copy_length, 31, 0)
node _sequence_T_2 = bits(lit_len_so_far, 31, 0)
node sequence_hi = cat(_sequence_T, _sequence_T_1)
node sequence = cat(sequence_hi, _sequence_T_2)
regreset llInjectorState : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_9 = eq(incoming_writes_Q.io.deq.bits.is_copy, UInt<1>(0h0))
node _T_10 = eq(llInjectorState, UInt<2>(0h0))
node _T_11 = eq(llInjectorState, UInt<2>(0h1))
node is_dummy_lit = eq(llInjectorState, UInt<2>(0h1))
node _io_lit_memwrites_out_valid_T = eq(incoming_writes_Q.io.deq.bits.length_header, UInt<1>(0h0))
node _io_lit_memwrites_out_valid_T_1 = and(incoming_writes_Q.io.deq.valid, _T_9)
node _io_lit_memwrites_out_valid_T_2 = and(_io_lit_memwrites_out_valid_T_1, _T_10)
node _io_lit_memwrites_out_valid_T_3 = and(_io_lit_memwrites_out_valid_T_2, _io_lit_memwrites_out_valid_T)
node _io_lit_memwrites_out_valid_T_4 = or(_io_lit_memwrites_out_valid_T_3, _T_11)
connect io.lit_memwrites_out.valid, _io_lit_memwrites_out_valid_T_4
connect io.lit_memwrites_out.bits, incoming_writes_Q.io.deq.bits
node _io_lit_memwrites_out_bits_data_T = mux(is_dummy_lit, UInt<1>(0h0), incoming_writes_Q.io.deq.bits.data)
connect io.lit_memwrites_out.bits.data, _io_lit_memwrites_out_bits_data_T
node _io_lit_memwrites_out_bits_validbytes_T = mux(is_dummy_lit, UInt<1>(0h1), incoming_writes_Q.io.deq.bits.validbytes)
connect io.lit_memwrites_out.bits.validbytes, _io_lit_memwrites_out_bits_validbytes_T
node _io_lit_memwrites_out_bits_end_of_message_T = or(incoming_writes_Q.io.deq.bits.end_of_message, is_dummy_lit)
connect io.lit_memwrites_out.bits.end_of_message, _io_lit_memwrites_out_bits_end_of_message_T
connect io.lit_memwrites_out.bits.is_dummy, is_dummy_lit
node _T_12 = and(io.lit_memwrites_out.ready, incoming_writes_Q.io.deq.valid)
node _T_13 = and(_T_12, _T_9)
node _T_14 = and(_T_13, _T_10)
when _T_14 :
node _lit_len_so_far_T = eq(incoming_writes_Q.io.deq.bits.length_header, UInt<1>(0h0))
node _lit_len_so_far_T_1 = mux(_lit_len_so_far_T, incoming_writes_Q.io.deq.bits.validbytes, UInt<1>(0h0))
node _lit_len_so_far_T_2 = add(lit_len_so_far, _lit_len_so_far_T_1)
node _lit_len_so_far_T_3 = tail(_lit_len_so_far_T_2, 1)
connect lit_len_so_far, _lit_len_so_far_T_3
when incoming_writes_Q.io.deq.bits.end_of_message :
connect llInjectorState, UInt<2>(0h2)
regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1))
node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1)
connect loginfo_cycles_2, _loginfo_cycles_T_5
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "LLInjector-LIT_FIRE\n") : printf_5
regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1))
node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1)
connect loginfo_cycles_3, _loginfo_cycles_T_7
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "data: 0x%x\n validbytes: %d, EOM: %d\n", io.lit_memwrites_out.bits.data, io.lit_memwrites_out.bits.validbytes, io.lit_memwrites_out.bits.end_of_message) : printf_7
node _T_23 = and(io.lit_memwrites_out.ready, _T_11)
when _T_23 :
regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1))
node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1)
connect loginfo_cycles_4, _loginfo_cycles_T_9
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
printf(clock, UInt<1>(0h1), "LLInjector-DUMMY_LIT_FIRE\n") : printf_9
node _T_28 = eq(llInjectorState, UInt<2>(0h0))
node _T_29 = eq(llInjectorState, UInt<2>(0h2))
node is_dummy_copy = eq(llInjectorState, UInt<2>(0h2))
node _io_seq_memwrites_out_valid_T = and(incoming_writes_Q.io.deq.valid, incoming_writes_Q.io.deq.bits.is_copy)
node _io_seq_memwrites_out_valid_T_1 = and(_io_seq_memwrites_out_valid_T, _T_28)
node _io_seq_memwrites_out_valid_T_2 = or(_io_seq_memwrites_out_valid_T_1, _T_29)
connect io.seq_memwrites_out.valid, _io_seq_memwrites_out_valid_T_2
connect io.seq_memwrites_out.bits.is_dummy, io.lit_memwrites_out.bits.is_dummy
connect io.seq_memwrites_out.bits.length_header, io.lit_memwrites_out.bits.length_header
connect io.seq_memwrites_out.bits.is_copy, io.lit_memwrites_out.bits.is_copy
connect io.seq_memwrites_out.bits.end_of_message, io.lit_memwrites_out.bits.end_of_message
connect io.seq_memwrites_out.bits.validbytes, io.lit_memwrites_out.bits.validbytes
connect io.seq_memwrites_out.bits.data, io.lit_memwrites_out.bits.data
node _io_seq_memwrites_out_bits_data_T = mux(is_dummy_copy, UInt<1>(0h0), sequence)
connect io.seq_memwrites_out.bits.data, _io_seq_memwrites_out_bits_data_T
node _io_seq_memwrites_out_bits_validbytes_T = mux(is_dummy_copy, UInt<1>(0h1), UInt<4>(0hc))
connect io.seq_memwrites_out.bits.validbytes, _io_seq_memwrites_out_bits_validbytes_T
node _io_seq_memwrites_out_bits_end_of_message_T = or(incoming_writes_Q.io.deq.bits.end_of_message, is_dummy_copy)
connect io.seq_memwrites_out.bits.end_of_message, _io_seq_memwrites_out_bits_end_of_message_T
connect io.seq_memwrites_out.bits.is_dummy, is_dummy_copy
node _T_30 = and(io.seq_memwrites_out.ready, incoming_writes_Q.io.deq.valid)
node _T_31 = and(_T_30, incoming_writes_Q.io.deq.bits.is_copy)
node _T_32 = and(_T_31, _T_28)
when _T_32 :
connect lit_len_so_far, UInt<1>(0h0)
when incoming_writes_Q.io.deq.bits.end_of_message :
connect llInjectorState, UInt<2>(0h1)
regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1))
node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1)
connect loginfo_cycles_5, _loginfo_cycles_T_11
node _T_33 = asUInt(reset)
node _T_34 = eq(_T_33, UInt<1>(0h0))
when _T_34 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "LLInjector-COPY_FIRE\n") : printf_11
node _T_37 = bits(sequence, 31, 0)
node _T_38 = bits(sequence, 63, 32)
node _T_39 = bits(sequence, 95, 64)
regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1))
node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1)
connect loginfo_cycles_6, _loginfo_cycles_T_13
node _T_40 = asUInt(reset)
node _T_41 = eq(_T_40, UInt<1>(0h0))
when _T_41 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12
node _T_42 = asUInt(reset)
node _T_43 = eq(_T_42, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "ll: %d, ml: %d, of: %d EOM: %d bid: %d\n", _T_37, _T_38, _T_39, io.seq_memwrites_out.bits.end_of_message, track_blocks) : printf_13
node _T_44 = and(io.seq_memwrites_out.ready, _T_29)
when _T_44 :
regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0)
node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1))
node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1)
connect loginfo_cycles_7, _loginfo_cycles_T_15
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "LLInjector-DUMMY_COPY_FIRE\n") : printf_15
node _T_49 = and(io.seq_memwrites_out.ready, _T_29)
node _T_50 = and(io.lit_memwrites_out.ready, _T_11)
node _T_51 = or(_T_49, _T_50)
when _T_51 :
connect llInjectorState, UInt<2>(0h0)
connect lit_len_so_far, UInt<1>(0h0)
node _track_blocks_T = add(track_blocks, UInt<1>(0h1))
node _track_blocks_T_1 = tail(_track_blocks_T, 1)
connect track_blocks, _track_blocks_T_1
node _incoming_writes_Q_io_deq_ready_T = and(io.lit_memwrites_out.ready, _T_9)
node _incoming_writes_Q_io_deq_ready_T_1 = and(_incoming_writes_Q_io_deq_ready_T, _T_10)
node _incoming_writes_Q_io_deq_ready_T_2 = and(io.seq_memwrites_out.ready, incoming_writes_Q.io.deq.bits.is_copy)
node _incoming_writes_Q_io_deq_ready_T_3 = and(_incoming_writes_Q_io_deq_ready_T_2, _T_28)
node _incoming_writes_Q_io_deq_ready_T_4 = or(_incoming_writes_Q_io_deq_ready_T_1, _incoming_writes_Q_io_deq_ready_T_3)
connect incoming_writes_Q.io.deq.ready, _incoming_writes_Q_io_deq_ready_T_4 | module ZstdMatchFinderLitLenInjector( // @[ZstdMatchFinderLitLenInjector.scala:17:7]
input clock, // @[ZstdMatchFinderLitLenInjector.scala:17:7]
input reset, // @[ZstdMatchFinderLitLenInjector.scala:17:7]
output io_memwrites_in_ready, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input io_memwrites_in_valid, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input [255:0] io_memwrites_in_bits_data, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input [5:0] io_memwrites_in_bits_validbytes, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input io_memwrites_in_bits_end_of_message, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input io_memwrites_in_bits_is_copy, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input io_memwrites_in_bits_length_header, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input io_seq_memwrites_out_ready, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_seq_memwrites_out_valid, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output [255:0] io_seq_memwrites_out_bits_data, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output [5:0] io_seq_memwrites_out_bits_validbytes, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_seq_memwrites_out_bits_end_of_message, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_seq_memwrites_out_bits_is_copy, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_seq_memwrites_out_bits_length_header, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_seq_memwrites_out_bits_is_dummy, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
input io_lit_memwrites_out_ready, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_lit_memwrites_out_valid, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output [255:0] io_lit_memwrites_out_bits_data, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output [5:0] io_lit_memwrites_out_bits_validbytes, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_lit_memwrites_out_bits_end_of_message, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_lit_memwrites_out_bits_is_copy, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_lit_memwrites_out_bits_length_header, // @[ZstdMatchFinderLitLenInjector.scala:18:14]
output io_lit_memwrites_out_bits_is_dummy // @[ZstdMatchFinderLitLenInjector.scala:18:14]
);
wire _incoming_writes_Q_io_deq_valid; // @[ZstdMatchFinderLitLenInjector.scala:27:33]
wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdMatchFinderLitLenInjector.scala:27:33]
wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdMatchFinderLitLenInjector.scala:27:33]
wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdMatchFinderLitLenInjector.scala:27:33]
wire _incoming_writes_Q_io_deq_bits_is_copy; // @[ZstdMatchFinderLitLenInjector.scala:27:33]
wire _incoming_writes_Q_io_deq_bits_length_header; // @[ZstdMatchFinderLitLenInjector.scala:27:33]
wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire [5:0] io_memwrites_in_bits_validbytes_0 = io_memwrites_in_bits_validbytes; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_memwrites_in_bits_is_copy_0 = io_memwrites_in_bits_is_copy; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_memwrites_in_bits_length_header_0 = io_memwrites_in_bits_length_header; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_seq_memwrites_out_ready_0 = io_seq_memwrites_out_ready; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_lit_memwrites_out_ready_0 = io_lit_memwrites_out_ready; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_memwrites_in_bits_is_dummy = 1'h0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire _io_seq_memwrites_out_valid_T_2; // @[ZstdMatchFinderLitLenInjector.scala:104:77]
wire _io_seq_memwrites_out_bits_end_of_message_T; // @[ZstdMatchFinderLitLenInjector.scala:108:92]
wire io_lit_memwrites_out_bits_is_copy_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_lit_memwrites_out_bits_length_header_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire is_dummy_copy; // @[ZstdMatchFinderLitLenInjector.scala:102:39]
wire _io_lit_memwrites_out_valid_T_4; // @[ZstdMatchFinderLitLenInjector.scala:67:95]
wire [255:0] _io_lit_memwrites_out_bits_data_T; // @[ZstdMatchFinderLitLenInjector.scala:70:40]
wire [5:0] _io_lit_memwrites_out_bits_validbytes_T; // @[ZstdMatchFinderLitLenInjector.scala:71:46]
wire _io_lit_memwrites_out_bits_end_of_message_T; // @[ZstdMatchFinderLitLenInjector.scala:72:92]
wire io_seq_memwrites_out_bits_is_copy_0 = io_lit_memwrites_out_bits_is_copy_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_seq_memwrites_out_bits_length_header_0 = io_lit_memwrites_out_bits_length_header_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire is_dummy_lit; // @[ZstdMatchFinderLitLenInjector.scala:64:38]
wire io_memwrites_in_ready_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire [255:0] io_seq_memwrites_out_bits_data_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire [5:0] io_seq_memwrites_out_bits_validbytes_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_seq_memwrites_out_bits_end_of_message_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_seq_memwrites_out_bits_is_dummy_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_seq_memwrites_out_valid_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire [255:0] io_lit_memwrites_out_bits_data_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire [5:0] io_lit_memwrites_out_bits_validbytes_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_lit_memwrites_out_bits_end_of_message_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_lit_memwrites_out_bits_is_dummy_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
wire io_lit_memwrites_out_valid_0; // @[ZstdMatchFinderLitLenInjector.scala:17:7]
reg [63:0] track_blocks; // @[ZstdMatchFinderLitLenInjector.scala:25:29]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
reg [63:0] lit_len_so_far; // @[ZstdMatchFinderLitLenInjector.scala:40:31]
wire [63:0] _copy_length_T = _incoming_writes_Q_io_deq_bits_data[127:64]; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :43:55]
wire [64:0] _copy_length_T_1 = {1'h0, _copy_length_T} - 65'h3; // @[ZstdMatchFinderLitLenInjector.scala:43:{55,65}]
wire [63:0] copy_length = _copy_length_T_1[63:0]; // @[ZstdMatchFinderLitLenInjector.scala:43:65]
wire [63:0] _copy_offset_T = _incoming_writes_Q_io_deq_bits_data[63:0]; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :44:55]
wire [64:0] _copy_offset_T_1 = {1'h0, _copy_offset_T} + 65'h3; // @[ZstdMatchFinderLitLenInjector.scala:44:{55,63}]
wire [63:0] copy_offset = _copy_offset_T_1[63:0]; // @[ZstdMatchFinderLitLenInjector.scala:44:63]
wire [31:0] _sequence_T = copy_offset[31:0]; // @[ZstdMatchFinderLitLenInjector.scala:44:63, :46:33]
wire [31:0] _sequence_T_1 = copy_length[31:0]; // @[ZstdMatchFinderLitLenInjector.scala:43:65, :46:53]
wire [31:0] _sequence_T_2 = lit_len_so_far[31:0]; // @[ZstdMatchFinderLitLenInjector.scala:40:31, :46:76]
wire [63:0] sequence_hi = {_sequence_T, _sequence_T_1}; // @[ZstdMatchFinderLitLenInjector.scala:46:{21,33,53}]
wire [95:0] sequence_0 = {sequence_hi, _sequence_T_2}; // @[ZstdMatchFinderLitLenInjector.scala:46:{21,76}]
reg [1:0] llInjectorState; // @[ZstdMatchFinderLitLenInjector.scala:51:32]
wire _T_28 = llInjectorState == 2'h0; // @[ZstdMatchFinderLitLenInjector.scala:51:32, :57:21]
assign is_dummy_lit = llInjectorState == 2'h1; // @[ZstdMatchFinderLitLenInjector.scala:51:32, :61:21, :64:38]
assign io_lit_memwrites_out_bits_is_dummy_0 = is_dummy_lit; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :64:38]
wire _io_lit_memwrites_out_valid_T = ~_incoming_writes_Q_io_deq_bits_length_header; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :67:76]
wire _io_lit_memwrites_out_valid_T_1 = _incoming_writes_Q_io_deq_valid & ~_incoming_writes_Q_io_deq_bits_is_copy; // @[Misc.scala:26:53]
wire _io_lit_memwrites_out_valid_T_2 = _io_lit_memwrites_out_valid_T_1 & _T_28; // @[Misc.scala:26:53]
wire _io_lit_memwrites_out_valid_T_3 = _io_lit_memwrites_out_valid_T_2 & _io_lit_memwrites_out_valid_T; // @[Misc.scala:26:53]
assign _io_lit_memwrites_out_valid_T_4 = _io_lit_memwrites_out_valid_T_3 | is_dummy_lit; // @[Misc.scala:26:53]
assign io_lit_memwrites_out_valid_0 = _io_lit_memwrites_out_valid_T_4; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :67:95]
assign _io_lit_memwrites_out_bits_data_T = is_dummy_lit ? 256'h0 : _incoming_writes_Q_io_deq_bits_data; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :64:38, :70:40]
assign io_lit_memwrites_out_bits_data_0 = _io_lit_memwrites_out_bits_data_T; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :70:40]
assign _io_lit_memwrites_out_bits_validbytes_T = is_dummy_lit ? 6'h1 : _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :64:38, :71:46]
assign io_lit_memwrites_out_bits_validbytes_0 = _io_lit_memwrites_out_bits_validbytes_T; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :71:46]
assign _io_lit_memwrites_out_bits_end_of_message_T = _incoming_writes_Q_io_deq_bits_end_of_message | is_dummy_lit; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :64:38, :72:92]
assign io_lit_memwrites_out_bits_end_of_message_0 = _io_lit_memwrites_out_bits_end_of_message_T; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :72:92]
wire _T_14 = io_lit_memwrites_out_ready_0 & _incoming_writes_Q_io_deq_valid & ~_incoming_writes_Q_io_deq_bits_is_copy & _T_28; // @[Misc.scala:29:18]
wire _lit_len_so_far_T = ~_incoming_writes_Q_io_deq_bits_length_header; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :67:76, :76:44]
wire [5:0] _lit_len_so_far_T_1 = _lit_len_so_far_T ? _incoming_writes_Q_io_deq_bits_validbytes : 6'h0; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :76:{43,44}]
wire [64:0] _lit_len_so_far_T_2 = {1'h0, lit_len_so_far} + {59'h0, _lit_len_so_far_T_1}; // @[ZstdMatchFinderLitLenInjector.scala:40:31, :76:{38,43}]
wire [63:0] _lit_len_so_far_T_3 = _lit_len_so_far_T_2[63:0]; // @[ZstdMatchFinderLitLenInjector.scala:76:38]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
wire _T_50 = io_lit_memwrites_out_ready_0 & is_dummy_lit; // @[Misc.scala:29:18]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
assign is_dummy_copy = llInjectorState == 2'h2; // @[ZstdMatchFinderLitLenInjector.scala:51:32, :100:21, :102:39]
assign io_seq_memwrites_out_bits_is_dummy_0 = is_dummy_copy; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :102:39]
wire _io_seq_memwrites_out_valid_T = _incoming_writes_Q_io_deq_valid & _incoming_writes_Q_io_deq_bits_is_copy; // @[Misc.scala:26:53]
wire _io_seq_memwrites_out_valid_T_1 = _io_seq_memwrites_out_valid_T & _T_28; // @[Misc.scala:26:53]
assign _io_seq_memwrites_out_valid_T_2 = _io_seq_memwrites_out_valid_T_1 | is_dummy_copy; // @[Misc.scala:26:53]
assign io_seq_memwrites_out_valid_0 = _io_seq_memwrites_out_valid_T_2; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :104:77]
wire [95:0] _io_seq_memwrites_out_bits_data_T = is_dummy_copy ? 96'h0 : sequence_0; // @[ZstdMatchFinderLitLenInjector.scala:46:21, :102:39, :106:40]
assign io_seq_memwrites_out_bits_data_0 = {160'h0, _io_seq_memwrites_out_bits_data_T}; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :106:{34,40}]
wire [3:0] _io_seq_memwrites_out_bits_validbytes_T = is_dummy_copy ? 4'h1 : 4'hC; // @[ZstdMatchFinderLitLenInjector.scala:102:39, :107:46]
assign io_seq_memwrites_out_bits_validbytes_0 = {2'h0, _io_seq_memwrites_out_bits_validbytes_T}; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :107:{40,46}]
assign _io_seq_memwrites_out_bits_end_of_message_T = _incoming_writes_Q_io_deq_bits_end_of_message | is_dummy_copy; // @[ZstdMatchFinderLitLenInjector.scala:27:33, :102:39, :108:92]
assign io_seq_memwrites_out_bits_end_of_message_0 = _io_seq_memwrites_out_bits_end_of_message_T; // @[ZstdMatchFinderLitLenInjector.scala:17:7, :108:92]
wire _T_32 = io_seq_memwrites_out_ready_0 & _incoming_writes_Q_io_deq_valid & _incoming_writes_Q_io_deq_bits_is_copy & _T_28; // @[Misc.scala:29:18]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38]
wire _T_49 = io_seq_memwrites_out_ready_0 & is_dummy_copy; // @[Misc.scala:29:18]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to this FIRRTL code module PE_492 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_236
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_492( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_236 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_123 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}}, flip out_credit_available : { `1` : UInt<1>[10], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}}
inst input_buffer of InputBuffer_123
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
connect input_buffer.io.deq[8].ready, UInt<1>(0h0)
connect input_buffer.io.deq[9].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter10_RouteComputerReq_17
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[8], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[9], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_9 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_9 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_10 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_10 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_11 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_11 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_12 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_12 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_13 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_13 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_14 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_14 :
connect states[7].g, UInt<3>(0h2)
node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1))
connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T
connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id
connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node
connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id
connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node
connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id
connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8)
node _T_15 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid)
when _T_15 :
connect states[8].g, UInt<3>(0h2)
node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1))
connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T
connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id
connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node
connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id
connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node
connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id
connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9)
node _T_16 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid)
when _T_16 :
connect states[9].g, UInt<3>(0h2)
node _T_17 = and(io.router_req.ready, io.router_req.valid)
when _T_17 :
node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_30 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id)
when _T_30 :
connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_31 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id)
when _T_31 :
connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1`
regreset mask : UInt<10>, clock, reset, UInt<10>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}}[10]
wire vcalloc_vals : UInt<1>[10]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5])
node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8])
node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5])
node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16)
node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17)
node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18)
node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0))
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34)
node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35)
node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36)
node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37)
node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38)
node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39)
node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40)
node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41)
node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43)
node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_32 = and(io.router_req.ready, io.router_req.valid)
when _T_32 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_33 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_34 = or(_T_33, vcalloc_vals[2])
node _T_35 = or(_T_34, vcalloc_vals[3])
node _T_36 = or(_T_35, vcalloc_vals[4])
node _T_37 = or(_T_36, vcalloc_vals[5])
node _T_38 = or(_T_37, vcalloc_vals[6])
node _T_39 = or(_T_38, vcalloc_vals[7])
node _T_40 = or(_T_39, vcalloc_vals[8])
node _T_41 = or(_T_40, vcalloc_vals[9])
when _T_41 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = not(UInt<9>(0h0))
node _mask_T_12 = not(UInt<10>(0h0))
node _mask_T_13 = bits(vcalloc_sel, 0, 0)
node _mask_T_14 = bits(vcalloc_sel, 1, 1)
node _mask_T_15 = bits(vcalloc_sel, 2, 2)
node _mask_T_16 = bits(vcalloc_sel, 3, 3)
node _mask_T_17 = bits(vcalloc_sel, 4, 4)
node _mask_T_18 = bits(vcalloc_sel, 5, 5)
node _mask_T_19 = bits(vcalloc_sel, 6, 6)
node _mask_T_20 = bits(vcalloc_sel, 7, 7)
node _mask_T_21 = bits(vcalloc_sel, 8, 8)
node _mask_T_22 = bits(vcalloc_sel, 9, 9)
node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0))
node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0))
node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0))
node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0))
node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0))
node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0))
node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0))
node _mask_T_33 = or(_mask_T_23, _mask_T_24)
node _mask_T_34 = or(_mask_T_33, _mask_T_25)
node _mask_T_35 = or(_mask_T_34, _mask_T_26)
node _mask_T_36 = or(_mask_T_35, _mask_T_27)
node _mask_T_37 = or(_mask_T_36, _mask_T_28)
node _mask_T_38 = or(_mask_T_37, _mask_T_29)
node _mask_T_39 = or(_mask_T_38, _mask_T_30)
node _mask_T_40 = or(_mask_T_39, _mask_T_31)
node _mask_T_41 = or(_mask_T_40, _mask_T_32)
wire _mask_WIRE : UInt<10>
connect _mask_WIRE, _mask_T_41
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8])
node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8)
node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[10], `0` : UInt<1>[10]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10]
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15)
node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16)
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18)
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30)
node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31)
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33)
node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35)
node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36)
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50)
node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51)
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75)
node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90)
node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91)
node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92)
node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93)
node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94)
node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106)
node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107)
node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108)
node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109)
node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110)
node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111)
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125)
node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126)
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150)
node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151)
node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165)
node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166)
node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167)
node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168)
node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169)
node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170)
node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180
connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182)
node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183)
node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184)
node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185)
node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186)
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199
connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[10]
node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201)
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218
connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225)
node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226)
node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227)
node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_237
connect _io_vcalloc_req_bits_WIRE_13[1], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240)
node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241)
node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242)
node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243)
node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244)
node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245)
node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246)
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_256
connect _io_vcalloc_req_bits_WIRE_13[2], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258)
node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259)
node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260)
node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261)
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_275
connect _io_vcalloc_req_bits_WIRE_13[3], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_294
connect _io_vcalloc_req_bits_WIRE_13[4], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300)
node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301)
node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302)
node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303)
node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_313
connect _io_vcalloc_req_bits_WIRE_13[5], _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315)
node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316)
node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317)
node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318)
node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319)
node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320)
node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321)
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_332
connect _io_vcalloc_req_bits_WIRE_13[6], _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334)
node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335)
node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336)
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_351
connect _io_vcalloc_req_bits_WIRE_13[7], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[8], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360)
node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_370
connect _io_vcalloc_req_bits_WIRE_13[8], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_377 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_378 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_379 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_380 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[9], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_371, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_383 = or(_io_vcalloc_req_bits_T_382, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_384 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_375)
node _io_vcalloc_req_bits_T_385 = or(_io_vcalloc_req_bits_T_384, _io_vcalloc_req_bits_T_376)
node _io_vcalloc_req_bits_T_386 = or(_io_vcalloc_req_bits_T_385, _io_vcalloc_req_bits_T_377)
node _io_vcalloc_req_bits_T_387 = or(_io_vcalloc_req_bits_T_386, _io_vcalloc_req_bits_T_378)
node _io_vcalloc_req_bits_T_388 = or(_io_vcalloc_req_bits_T_387, _io_vcalloc_req_bits_T_379)
node _io_vcalloc_req_bits_T_389 = or(_io_vcalloc_req_bits_T_388, _io_vcalloc_req_bits_T_380)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_389
connect _io_vcalloc_req_bits_WIRE_13[9], _io_vcalloc_req_bits_WIRE_23
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_392 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_393 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_394 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_395 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_396 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_397 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = or(_io_vcalloc_req_bits_T_390, _io_vcalloc_req_bits_T_391)
node _io_vcalloc_req_bits_T_401 = or(_io_vcalloc_req_bits_T_400, _io_vcalloc_req_bits_T_392)
node _io_vcalloc_req_bits_T_402 = or(_io_vcalloc_req_bits_T_401, _io_vcalloc_req_bits_T_393)
node _io_vcalloc_req_bits_T_403 = or(_io_vcalloc_req_bits_T_402, _io_vcalloc_req_bits_T_394)
node _io_vcalloc_req_bits_T_404 = or(_io_vcalloc_req_bits_T_403, _io_vcalloc_req_bits_T_395)
node _io_vcalloc_req_bits_T_405 = or(_io_vcalloc_req_bits_T_404, _io_vcalloc_req_bits_T_396)
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_405, _io_vcalloc_req_bits_T_397)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_398)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_399)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_408
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_24
wire _io_vcalloc_req_bits_WIRE_25 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}
node _io_vcalloc_req_bits_T_409 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_410 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_411 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_412 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_410)
node _io_vcalloc_req_bits_T_420 = or(_io_vcalloc_req_bits_T_419, _io_vcalloc_req_bits_T_411)
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_420, _io_vcalloc_req_bits_T_412)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_413)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_418)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_25.egress_node_id, _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_437 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_443 = or(_io_vcalloc_req_bits_T_442, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_444 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_435)
node _io_vcalloc_req_bits_T_445 = or(_io_vcalloc_req_bits_T_444, _io_vcalloc_req_bits_T_436)
node _io_vcalloc_req_bits_T_446 = or(_io_vcalloc_req_bits_T_445, _io_vcalloc_req_bits_T_437)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_446
connect _io_vcalloc_req_bits_WIRE_25.egress_node, _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_452 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_453 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_454 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_455 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_456 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_447, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_458 = or(_io_vcalloc_req_bits_T_457, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_459 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_450)
node _io_vcalloc_req_bits_T_460 = or(_io_vcalloc_req_bits_T_459, _io_vcalloc_req_bits_T_451)
node _io_vcalloc_req_bits_T_461 = or(_io_vcalloc_req_bits_T_460, _io_vcalloc_req_bits_T_452)
node _io_vcalloc_req_bits_T_462 = or(_io_vcalloc_req_bits_T_461, _io_vcalloc_req_bits_T_453)
node _io_vcalloc_req_bits_T_463 = or(_io_vcalloc_req_bits_T_462, _io_vcalloc_req_bits_T_454)
node _io_vcalloc_req_bits_T_464 = or(_io_vcalloc_req_bits_T_463, _io_vcalloc_req_bits_T_455)
node _io_vcalloc_req_bits_T_465 = or(_io_vcalloc_req_bits_T_464, _io_vcalloc_req_bits_T_456)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_465
connect _io_vcalloc_req_bits_WIRE_25.ingress_node_id, _io_vcalloc_req_bits_WIRE_28
node _io_vcalloc_req_bits_T_466 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_467 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_468 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_469 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_470 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_471 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_472 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_467)
node _io_vcalloc_req_bits_T_477 = or(_io_vcalloc_req_bits_T_476, _io_vcalloc_req_bits_T_468)
node _io_vcalloc_req_bits_T_478 = or(_io_vcalloc_req_bits_T_477, _io_vcalloc_req_bits_T_469)
node _io_vcalloc_req_bits_T_479 = or(_io_vcalloc_req_bits_T_478, _io_vcalloc_req_bits_T_470)
node _io_vcalloc_req_bits_T_480 = or(_io_vcalloc_req_bits_T_479, _io_vcalloc_req_bits_T_471)
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_480, _io_vcalloc_req_bits_T_472)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_473)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_475)
wire _io_vcalloc_req_bits_WIRE_29 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_484
connect _io_vcalloc_req_bits_WIRE_25.ingress_node, _io_vcalloc_req_bits_WIRE_29
node _io_vcalloc_req_bits_T_485 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_486 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_487 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_486)
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_495, _io_vcalloc_req_bits_T_487)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_488)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_503 = or(_io_vcalloc_req_bits_T_502, _io_vcalloc_req_bits_T_494)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_503
connect _io_vcalloc_req_bits_WIRE_25.vnet_id, _io_vcalloc_req_bits_WIRE_30
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_25
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`0`[8]
invalidate vcalloc_reqs[0].vc_sel.`0`[9]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[5]
invalidate vcalloc_reqs[0].vc_sel.`1`[6]
invalidate vcalloc_reqs[0].vc_sel.`1`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[8]
invalidate vcalloc_reqs[0].vc_sel.`1`[9]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`0`[3]
invalidate vcalloc_reqs[1].vc_sel.`0`[4]
invalidate vcalloc_reqs[1].vc_sel.`0`[5]
invalidate vcalloc_reqs[1].vc_sel.`0`[6]
invalidate vcalloc_reqs[1].vc_sel.`0`[7]
invalidate vcalloc_reqs[1].vc_sel.`0`[8]
invalidate vcalloc_reqs[1].vc_sel.`0`[9]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[3]
invalidate vcalloc_reqs[1].vc_sel.`1`[4]
invalidate vcalloc_reqs[1].vc_sel.`1`[5]
invalidate vcalloc_reqs[1].vc_sel.`1`[6]
invalidate vcalloc_reqs[1].vc_sel.`1`[7]
invalidate vcalloc_reqs[1].vc_sel.`1`[8]
invalidate vcalloc_reqs[1].vc_sel.`1`[9]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_42 = bits(vcalloc_sel, 2, 2)
node _T_43 = and(vcalloc_vals[2], _T_42)
node _T_44 = and(_T_43, io.vcalloc_req.ready)
when _T_44 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_45 = bits(vcalloc_sel, 3, 3)
node _T_46 = and(vcalloc_vals[3], _T_45)
node _T_47 = and(_T_46, io.vcalloc_req.ready)
when _T_47 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_48 = bits(vcalloc_sel, 4, 4)
node _T_49 = and(vcalloc_vals[4], _T_48)
node _T_50 = and(_T_49, io.vcalloc_req.ready)
when _T_50 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_51 = bits(vcalloc_sel, 5, 5)
node _T_52 = and(vcalloc_vals[5], _T_51)
node _T_53 = and(_T_52, io.vcalloc_req.ready)
when _T_53 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_54 = bits(vcalloc_sel, 6, 6)
node _T_55 = and(vcalloc_vals[6], _T_54)
node _T_56 = and(_T_55, io.vcalloc_req.ready)
when _T_56 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_57 = bits(vcalloc_sel, 7, 7)
node _T_58 = and(vcalloc_vals[7], _T_57)
node _T_59 = and(_T_58, io.vcalloc_req.ready)
when _T_59 :
connect states[7].g, UInt<3>(0h3)
node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2))
node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1)
connect vcalloc_vals[8], _vcalloc_vals_8_T_2
connect vcalloc_reqs[8].in_vc, UInt<4>(0h8)
connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0`
connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1`
connect vcalloc_reqs[8].flow, states[8].flow
node _T_60 = bits(vcalloc_sel, 8, 8)
node _T_61 = and(vcalloc_vals[8], _T_60)
node _T_62 = and(_T_61, io.vcalloc_req.ready)
when _T_62 :
connect states[8].g, UInt<3>(0h3)
node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2))
node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1)
connect vcalloc_vals[9], _vcalloc_vals_9_T_2
connect vcalloc_reqs[9].in_vc, UInt<4>(0h9)
connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0`
connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1`
connect vcalloc_reqs[9].flow, states[9].flow
node _T_63 = bits(vcalloc_sel, 9, 9)
node _T_64 = and(vcalloc_vals[9], _T_63)
node _T_65 = and(_T_64, io.vcalloc_req.ready)
when _T_65 :
connect states[9].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0)
node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5)
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9])
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0)
node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0)
node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13)
node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0)
node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15)
node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0)
node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready)
node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_19
node _T_66 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_66 :
node _T_67 = bits(vcalloc_sel, 0, 0)
when _T_67 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].g, UInt<3>(0h3)
node _T_68 = eq(states[0].g, UInt<3>(0h2))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_68, UInt<1>(0h1), "") : assert_3
node _T_72 = bits(vcalloc_sel, 1, 1)
when _T_72 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].g, UInt<3>(0h3)
node _T_73 = eq(states[1].g, UInt<3>(0h2))
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_73, UInt<1>(0h1), "") : assert_4
node _T_77 = bits(vcalloc_sel, 2, 2)
when _T_77 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].g, UInt<3>(0h3)
node _T_78 = eq(states[2].g, UInt<3>(0h2))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_78, UInt<1>(0h1), "") : assert_5
node _T_82 = bits(vcalloc_sel, 3, 3)
when _T_82 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].g, UInt<3>(0h3)
node _T_83 = eq(states[3].g, UInt<3>(0h2))
node _T_84 = asUInt(reset)
node _T_85 = eq(_T_84, UInt<1>(0h0))
when _T_85 :
node _T_86 = eq(_T_83, UInt<1>(0h0))
when _T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_83, UInt<1>(0h1), "") : assert_6
node _T_87 = bits(vcalloc_sel, 4, 4)
when _T_87 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].g, UInt<3>(0h3)
node _T_88 = eq(states[4].g, UInt<3>(0h2))
node _T_89 = asUInt(reset)
node _T_90 = eq(_T_89, UInt<1>(0h0))
when _T_90 :
node _T_91 = eq(_T_88, UInt<1>(0h0))
when _T_91 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_88, UInt<1>(0h1), "") : assert_7
node _T_92 = bits(vcalloc_sel, 5, 5)
when _T_92 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].g, UInt<3>(0h3)
node _T_93 = eq(states[5].g, UInt<3>(0h2))
node _T_94 = asUInt(reset)
node _T_95 = eq(_T_94, UInt<1>(0h0))
when _T_95 :
node _T_96 = eq(_T_93, UInt<1>(0h0))
when _T_96 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_93, UInt<1>(0h1), "") : assert_8
node _T_97 = bits(vcalloc_sel, 6, 6)
when _T_97 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].g, UInt<3>(0h3)
node _T_98 = eq(states[6].g, UInt<3>(0h2))
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_98, UInt<1>(0h1), "") : assert_9
node _T_102 = bits(vcalloc_sel, 7, 7)
when _T_102 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].g, UInt<3>(0h3)
node _T_103 = eq(states[7].g, UInt<3>(0h2))
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_103, UInt<1>(0h1), "") : assert_10
node _T_107 = bits(vcalloc_sel, 8, 8)
when _T_107 :
connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[8].g, UInt<3>(0h3)
node _T_108 = eq(states[8].g, UInt<3>(0h2))
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11
assert(clock, _T_108, UInt<1>(0h1), "") : assert_11
node _T_112 = bits(vcalloc_sel, 9, 9)
when _T_112 :
connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[9].g, UInt<3>(0h3)
node _T_113 = eq(states[9].g, UInt<3>(0h2))
node _T_114 = asUInt(reset)
node _T_115 = eq(_T_114, UInt<1>(0h0))
when _T_115 :
node _T_116 = eq(_T_113, UInt<1>(0h0))
when _T_116 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12
assert(clock, _T_113, UInt<1>(0h1), "") : assert_12
inst salloc_arb of SwitchArbiter_328
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[8]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[9]
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[8]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[9]
node credit_available_lo_lo = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_hi = cat(states[2].vc_sel.`0`[4], states[2].vc_sel.`0`[3])
node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[2].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[2].vc_sel.`0`[6], states[2].vc_sel.`0`[5])
node credit_available_hi_hi_hi = cat(states[2].vc_sel.`0`[9], states[2].vc_sel.`0`[8])
node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[2].vc_sel.`0`[7])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_hi_1 = cat(states[2].vc_sel.`1`[4], states[2].vc_sel.`1`[3])
node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, states[2].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[2].vc_sel.`1`[6], states[2].vc_sel.`1`[5])
node credit_available_hi_hi_hi_1 = cat(states[2].vc_sel.`1`[9], states[2].vc_sel.`1`[8])
node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, states[2].vc_sel.`1`[7])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node _credit_available_T_2 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_lo_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_2 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, io.out_credit_available.`0`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_2 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, io.out_credit_available.`0`[7])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_3 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`1`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`1`[7])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_4 = cat(credit_available_hi_3, credit_available_lo_3)
node _credit_available_T_5 = cat(_credit_available_T_4, _credit_available_T_3)
node _credit_available_T_6 = and(_credit_available_T_2, _credit_available_T_5)
node credit_available = neq(_credit_available_T_6, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[8], states[2].vc_sel.`0`[8]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[9], states[2].vc_sel.`0`[9]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[8], states[2].vc_sel.`1`[8]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[9], states[2].vc_sel.`1`[9]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_117 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_118 = and(_T_117, input_buffer.io.deq[2].bits.tail)
when _T_118 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_4 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_hi_4 = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3])
node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, states[3].vc_sel.`0`[2])
node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5])
node credit_available_hi_hi_hi_4 = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8])
node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, states[3].vc_sel.`0`[7])
node credit_available_hi_4 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_7 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_5 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_hi_5 = cat(states[3].vc_sel.`1`[4], states[3].vc_sel.`1`[3])
node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, states[3].vc_sel.`1`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(states[3].vc_sel.`1`[6], states[3].vc_sel.`1`[5])
node credit_available_hi_hi_hi_5 = cat(states[3].vc_sel.`1`[9], states[3].vc_sel.`1`[8])
node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, states[3].vc_sel.`1`[7])
node credit_available_hi_5 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_8 = cat(credit_available_hi_5, credit_available_lo_5)
node _credit_available_T_9 = cat(_credit_available_T_8, _credit_available_T_7)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_6 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_6, io.out_credit_available.`0`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_6 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_6, io.out_credit_available.`0`[7])
node credit_available_hi_6 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_10 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_7 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_7 = cat(credit_available_lo_hi_hi_7, io.out_credit_available.`1`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_7 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_7 = cat(credit_available_hi_hi_hi_7, io.out_credit_available.`1`[7])
node credit_available_hi_7 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_11 = cat(credit_available_hi_7, credit_available_lo_7)
node _credit_available_T_12 = cat(_credit_available_T_11, _credit_available_T_10)
node _credit_available_T_13 = and(_credit_available_T_9, _credit_available_T_12)
node credit_available_1 = neq(_credit_available_T_13, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_1)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[8], states[3].vc_sel.`1`[8]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[9], states[3].vc_sel.`1`[9]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_119 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_120 = and(_T_119, input_buffer.io.deq[3].bits.tail)
when _T_120 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_8 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_hi_8 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3])
node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_8, states[4].vc_sel.`0`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5])
node credit_available_hi_hi_hi_8 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8])
node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_8, states[4].vc_sel.`0`[7])
node credit_available_hi_8 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_14 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_lo_9 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_hi_9 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3])
node credit_available_lo_hi_9 = cat(credit_available_lo_hi_hi_9, states[4].vc_sel.`1`[2])
node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[4].vc_sel.`1`[6], states[4].vc_sel.`1`[5])
node credit_available_hi_hi_hi_9 = cat(states[4].vc_sel.`1`[9], states[4].vc_sel.`1`[8])
node credit_available_hi_hi_9 = cat(credit_available_hi_hi_hi_9, states[4].vc_sel.`1`[7])
node credit_available_hi_9 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_15 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_16 = cat(_credit_available_T_15, _credit_available_T_14)
node credit_available_lo_lo_10 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_10 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_10, io.out_credit_available.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_10 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_10, io.out_credit_available.`0`[7])
node credit_available_hi_10 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_17 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_11 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_11 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_11 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`1`[7])
node credit_available_hi_11 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_18 = cat(credit_available_hi_11, credit_available_lo_11)
node _credit_available_T_19 = cat(_credit_available_T_18, _credit_available_T_17)
node _credit_available_T_20 = and(_credit_available_T_16, _credit_available_T_19)
node credit_available_2 = neq(_credit_available_T_20, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_2)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[8], states[4].vc_sel.`1`[8]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[9], states[4].vc_sel.`1`[9]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_121 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_122 = and(_T_121, input_buffer.io.deq[4].bits.tail)
when _T_122 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_12 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_hi_12 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3])
node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_12, states[5].vc_sel.`0`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5])
node credit_available_hi_hi_hi_12 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8])
node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_12, states[5].vc_sel.`0`[7])
node credit_available_hi_12 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_21 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_13 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_hi_13 = cat(states[5].vc_sel.`1`[4], states[5].vc_sel.`1`[3])
node credit_available_lo_hi_13 = cat(credit_available_lo_hi_hi_13, states[5].vc_sel.`1`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(states[5].vc_sel.`1`[6], states[5].vc_sel.`1`[5])
node credit_available_hi_hi_hi_13 = cat(states[5].vc_sel.`1`[9], states[5].vc_sel.`1`[8])
node credit_available_hi_hi_13 = cat(credit_available_hi_hi_hi_13, states[5].vc_sel.`1`[7])
node credit_available_hi_13 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_22 = cat(credit_available_hi_13, credit_available_lo_13)
node _credit_available_T_23 = cat(_credit_available_T_22, _credit_available_T_21)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_14 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_14, io.out_credit_available.`0`[2])
node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_14 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_14, io.out_credit_available.`0`[7])
node credit_available_hi_14 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_24 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_15 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`1`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_15 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`1`[7])
node credit_available_hi_15 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_25 = cat(credit_available_hi_15, credit_available_lo_15)
node _credit_available_T_26 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_27 = and(_credit_available_T_23, _credit_available_T_26)
node credit_available_3 = neq(_credit_available_T_27, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_3)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[8], states[5].vc_sel.`1`[8]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[9], states[5].vc_sel.`1`[9]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_123 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_124 = and(_T_123, input_buffer.io.deq[5].bits.tail)
when _T_124 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_16 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_hi_16 = cat(states[6].vc_sel.`0`[4], states[6].vc_sel.`0`[3])
node credit_available_lo_hi_16 = cat(credit_available_lo_hi_hi_16, states[6].vc_sel.`0`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[6].vc_sel.`0`[6], states[6].vc_sel.`0`[5])
node credit_available_hi_hi_hi_16 = cat(states[6].vc_sel.`0`[9], states[6].vc_sel.`0`[8])
node credit_available_hi_hi_16 = cat(credit_available_hi_hi_hi_16, states[6].vc_sel.`0`[7])
node credit_available_hi_16 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_28 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_17 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_hi_17 = cat(states[6].vc_sel.`1`[4], states[6].vc_sel.`1`[3])
node credit_available_lo_hi_17 = cat(credit_available_lo_hi_hi_17, states[6].vc_sel.`1`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[6].vc_sel.`1`[6], states[6].vc_sel.`1`[5])
node credit_available_hi_hi_hi_17 = cat(states[6].vc_sel.`1`[9], states[6].vc_sel.`1`[8])
node credit_available_hi_hi_17 = cat(credit_available_hi_hi_hi_17, states[6].vc_sel.`1`[7])
node credit_available_hi_17 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_29 = cat(credit_available_hi_17, credit_available_lo_17)
node _credit_available_T_30 = cat(_credit_available_T_29, _credit_available_T_28)
node credit_available_lo_lo_18 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_18 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_18 = cat(credit_available_lo_hi_hi_18, io.out_credit_available.`0`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_18 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_18 = cat(credit_available_hi_hi_hi_18, io.out_credit_available.`0`[7])
node credit_available_hi_18 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_31 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_lo_19 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_19 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_19 = cat(credit_available_lo_hi_hi_19, io.out_credit_available.`1`[2])
node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_19 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_19 = cat(credit_available_hi_hi_hi_19, io.out_credit_available.`1`[7])
node credit_available_hi_19 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_32 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_33 = cat(_credit_available_T_32, _credit_available_T_31)
node _credit_available_T_34 = and(_credit_available_T_30, _credit_available_T_33)
node credit_available_4 = neq(_credit_available_T_34, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_4)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[8], states[6].vc_sel.`0`[8]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[9], states[6].vc_sel.`0`[9]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[8], states[6].vc_sel.`1`[8]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[9], states[6].vc_sel.`1`[9]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_125 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_126 = and(_T_125, input_buffer.io.deq[6].bits.tail)
when _T_126 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_20 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_hi_20 = cat(states[7].vc_sel.`0`[4], states[7].vc_sel.`0`[3])
node credit_available_lo_hi_20 = cat(credit_available_lo_hi_hi_20, states[7].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(states[7].vc_sel.`0`[6], states[7].vc_sel.`0`[5])
node credit_available_hi_hi_hi_20 = cat(states[7].vc_sel.`0`[9], states[7].vc_sel.`0`[8])
node credit_available_hi_hi_20 = cat(credit_available_hi_hi_hi_20, states[7].vc_sel.`0`[7])
node credit_available_hi_20 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_35 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_21 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_hi_21 = cat(states[7].vc_sel.`1`[4], states[7].vc_sel.`1`[3])
node credit_available_lo_hi_21 = cat(credit_available_lo_hi_hi_21, states[7].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(states[7].vc_sel.`1`[6], states[7].vc_sel.`1`[5])
node credit_available_hi_hi_hi_21 = cat(states[7].vc_sel.`1`[9], states[7].vc_sel.`1`[8])
node credit_available_hi_hi_21 = cat(credit_available_hi_hi_hi_21, states[7].vc_sel.`1`[7])
node credit_available_hi_21 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_36 = cat(credit_available_hi_21, credit_available_lo_21)
node _credit_available_T_37 = cat(_credit_available_T_36, _credit_available_T_35)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_22 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_22 = cat(credit_available_lo_hi_hi_22, io.out_credit_available.`0`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_22 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_22 = cat(credit_available_hi_hi_hi_22, io.out_credit_available.`0`[7])
node credit_available_hi_22 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_38 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_23 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_23 = cat(credit_available_lo_hi_hi_23, io.out_credit_available.`1`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_23 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_23 = cat(credit_available_hi_hi_hi_23, io.out_credit_available.`1`[7])
node credit_available_hi_23 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_39 = cat(credit_available_hi_23, credit_available_lo_23)
node _credit_available_T_40 = cat(_credit_available_T_39, _credit_available_T_38)
node _credit_available_T_41 = and(_credit_available_T_37, _credit_available_T_40)
node credit_available_5 = neq(_credit_available_T_41, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_5)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[8], states[7].vc_sel.`0`[8]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[9], states[7].vc_sel.`0`[9]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[8], states[7].vc_sel.`1`[8]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[9], states[7].vc_sel.`1`[9]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_127 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_128 = and(_T_127, input_buffer.io.deq[7].bits.tail)
when _T_128 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node credit_available_lo_lo_24 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0])
node credit_available_lo_hi_hi_24 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3])
node credit_available_lo_hi_24 = cat(credit_available_lo_hi_hi_24, states[8].vc_sel.`0`[2])
node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5])
node credit_available_hi_hi_hi_24 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8])
node credit_available_hi_hi_24 = cat(credit_available_hi_hi_hi_24, states[8].vc_sel.`0`[7])
node credit_available_hi_24 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_42 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_25 = cat(states[8].vc_sel.`1`[1], states[8].vc_sel.`1`[0])
node credit_available_lo_hi_hi_25 = cat(states[8].vc_sel.`1`[4], states[8].vc_sel.`1`[3])
node credit_available_lo_hi_25 = cat(credit_available_lo_hi_hi_25, states[8].vc_sel.`1`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[8].vc_sel.`1`[6], states[8].vc_sel.`1`[5])
node credit_available_hi_hi_hi_25 = cat(states[8].vc_sel.`1`[9], states[8].vc_sel.`1`[8])
node credit_available_hi_hi_25 = cat(credit_available_hi_hi_hi_25, states[8].vc_sel.`1`[7])
node credit_available_hi_25 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_43 = cat(credit_available_hi_25, credit_available_lo_25)
node _credit_available_T_44 = cat(_credit_available_T_43, _credit_available_T_42)
node credit_available_lo_lo_26 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_26 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_26 = cat(credit_available_lo_hi_hi_26, io.out_credit_available.`0`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_26 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_26 = cat(credit_available_hi_hi_hi_26, io.out_credit_available.`0`[7])
node credit_available_hi_26 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_45 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_27 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_27 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_27 = cat(credit_available_lo_hi_hi_27, io.out_credit_available.`1`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_27 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_27 = cat(credit_available_hi_hi_hi_27, io.out_credit_available.`1`[7])
node credit_available_hi_27 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_46 = cat(credit_available_hi_27, credit_available_lo_27)
node _credit_available_T_47 = cat(_credit_available_T_46, _credit_available_T_45)
node _credit_available_T_48 = and(_credit_available_T_44, _credit_available_T_47)
node credit_available_6 = neq(_credit_available_T_48, UInt<1>(0h0))
node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3))
node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_6)
node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid)
connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2
connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8]
connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[1], states[8].vc_sel.`1`[1]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[2], states[8].vc_sel.`1`[2]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[3], states[8].vc_sel.`1`[3]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[4], states[8].vc_sel.`1`[4]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[5], states[8].vc_sel.`1`[5]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[6], states[8].vc_sel.`1`[6]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[7], states[8].vc_sel.`1`[7]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[8], states[8].vc_sel.`1`[8]
connect salloc_arb.io.in[8].bits.vc_sel.`1`[9], states[8].vc_sel.`1`[9]
connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail
node _T_129 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid)
node _T_130 = and(_T_129, input_buffer.io.deq[8].bits.tail)
when _T_130 :
connect states[8].g, UInt<3>(0h0)
connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready
node credit_available_lo_lo_28 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0])
node credit_available_lo_hi_hi_28 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3])
node credit_available_lo_hi_28 = cat(credit_available_lo_hi_hi_28, states[9].vc_sel.`0`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5])
node credit_available_hi_hi_hi_28 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8])
node credit_available_hi_hi_28 = cat(credit_available_hi_hi_hi_28, states[9].vc_sel.`0`[7])
node credit_available_hi_28 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_49 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_lo_29 = cat(states[9].vc_sel.`1`[1], states[9].vc_sel.`1`[0])
node credit_available_lo_hi_hi_29 = cat(states[9].vc_sel.`1`[4], states[9].vc_sel.`1`[3])
node credit_available_lo_hi_29 = cat(credit_available_lo_hi_hi_29, states[9].vc_sel.`1`[2])
node credit_available_lo_29 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(states[9].vc_sel.`1`[6], states[9].vc_sel.`1`[5])
node credit_available_hi_hi_hi_29 = cat(states[9].vc_sel.`1`[9], states[9].vc_sel.`1`[8])
node credit_available_hi_hi_29 = cat(credit_available_hi_hi_hi_29, states[9].vc_sel.`1`[7])
node credit_available_hi_29 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_50 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_51 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_hi_30 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_lo_hi_30 = cat(credit_available_lo_hi_hi_30, io.out_credit_available.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node credit_available_hi_hi_hi_30 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node credit_available_hi_hi_30 = cat(credit_available_hi_hi_hi_30, io.out_credit_available.`0`[7])
node credit_available_hi_30 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_52 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_hi_31 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3])
node credit_available_lo_hi_31 = cat(credit_available_lo_hi_hi_31, io.out_credit_available.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`1`[6], io.out_credit_available.`1`[5])
node credit_available_hi_hi_hi_31 = cat(io.out_credit_available.`1`[9], io.out_credit_available.`1`[8])
node credit_available_hi_hi_31 = cat(credit_available_hi_hi_hi_31, io.out_credit_available.`1`[7])
node credit_available_hi_31 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_53 = cat(credit_available_hi_31, credit_available_lo_31)
node _credit_available_T_54 = cat(_credit_available_T_53, _credit_available_T_52)
node _credit_available_T_55 = and(_credit_available_T_51, _credit_available_T_54)
node credit_available_7 = neq(_credit_available_T_55, UInt<1>(0h0))
node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3))
node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_7)
node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid)
connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2
connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8]
connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[1], states[9].vc_sel.`1`[1]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[2], states[9].vc_sel.`1`[2]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[3], states[9].vc_sel.`1`[3]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[4], states[9].vc_sel.`1`[4]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[5], states[9].vc_sel.`1`[5]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[6], states[9].vc_sel.`1`[6]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[7], states[9].vc_sel.`1`[7]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[8], states[9].vc_sel.`1`[8]
connect salloc_arb.io.in[9].bits.vc_sel.`1`[9], states[9].vc_sel.`1`[9]
connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail
node _T_131 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid)
node _T_132 = and(_T_131, input_buffer.io.deq[9].bits.tail)
when _T_132 :
connect states[9].g, UInt<3>(0h0)
connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16)
node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0)
node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0)
node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31)
node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0)
node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33)
node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0)
node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35)
node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_37
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14)
node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15)
node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16)
node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17)
node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18)
node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19)
node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29
node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_31
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2)
node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0)
node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2)
node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2)
node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1)
node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6)
node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7)
node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
wire vc_sel : { `1` : UInt<1>[10], `0` : UInt<1>[10]}
wire _vc_sel_WIRE : UInt<1>[10]
node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13)
node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14)
node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15)
node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16)
node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18)
node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_28
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30)
node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31)
node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32)
node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33)
node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34)
node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35)
node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36)
node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_47
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49)
node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50)
node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51)
node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_66
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73)
node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74)
node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75)
node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_85
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88)
node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89)
node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90)
node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91)
node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92)
node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93)
node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94)
node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_104
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106)
node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107)
node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108)
node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109)
node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110)
node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111)
node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_123
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125)
node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126)
node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_142
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148)
node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149)
node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150)
node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151)
node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_161
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0))
node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163)
node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164)
node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165)
node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166)
node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167)
node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168)
node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169)
node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170)
node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_180
connect _vc_sel_WIRE[8], _vc_sel_WIRE_9
node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0))
node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182)
node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183)
node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184)
node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185)
node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186)
node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_199
connect _vc_sel_WIRE[9], _vc_sel_WIRE_10
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_11 : UInt<1>[10]
node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201)
node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208)
node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_218
connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12
node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223)
node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224)
node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225)
node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226)
node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227)
node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_237
connect _vc_sel_WIRE_11[1], _vc_sel_WIRE_13
node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239)
node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240)
node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241)
node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242)
node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243)
node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244)
node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245)
node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246)
node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_256
connect _vc_sel_WIRE_11[2], _vc_sel_WIRE_14
node _vc_sel_T_257 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_258 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_259 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_260 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_261 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_262 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_263 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_267 = or(_vc_sel_T_257, _vc_sel_T_258)
node _vc_sel_T_268 = or(_vc_sel_T_267, _vc_sel_T_259)
node _vc_sel_T_269 = or(_vc_sel_T_268, _vc_sel_T_260)
node _vc_sel_T_270 = or(_vc_sel_T_269, _vc_sel_T_261)
node _vc_sel_T_271 = or(_vc_sel_T_270, _vc_sel_T_262)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_263)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_264)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_265)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_266)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_275
connect _vc_sel_WIRE_11[3], _vc_sel_WIRE_15
node _vc_sel_T_276 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_277 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_278 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_276, _vc_sel_T_277)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_278)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_279)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_280)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_281)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_282)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_283)
node _vc_sel_T_293 = or(_vc_sel_T_292, _vc_sel_T_284)
node _vc_sel_T_294 = or(_vc_sel_T_293, _vc_sel_T_285)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_294
connect _vc_sel_WIRE_11[4], _vc_sel_WIRE_16
node _vc_sel_T_295 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_301 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_302 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_303 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_304 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_305 = or(_vc_sel_T_295, _vc_sel_T_296)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_297)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_298)
node _vc_sel_T_308 = or(_vc_sel_T_307, _vc_sel_T_299)
node _vc_sel_T_309 = or(_vc_sel_T_308, _vc_sel_T_300)
node _vc_sel_T_310 = or(_vc_sel_T_309, _vc_sel_T_301)
node _vc_sel_T_311 = or(_vc_sel_T_310, _vc_sel_T_302)
node _vc_sel_T_312 = or(_vc_sel_T_311, _vc_sel_T_303)
node _vc_sel_T_313 = or(_vc_sel_T_312, _vc_sel_T_304)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_313
connect _vc_sel_WIRE_11[5], _vc_sel_WIRE_17
node _vc_sel_T_314 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_316 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_317 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_318 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_319 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_320 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_321 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_322 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_323 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_324 = or(_vc_sel_T_314, _vc_sel_T_315)
node _vc_sel_T_325 = or(_vc_sel_T_324, _vc_sel_T_316)
node _vc_sel_T_326 = or(_vc_sel_T_325, _vc_sel_T_317)
node _vc_sel_T_327 = or(_vc_sel_T_326, _vc_sel_T_318)
node _vc_sel_T_328 = or(_vc_sel_T_327, _vc_sel_T_319)
node _vc_sel_T_329 = or(_vc_sel_T_328, _vc_sel_T_320)
node _vc_sel_T_330 = or(_vc_sel_T_329, _vc_sel_T_321)
node _vc_sel_T_331 = or(_vc_sel_T_330, _vc_sel_T_322)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_323)
wire _vc_sel_WIRE_18 : UInt<1>
connect _vc_sel_WIRE_18, _vc_sel_T_332
connect _vc_sel_WIRE_11[6], _vc_sel_WIRE_18
node _vc_sel_T_333 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_334 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_335 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_336 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_337 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_338 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_343 = or(_vc_sel_T_333, _vc_sel_T_334)
node _vc_sel_T_344 = or(_vc_sel_T_343, _vc_sel_T_335)
node _vc_sel_T_345 = or(_vc_sel_T_344, _vc_sel_T_336)
node _vc_sel_T_346 = or(_vc_sel_T_345, _vc_sel_T_337)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_338)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_339)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_340)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_341)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_342)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_351
connect _vc_sel_WIRE_11[7], _vc_sel_WIRE_19
node _vc_sel_T_352 = mux(_vc_sel_T, states[0].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_353 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_361 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[8], UInt<1>(0h0))
node _vc_sel_T_362 = or(_vc_sel_T_352, _vc_sel_T_353)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_354)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_355)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_356)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_357)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_358)
node _vc_sel_T_368 = or(_vc_sel_T_367, _vc_sel_T_359)
node _vc_sel_T_369 = or(_vc_sel_T_368, _vc_sel_T_360)
node _vc_sel_T_370 = or(_vc_sel_T_369, _vc_sel_T_361)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_370
connect _vc_sel_WIRE_11[8], _vc_sel_WIRE_20
node _vc_sel_T_371 = mux(_vc_sel_T, states[0].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_376 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_377 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_378 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_379 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_380 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[9], UInt<1>(0h0))
node _vc_sel_T_381 = or(_vc_sel_T_371, _vc_sel_T_372)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_373)
node _vc_sel_T_383 = or(_vc_sel_T_382, _vc_sel_T_374)
node _vc_sel_T_384 = or(_vc_sel_T_383, _vc_sel_T_375)
node _vc_sel_T_385 = or(_vc_sel_T_384, _vc_sel_T_376)
node _vc_sel_T_386 = or(_vc_sel_T_385, _vc_sel_T_377)
node _vc_sel_T_387 = or(_vc_sel_T_386, _vc_sel_T_378)
node _vc_sel_T_388 = or(_vc_sel_T_387, _vc_sel_T_379)
node _vc_sel_T_389 = or(_vc_sel_T_388, _vc_sel_T_380)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_389
connect _vc_sel_WIRE_11[9], _vc_sel_WIRE_21
connect vc_sel.`1`, _vc_sel_WIRE_11
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8])
node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9])
node _channel_oh_T_8 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[2])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[3])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[4])
node _channel_oh_T_12 = or(_channel_oh_T_11, vc_sel.`1`[5])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`1`[6])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`1`[7])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`1`[8])
node channel_oh_1 = or(_channel_oh_T_15, vc_sel.`1`[9])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3])
node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5])
node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8])
node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8)
node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2)
node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0)
node _virt_channel_T_5 = orr(virt_channel_hi_3)
node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3)
node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1)
node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7)
node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8)
node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3])
node virt_channel_lo_hi_1 = cat(virt_channel_lo_hi_hi_1, vc_sel.`1`[2])
node virt_channel_lo_4 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[6], vc_sel.`1`[5])
node virt_channel_hi_hi_hi_1 = cat(vc_sel.`1`[9], vc_sel.`1`[8])
node virt_channel_hi_hi_1 = cat(virt_channel_hi_hi_hi_1, vc_sel.`1`[7])
node virt_channel_hi_4 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_11 = cat(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_11, 9, 8)
node virt_channel_lo_5 = bits(_virt_channel_T_11, 7, 0)
node _virt_channel_T_12 = orr(virt_channel_hi_5)
node _virt_channel_T_13 = or(virt_channel_hi_5, virt_channel_lo_5)
node virt_channel_hi_6 = bits(_virt_channel_T_13, 7, 4)
node virt_channel_lo_6 = bits(_virt_channel_T_13, 3, 0)
node _virt_channel_T_14 = orr(virt_channel_hi_6)
node _virt_channel_T_15 = or(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_15, 3, 2)
node virt_channel_lo_7 = bits(_virt_channel_T_15, 1, 0)
node _virt_channel_T_16 = orr(virt_channel_hi_7)
node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_7)
node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1)
node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18)
node _virt_channel_T_20 = cat(_virt_channel_T_14, _virt_channel_T_19)
node _virt_channel_T_21 = cat(_virt_channel_T_12, _virt_channel_T_20)
node _virt_channel_T_22 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0))
node _virt_channel_T_23 = mux(channel_oh_1, _virt_channel_T_21, UInt<1>(0h0))
node _virt_channel_T_24 = or(_virt_channel_T_22, _virt_channel_T_23)
wire virt_channel : UInt<4>
connect virt_channel, _virt_channel_T_24
node _T_133 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_133 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15)
node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16)
node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17)
node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18)
node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15)
node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16)
node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17)
node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18)
node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15)
node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16)
node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17)
node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18)
node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8)
node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15)
node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16)
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18)
node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30)
node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31)
node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32)
node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33)
node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34)
node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35)
node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36)
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49)
node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50)
node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51)
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75)
node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87)
node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88)
node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89)
node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90)
node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91)
node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92)
node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93)
node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94)
node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`0`[8]
invalidate states[0].vc_sel.`0`[9]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`1`[3]
invalidate states[0].vc_sel.`1`[4]
invalidate states[0].vc_sel.`1`[5]
invalidate states[0].vc_sel.`1`[6]
invalidate states[0].vc_sel.`1`[7]
invalidate states[0].vc_sel.`1`[8]
invalidate states[0].vc_sel.`1`[9]
invalidate states[0].g
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`0`[3]
invalidate states[1].vc_sel.`0`[4]
invalidate states[1].vc_sel.`0`[5]
invalidate states[1].vc_sel.`0`[6]
invalidate states[1].vc_sel.`0`[7]
invalidate states[1].vc_sel.`0`[8]
invalidate states[1].vc_sel.`0`[9]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`1`[3]
invalidate states[1].vc_sel.`1`[4]
invalidate states[1].vc_sel.`1`[5]
invalidate states[1].vc_sel.`1`[6]
invalidate states[1].vc_sel.`1`[7]
invalidate states[1].vc_sel.`1`[8]
invalidate states[1].vc_sel.`1`[9]
invalidate states[1].g
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[6], UInt<1>(0h0)
connect states[2].vc_sel.`0`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[8], UInt<1>(0h0)
connect states[2].vc_sel.`0`[9], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[6], UInt<1>(0h0)
connect states[3].vc_sel.`0`[7], UInt<1>(0h0)
connect states[3].vc_sel.`0`[8], UInt<1>(0h0)
connect states[3].vc_sel.`0`[9], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[1], UInt<1>(0h0)
connect states[3].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[4].vc_sel.`0`[8], UInt<1>(0h0)
connect states[4].vc_sel.`0`[9], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`0`[8], UInt<1>(0h0)
connect states[5].vc_sel.`0`[9], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`0`[8], UInt<1>(0h0)
connect states[6].vc_sel.`0`[9], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`0`[8], UInt<1>(0h0)
connect states[7].vc_sel.`0`[9], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[8].vc_sel.`0`[0], UInt<1>(0h0)
connect states[8].vc_sel.`0`[1], UInt<1>(0h0)
connect states[8].vc_sel.`0`[2], UInt<1>(0h0)
connect states[8].vc_sel.`0`[3], UInt<1>(0h0)
connect states[8].vc_sel.`0`[4], UInt<1>(0h0)
connect states[8].vc_sel.`0`[5], UInt<1>(0h0)
connect states[8].vc_sel.`0`[6], UInt<1>(0h0)
connect states[8].vc_sel.`0`[7], UInt<1>(0h0)
connect states[8].vc_sel.`0`[8], UInt<1>(0h0)
connect states[8].vc_sel.`0`[9], UInt<1>(0h0)
connect states[8].vc_sel.`1`[0], UInt<1>(0h0)
connect states[8].vc_sel.`1`[1], UInt<1>(0h0)
connect states[8].vc_sel.`1`[2], UInt<1>(0h0)
connect states[9].vc_sel.`0`[0], UInt<1>(0h0)
connect states[9].vc_sel.`0`[1], UInt<1>(0h0)
connect states[9].vc_sel.`0`[2], UInt<1>(0h0)
connect states[9].vc_sel.`0`[3], UInt<1>(0h0)
connect states[9].vc_sel.`0`[4], UInt<1>(0h0)
connect states[9].vc_sel.`0`[5], UInt<1>(0h0)
connect states[9].vc_sel.`0`[6], UInt<1>(0h0)
connect states[9].vc_sel.`0`[7], UInt<1>(0h0)
connect states[9].vc_sel.`0`[8], UInt<1>(0h0)
connect states[9].vc_sel.`0`[9], UInt<1>(0h0)
connect states[9].vc_sel.`1`[0], UInt<1>(0h0)
connect states[9].vc_sel.`1`[1], UInt<1>(0h0)
connect states[9].vc_sel.`1`[2], UInt<1>(0h0)
node _T_134 = asUInt(reset)
when _T_134 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0)
connect states[8].g, UInt<3>(0h0)
connect states[9].g, UInt<3>(0h0) | module InputUnit_123( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_8, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_9, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_8, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_9, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_8, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_9, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [9:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_9; // @[InputUnit.scala:266:32]
wire vcalloc_vals_8; // @[InputUnit.scala:266:32]
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_8_g; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_9_g; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_8; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [9:0] mask; // @[InputUnit.scala:250:21]
wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, 2'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_2 ? 20'h1000 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_6 ? 20'h10000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71]
wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7 | vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_62 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_62( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_40 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_40( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_9 :
input clock : Clock
input reset : Reset
output io : { req : { flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}}, resp : { `1` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `0` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, channel_status : { flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6]}, out_allocs : { `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[6]}}
regreset mask : UInt<2>, clock, reset, UInt<2>(0h0)
wire in_arb_reqs : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}[2]
wire in_arb_vals : UInt<1>[2]
node _in_arb_filter_T = cat(in_arb_vals[1], in_arb_vals[0])
node _in_arb_filter_T_1 = cat(in_arb_vals[1], in_arb_vals[0])
node _in_arb_filter_T_2 = not(mask)
node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2)
node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3)
node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0)
node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1)
node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2)
node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3)
node _in_arb_filter_T_9 = mux(_in_arb_filter_T_8, UInt<4>(0h8), UInt<4>(0h0))
node _in_arb_filter_T_10 = mux(_in_arb_filter_T_7, UInt<4>(0h4), _in_arb_filter_T_9)
node _in_arb_filter_T_11 = mux(_in_arb_filter_T_6, UInt<4>(0h2), _in_arb_filter_T_10)
node in_arb_filter = mux(_in_arb_filter_T_5, UInt<4>(0h1), _in_arb_filter_T_11)
node _in_arb_sel_T = bits(in_arb_filter, 1, 0)
node _in_arb_sel_T_1 = shr(in_arb_filter, 2)
node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1)
node _T = or(in_arb_vals[0], in_arb_vals[1])
when _T :
node _mask_T = not(UInt<1>(0h0))
node _mask_T_1 = not(UInt<2>(0h0))
node _mask_T_2 = bits(in_arb_sel, 0, 0)
node _mask_T_3 = bits(in_arb_sel, 1, 1)
node _mask_T_4 = mux(_mask_T_2, _mask_T, UInt<1>(0h0))
node _mask_T_5 = mux(_mask_T_3, _mask_T_1, UInt<1>(0h0))
node _mask_T_6 = or(_mask_T_4, _mask_T_5)
wire _mask_WIRE : UInt<2>
connect _mask_WIRE, _mask_T_6
connect mask, _mask_WIRE
node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T)
connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1
node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T)
connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1
node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T)
connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1
node _in_arb_reqs_0_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_3_T_1 = and(io.req.`0`.bits.vc_sel.`0`[3], _in_arb_reqs_0_0_3_T)
connect in_arb_reqs[0].`0`[3], _in_arb_reqs_0_0_3_T_1
node _in_arb_reqs_0_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_4_T_1 = and(io.req.`0`.bits.vc_sel.`0`[4], _in_arb_reqs_0_0_4_T)
connect in_arb_reqs[0].`0`[4], _in_arb_reqs_0_0_4_T_1
node _in_arb_reqs_0_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_5_T_1 = and(io.req.`0`.bits.vc_sel.`0`[5], _in_arb_reqs_0_0_5_T)
connect in_arb_reqs[0].`0`[5], _in_arb_reqs_0_0_5_T_1
node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T)
connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1
node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T)
connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1
node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1])
node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2])
node _in_arb_vals_0_T_2 = or(_in_arb_vals_0_T_1, in_arb_reqs[0].`0`[3])
node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`0`[4])
node _in_arb_vals_0_T_4 = or(_in_arb_vals_0_T_3, in_arb_reqs[0].`0`[5])
node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`1`[0])
node _in_arb_vals_0_T_6 = or(_in_arb_vals_0_T_5, in_arb_reqs[0].`2`[0])
node _in_arb_vals_0_T_7 = and(io.req.`0`.valid, _in_arb_vals_0_T_6)
connect in_arb_vals[0], _in_arb_vals_0_T_7
node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T)
connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1
node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T)
connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1
node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T)
connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1
node _in_arb_reqs_1_0_3_T = eq(io.channel_status.`0`[3].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_3_T_1 = and(io.req.`1`.bits.vc_sel.`0`[3], _in_arb_reqs_1_0_3_T)
connect in_arb_reqs[1].`0`[3], _in_arb_reqs_1_0_3_T_1
node _in_arb_reqs_1_0_4_T = eq(io.channel_status.`0`[4].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_4_T_1 = and(io.req.`1`.bits.vc_sel.`0`[4], _in_arb_reqs_1_0_4_T)
connect in_arb_reqs[1].`0`[4], _in_arb_reqs_1_0_4_T_1
node _in_arb_reqs_1_0_5_T = eq(io.channel_status.`0`[5].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_5_T_1 = and(io.req.`1`.bits.vc_sel.`0`[5], _in_arb_reqs_1_0_5_T)
connect in_arb_reqs[1].`0`[5], _in_arb_reqs_1_0_5_T_1
node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T)
connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1
node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T)
connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1
node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1])
node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2])
node _in_arb_vals_1_T_2 = or(_in_arb_vals_1_T_1, in_arb_reqs[1].`0`[3])
node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`0`[4])
node _in_arb_vals_1_T_4 = or(_in_arb_vals_1_T_3, in_arb_reqs[1].`0`[5])
node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`1`[0])
node _in_arb_vals_1_T_6 = or(_in_arb_vals_1_T_5, in_arb_reqs[1].`2`[0])
node _in_arb_vals_1_T_7 = and(io.req.`1`.valid, _in_arb_vals_1_T_6)
connect in_arb_vals[1], _in_arb_vals_1_T_7
connect io.req.`0`.ready, UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h0)
wire in_alloc : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
node _in_flow_T = bits(in_arb_sel, 0, 0)
node _in_flow_T_1 = bits(in_arb_sel, 1, 1)
wire in_flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _in_flow_T_2 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_3 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_4 = or(_in_flow_T_2, _in_flow_T_3)
wire _in_flow_WIRE : UInt<2>
connect _in_flow_WIRE, _in_flow_T_4
connect in_flow.egress_node_id, _in_flow_WIRE
node _in_flow_T_5 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_6 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_7 = or(_in_flow_T_5, _in_flow_T_6)
wire _in_flow_WIRE_1 : UInt<4>
connect _in_flow_WIRE_1, _in_flow_T_7
connect in_flow.egress_node, _in_flow_WIRE_1
node _in_flow_T_8 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_9 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_10 = or(_in_flow_T_8, _in_flow_T_9)
wire _in_flow_WIRE_2 : UInt<2>
connect _in_flow_WIRE_2, _in_flow_T_10
connect in_flow.ingress_node_id, _in_flow_WIRE_2
node _in_flow_T_11 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_12 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_13 = or(_in_flow_T_11, _in_flow_T_12)
wire _in_flow_WIRE_3 : UInt<4>
connect _in_flow_WIRE_3, _in_flow_T_13
connect in_flow.ingress_node, _in_flow_WIRE_3
node _in_flow_T_14 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_15 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_16 = or(_in_flow_T_14, _in_flow_T_15)
wire _in_flow_WIRE_4 : UInt<2>
connect _in_flow_WIRE_4, _in_flow_T_16
connect in_flow.vnet_id, _in_flow_WIRE_4
node _in_vc_T = bits(in_arb_sel, 0, 0)
node _in_vc_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_T_2 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_3 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_4 = or(_in_vc_T_2, _in_vc_T_3)
wire in_vc : UInt<3>
connect in_vc, _in_vc_T_4
node _in_vc_sel_T = bits(in_arb_sel, 0, 0)
node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1)
wire in_vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
wire _in_vc_sel_WIRE : UInt<1>[6]
node _in_vc_sel_T_2 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_3 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_4 = or(_in_vc_sel_T_2, _in_vc_sel_T_3)
wire _in_vc_sel_WIRE_1 : UInt<1>
connect _in_vc_sel_WIRE_1, _in_vc_sel_T_4
connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1
node _in_vc_sel_T_5 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_6 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_7 = or(_in_vc_sel_T_5, _in_vc_sel_T_6)
wire _in_vc_sel_WIRE_2 : UInt<1>
connect _in_vc_sel_WIRE_2, _in_vc_sel_T_7
connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2
node _in_vc_sel_T_8 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_9 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_10 = or(_in_vc_sel_T_8, _in_vc_sel_T_9)
wire _in_vc_sel_WIRE_3 : UInt<1>
connect _in_vc_sel_WIRE_3, _in_vc_sel_T_10
connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3
node _in_vc_sel_T_11 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_12 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[3], UInt<1>(0h0))
node _in_vc_sel_T_13 = or(_in_vc_sel_T_11, _in_vc_sel_T_12)
wire _in_vc_sel_WIRE_4 : UInt<1>
connect _in_vc_sel_WIRE_4, _in_vc_sel_T_13
connect _in_vc_sel_WIRE[3], _in_vc_sel_WIRE_4
node _in_vc_sel_T_14 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_15 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[4], UInt<1>(0h0))
node _in_vc_sel_T_16 = or(_in_vc_sel_T_14, _in_vc_sel_T_15)
wire _in_vc_sel_WIRE_5 : UInt<1>
connect _in_vc_sel_WIRE_5, _in_vc_sel_T_16
connect _in_vc_sel_WIRE[4], _in_vc_sel_WIRE_5
node _in_vc_sel_T_17 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_18 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[5], UInt<1>(0h0))
node _in_vc_sel_T_19 = or(_in_vc_sel_T_17, _in_vc_sel_T_18)
wire _in_vc_sel_WIRE_6 : UInt<1>
connect _in_vc_sel_WIRE_6, _in_vc_sel_T_19
connect _in_vc_sel_WIRE[5], _in_vc_sel_WIRE_6
connect in_vc_sel.`0`, _in_vc_sel_WIRE
wire _in_vc_sel_WIRE_7 : UInt<1>[1]
node _in_vc_sel_T_20 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_21 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_22 = or(_in_vc_sel_T_20, _in_vc_sel_T_21)
wire _in_vc_sel_WIRE_8 : UInt<1>
connect _in_vc_sel_WIRE_8, _in_vc_sel_T_22
connect _in_vc_sel_WIRE_7[0], _in_vc_sel_WIRE_8
connect in_vc_sel.`1`, _in_vc_sel_WIRE_7
wire _in_vc_sel_WIRE_9 : UInt<1>[1]
node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_25 = or(_in_vc_sel_T_23, _in_vc_sel_T_24)
wire _in_vc_sel_WIRE_10 : UInt<1>
connect _in_vc_sel_WIRE_10, _in_vc_sel_T_25
connect _in_vc_sel_WIRE_9[0], _in_vc_sel_WIRE_10
connect in_vc_sel.`2`, _in_vc_sel_WIRE_9
node _T_1 = or(in_arb_vals[0], in_arb_vals[1])
node _T_2 = bits(in_arb_sel, 1, 1)
node _T_3 = and(io.req.`0`.ready, io.req.`0`.valid)
node _T_4 = and(io.req.`1`.ready, io.req.`1`.valid)
node _T_5 = or(_T_3, _T_4)
node lo_hi = cat(in_vc_sel.`0`[2], in_vc_sel.`0`[1])
node lo = cat(lo_hi, in_vc_sel.`0`[0])
node hi_hi = cat(in_vc_sel.`0`[5], in_vc_sel.`0`[4])
node hi = cat(hi_hi, in_vc_sel.`0`[3])
node _T_6 = cat(hi, lo)
node hi_1 = cat(in_vc_sel.`2`[0], in_vc_sel.`1`[0])
node _T_7 = cat(hi_1, _T_6)
regreset mask_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _full_T = not(mask_1)
node _full_T_1 = and(_T_7, _full_T)
node full = cat(_T_7, _full_T_1)
node _oh_T = bits(full, 0, 0)
node _oh_T_1 = bits(full, 1, 1)
node _oh_T_2 = bits(full, 2, 2)
node _oh_T_3 = bits(full, 3, 3)
node _oh_T_4 = bits(full, 4, 4)
node _oh_T_5 = bits(full, 5, 5)
node _oh_T_6 = bits(full, 6, 6)
node _oh_T_7 = bits(full, 7, 7)
node _oh_T_8 = bits(full, 8, 8)
node _oh_T_9 = bits(full, 9, 9)
node _oh_T_10 = bits(full, 10, 10)
node _oh_T_11 = bits(full, 11, 11)
node _oh_T_12 = bits(full, 12, 12)
node _oh_T_13 = bits(full, 13, 13)
node _oh_T_14 = bits(full, 14, 14)
node _oh_T_15 = bits(full, 15, 15)
node _oh_T_16 = mux(_oh_T_15, UInt<16>(0h8000), UInt<16>(0h0))
node _oh_T_17 = mux(_oh_T_14, UInt<16>(0h4000), _oh_T_16)
node _oh_T_18 = mux(_oh_T_13, UInt<16>(0h2000), _oh_T_17)
node _oh_T_19 = mux(_oh_T_12, UInt<16>(0h1000), _oh_T_18)
node _oh_T_20 = mux(_oh_T_11, UInt<16>(0h800), _oh_T_19)
node _oh_T_21 = mux(_oh_T_10, UInt<16>(0h400), _oh_T_20)
node _oh_T_22 = mux(_oh_T_9, UInt<16>(0h200), _oh_T_21)
node _oh_T_23 = mux(_oh_T_8, UInt<16>(0h100), _oh_T_22)
node _oh_T_24 = mux(_oh_T_7, UInt<16>(0h80), _oh_T_23)
node _oh_T_25 = mux(_oh_T_6, UInt<16>(0h40), _oh_T_24)
node _oh_T_26 = mux(_oh_T_5, UInt<16>(0h20), _oh_T_25)
node _oh_T_27 = mux(_oh_T_4, UInt<16>(0h10), _oh_T_26)
node _oh_T_28 = mux(_oh_T_3, UInt<16>(0h8), _oh_T_27)
node _oh_T_29 = mux(_oh_T_2, UInt<16>(0h4), _oh_T_28)
node _oh_T_30 = mux(_oh_T_1, UInt<16>(0h2), _oh_T_29)
node oh = mux(_oh_T, UInt<16>(0h1), _oh_T_30)
node _sel_T = bits(oh, 7, 0)
node _sel_T_1 = shr(oh, 8)
node sel = or(_sel_T, _sel_T_1)
when _T_5 :
node _mask_T_7 = bits(sel, 0, 0)
node _mask_T_8 = not(UInt<1>(0h0))
node _mask_T_9 = bits(sel, 1, 1)
node _mask_T_10 = not(UInt<2>(0h0))
node _mask_T_11 = bits(sel, 2, 2)
node _mask_T_12 = not(UInt<3>(0h0))
node _mask_T_13 = bits(sel, 3, 3)
node _mask_T_14 = not(UInt<4>(0h0))
node _mask_T_15 = bits(sel, 4, 4)
node _mask_T_16 = not(UInt<5>(0h0))
node _mask_T_17 = bits(sel, 5, 5)
node _mask_T_18 = not(UInt<6>(0h0))
node _mask_T_19 = bits(sel, 6, 6)
node _mask_T_20 = not(UInt<7>(0h0))
node _mask_T_21 = bits(sel, 7, 7)
node _mask_T_22 = not(UInt<8>(0h0))
node _mask_T_23 = mux(_mask_T_21, _mask_T_22, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_19, _mask_T_20, _mask_T_23)
node _mask_T_25 = mux(_mask_T_17, _mask_T_18, _mask_T_24)
node _mask_T_26 = mux(_mask_T_15, _mask_T_16, _mask_T_25)
node _mask_T_27 = mux(_mask_T_13, _mask_T_14, _mask_T_26)
node _mask_T_28 = mux(_mask_T_11, _mask_T_12, _mask_T_27)
node _mask_T_29 = mux(_mask_T_9, _mask_T_10, _mask_T_28)
node _mask_T_30 = mux(_mask_T_7, _mask_T_8, _mask_T_29)
connect mask_1, _mask_T_30
wire _WIRE : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
wire _WIRE_1 : UInt<8>
connect _WIRE_1, sel
node _T_8 = bits(_WIRE_1, 0, 0)
connect _WIRE.`0`[0], _T_8
node _T_9 = bits(_WIRE_1, 1, 1)
connect _WIRE.`0`[1], _T_9
node _T_10 = bits(_WIRE_1, 2, 2)
connect _WIRE.`0`[2], _T_10
node _T_11 = bits(_WIRE_1, 3, 3)
connect _WIRE.`0`[3], _T_11
node _T_12 = bits(_WIRE_1, 4, 4)
connect _WIRE.`0`[4], _T_12
node _T_13 = bits(_WIRE_1, 5, 5)
connect _WIRE.`0`[5], _T_13
node _T_14 = bits(_WIRE_1, 6, 6)
connect _WIRE.`1`[0], _T_14
node _T_15 = bits(_WIRE_1, 7, 7)
connect _WIRE.`2`[0], _T_15
wire _WIRE_2 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[6]}
connect _WIRE_2.`0`[0], UInt<1>(0h0)
connect _WIRE_2.`0`[1], UInt<1>(0h0)
connect _WIRE_2.`0`[2], UInt<1>(0h0)
connect _WIRE_2.`0`[3], UInt<1>(0h0)
connect _WIRE_2.`0`[4], UInt<1>(0h0)
connect _WIRE_2.`0`[5], UInt<1>(0h0)
connect _WIRE_2.`1`[0], UInt<1>(0h0)
connect _WIRE_2.`2`[0], UInt<1>(0h0)
node _T_16 = mux(_T_1, _WIRE, _WIRE_2)
connect in_alloc.`0`, _T_16.`0`
connect in_alloc.`1`, _T_16.`1`
connect in_alloc.`2`, _T_16.`2`
node _io_req_0_ready_T = bits(in_arb_sel, 0, 0)
connect io.req.`0`.ready, _io_req_0_ready_T
connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`0`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`0`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`0`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0]
node lo_hi_1 = cat(io.resp.`0`.vc_sel.`0`[2], io.resp.`0`.vc_sel.`0`[1])
node lo_1 = cat(lo_hi_1, io.resp.`0`.vc_sel.`0`[0])
node hi_hi_1 = cat(io.resp.`0`.vc_sel.`0`[5], io.resp.`0`.vc_sel.`0`[4])
node hi_2 = cat(hi_hi_1, io.resp.`0`.vc_sel.`0`[3])
node _T_17 = cat(hi_2, lo_1)
node hi_3 = cat(io.resp.`0`.vc_sel.`2`[0], io.resp.`0`.vc_sel.`1`[0])
node _T_18 = cat(hi_3, _T_17)
node _T_19 = bits(_T_18, 0, 0)
node _T_20 = bits(_T_18, 1, 1)
node _T_21 = bits(_T_18, 2, 2)
node _T_22 = bits(_T_18, 3, 3)
node _T_23 = bits(_T_18, 4, 4)
node _T_24 = bits(_T_18, 5, 5)
node _T_25 = bits(_T_18, 6, 6)
node _T_26 = bits(_T_18, 7, 7)
node _T_27 = add(_T_19, _T_20)
node _T_28 = bits(_T_27, 1, 0)
node _T_29 = add(_T_21, _T_22)
node _T_30 = bits(_T_29, 1, 0)
node _T_31 = add(_T_28, _T_30)
node _T_32 = bits(_T_31, 2, 0)
node _T_33 = add(_T_23, _T_24)
node _T_34 = bits(_T_33, 1, 0)
node _T_35 = add(_T_25, _T_26)
node _T_36 = bits(_T_35, 1, 0)
node _T_37 = add(_T_34, _T_36)
node _T_38 = bits(_T_37, 2, 0)
node _T_39 = add(_T_32, _T_38)
node _T_40 = bits(_T_39, 3, 0)
node _T_41 = leq(_T_40, UInt<1>(0h1))
node _T_42 = asUInt(reset)
node _T_43 = eq(_T_42, UInt<1>(0h0))
when _T_43 :
node _T_44 = eq(_T_41, UInt<1>(0h0))
when _T_44 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf
assert(clock, _T_41, UInt<1>(0h1), "") : assert
node _io_req_1_ready_T = bits(in_arb_sel, 1, 1)
connect io.req.`1`.ready, _io_req_1_ready_T
connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`1`.vc_sel.`0`[3], in_alloc.`0`[3]
connect io.resp.`1`.vc_sel.`0`[4], in_alloc.`0`[4]
connect io.resp.`1`.vc_sel.`0`[5], in_alloc.`0`[5]
connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0]
node lo_hi_2 = cat(io.resp.`1`.vc_sel.`0`[2], io.resp.`1`.vc_sel.`0`[1])
node lo_2 = cat(lo_hi_2, io.resp.`1`.vc_sel.`0`[0])
node hi_hi_2 = cat(io.resp.`1`.vc_sel.`0`[5], io.resp.`1`.vc_sel.`0`[4])
node hi_4 = cat(hi_hi_2, io.resp.`1`.vc_sel.`0`[3])
node _T_45 = cat(hi_4, lo_2)
node hi_5 = cat(io.resp.`1`.vc_sel.`2`[0], io.resp.`1`.vc_sel.`1`[0])
node _T_46 = cat(hi_5, _T_45)
node _T_47 = bits(_T_46, 0, 0)
node _T_48 = bits(_T_46, 1, 1)
node _T_49 = bits(_T_46, 2, 2)
node _T_50 = bits(_T_46, 3, 3)
node _T_51 = bits(_T_46, 4, 4)
node _T_52 = bits(_T_46, 5, 5)
node _T_53 = bits(_T_46, 6, 6)
node _T_54 = bits(_T_46, 7, 7)
node _T_55 = add(_T_47, _T_48)
node _T_56 = bits(_T_55, 1, 0)
node _T_57 = add(_T_49, _T_50)
node _T_58 = bits(_T_57, 1, 0)
node _T_59 = add(_T_56, _T_58)
node _T_60 = bits(_T_59, 2, 0)
node _T_61 = add(_T_51, _T_52)
node _T_62 = bits(_T_61, 1, 0)
node _T_63 = add(_T_53, _T_54)
node _T_64 = bits(_T_63, 1, 0)
node _T_65 = add(_T_62, _T_64)
node _T_66 = bits(_T_65, 2, 0)
node _T_67 = add(_T_60, _T_66)
node _T_68 = bits(_T_67, 3, 0)
node _T_69 = leq(_T_68, UInt<1>(0h1))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1
assert(clock, _T_69, UInt<1>(0h1), "") : assert_1
connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0]
connect io.out_allocs.`0`[0].flow, in_flow
connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1]
connect io.out_allocs.`0`[1].flow, in_flow
connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2]
connect io.out_allocs.`0`[2].flow, in_flow
connect io.out_allocs.`0`[3].alloc, in_alloc.`0`[3]
connect io.out_allocs.`0`[3].flow, in_flow
connect io.out_allocs.`0`[4].alloc, in_alloc.`0`[4]
connect io.out_allocs.`0`[4].flow, in_flow
connect io.out_allocs.`0`[5].alloc, in_alloc.`0`[5]
connect io.out_allocs.`0`[5].flow, in_flow
connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0]
connect io.out_allocs.`1`[0].flow, in_flow
connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0]
connect io.out_allocs.`2`[0].flow, in_flow | module RotatingSingleVCAllocator_9( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_3, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_4, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_5, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_3, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_4, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_0_5, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_3_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_4_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_5_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_2_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_3_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_4_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_5_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [1:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [1:0] _in_arb_filter_T_3 = {in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{57,84,86}, :32:39]
wire [3:0] in_arb_filter = _in_arb_filter_T_3[0] ? 4'h1 : _in_arb_filter_T_3[1] ? 4'h2 : in_arb_vals_0 ? 4'h4 : {in_arb_vals_1, 3'h0}; // @[OneHot.scala:85:71]
wire [1:0] in_arb_sel = in_arb_filter[1:0] | in_arb_filter[3:2]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1; // @[package.scala:81:59]
wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_3 = io_req_0_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_4 = io_req_0_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_5 = io_req_0_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_0_3 | in_arb_reqs_0_0_4 | in_arb_reqs_0_0_5 | in_arb_reqs_0_1_0 | in_arb_reqs_0_2_0); // @[package.scala:81:59]
wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_3 = io_req_1_bits_vc_sel_0_3 & ~io_channel_status_0_3_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_4 = io_req_1_bits_vc_sel_0_4 & ~io_channel_status_0_4_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_5 = io_req_1_bits_vc_sel_0_5 & ~io_channel_status_0_5_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_0_3 | in_arb_reqs_1_0_4 | in_arb_reqs_1_0_5 | in_arb_reqs_1_1_0 | in_arb_reqs_1_2_0); // @[package.scala:81:59]
wire _in_vc_sel_T_4 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_7 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_10 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_13 = in_arb_sel[0] & in_arb_reqs_0_0_3 | in_arb_sel[1] & in_arb_reqs_1_0_3; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_16 = in_arb_sel[0] & in_arb_reqs_0_0_4 | in_arb_sel[1] & in_arb_reqs_1_0_4; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_19 = in_arb_sel[0] & in_arb_reqs_0_0_5 | in_arb_sel[1] & in_arb_reqs_1_0_5; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_22 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_25 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0; // @[Mux.scala:30:73, :32:36]
reg [7:0] mask_1; // @[ISLIP.scala:17:25]
wire [7:0] _full_T_1 = {_in_vc_sel_T_25, _in_vc_sel_T_22, _in_vc_sel_T_19, _in_vc_sel_T_16, _in_vc_sel_T_13, _in_vc_sel_T_10, _in_vc_sel_T_7, _in_vc_sel_T_4} & ~mask_1; // @[Mux.scala:30:73]
wire [15:0] oh = _full_T_1[0] ? 16'h1 : _full_T_1[1] ? 16'h2 : _full_T_1[2] ? 16'h4 : _full_T_1[3] ? 16'h8 : _full_T_1[4] ? 16'h10 : _full_T_1[5] ? 16'h20 : _full_T_1[6] ? 16'h40 : _full_T_1[7] ? 16'h80 : _in_vc_sel_T_4 ? 16'h100 : _in_vc_sel_T_7 ? 16'h200 : _in_vc_sel_T_10 ? 16'h400 : _in_vc_sel_T_13 ? 16'h800 : _in_vc_sel_T_16 ? 16'h1000 : _in_vc_sel_T_19 ? 16'h2000 : _in_vc_sel_T_22 ? 16'h4000 : {_in_vc_sel_T_25, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] sel = oh[7:0] | oh[15:8]; // @[Mux.scala:50:70]
wire in_alloc_2_0 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59]
wire in_alloc_0_3 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_0_4 = _GEN & sel[4]; // @[package.scala:81:59]
wire in_alloc_0_5 = _GEN & sel[5]; // @[package.scala:81:59] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_535 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_535( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_70 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_70
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_70( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_70 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain :
output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_rockettile_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_rockettile_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip element_reset_domain_rockettile_reset_vector_in : UInt<32>, flip element_reset_domain_rockettile_hartid_in : UInt<1>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, tl_master_clock_xing_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst element_reset_domain of HierarchicalElementResetDomain
inst clockNode of FixedClockBroadcast_1_1
inst buffer of TLBuffer_a32d128s5k4z4u_2
connect buffer.clock, childClock
connect buffer.reset, childReset
inst buffer_1 of TLBuffer_2
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst intsink of IntSyncAsyncCrossingSink_n1x1
connect intsink.clock, childClock
connect intsink.reset, childReset
inst intsink_1 of IntSyncSyncCrossingSink_n1x2
inst intsink_2 of IntSyncSyncCrossingSink_n1x1
inst intsink_3 of IntSyncSyncCrossingSink_n1x1_1
inst intsink_4 of IntSyncSyncCrossingSink_n1x1_2
inst intsource of IntSyncCrossingSource_n1x1
connect intsource.clock, childClock
connect intsource.reset, childReset
inst intsink_5 of IntSyncSyncCrossingSink_n1x1_3
inst intsource_1 of IntSyncCrossingSource_n1x1_1
connect intsource_1.clock, childClock
connect intsource_1.reset, childReset
inst intsink_6 of IntSyncSyncCrossingSink_n1x1_4
inst intsource_2 of IntSyncCrossingSource_n1x1_2
connect intsource_2.clock, childClock
connect intsource_2.reset, childReset
wire tapClockNodeOut : { clock : Clock, reset : Reset}
invalidate tapClockNodeOut.reset
invalidate tapClockNodeOut.clock
wire tapClockNodeIn : { clock : Clock, reset : Reset}
invalidate tapClockNodeIn.reset
invalidate tapClockNodeIn.clock
connect tapClockNodeOut, tapClockNodeIn
wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate tlMasterClockXingOut.d.bits.corrupt
invalidate tlMasterClockXingOut.d.bits.data
invalidate tlMasterClockXingOut.d.bits.denied
invalidate tlMasterClockXingOut.d.bits.sink
invalidate tlMasterClockXingOut.d.bits.source
invalidate tlMasterClockXingOut.d.bits.size
invalidate tlMasterClockXingOut.d.bits.param
invalidate tlMasterClockXingOut.d.bits.opcode
invalidate tlMasterClockXingOut.d.valid
invalidate tlMasterClockXingOut.d.ready
invalidate tlMasterClockXingOut.a.bits.corrupt
invalidate tlMasterClockXingOut.a.bits.data
invalidate tlMasterClockXingOut.a.bits.mask
invalidate tlMasterClockXingOut.a.bits.address
invalidate tlMasterClockXingOut.a.bits.source
invalidate tlMasterClockXingOut.a.bits.size
invalidate tlMasterClockXingOut.a.bits.param
invalidate tlMasterClockXingOut.a.bits.opcode
invalidate tlMasterClockXingOut.a.valid
invalidate tlMasterClockXingOut.a.ready
wire x1_tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate x1_tlMasterClockXingOut.e.bits.sink
invalidate x1_tlMasterClockXingOut.e.valid
invalidate x1_tlMasterClockXingOut.e.ready
invalidate x1_tlMasterClockXingOut.d.bits.corrupt
invalidate x1_tlMasterClockXingOut.d.bits.data
invalidate x1_tlMasterClockXingOut.d.bits.denied
invalidate x1_tlMasterClockXingOut.d.bits.sink
invalidate x1_tlMasterClockXingOut.d.bits.source
invalidate x1_tlMasterClockXingOut.d.bits.size
invalidate x1_tlMasterClockXingOut.d.bits.param
invalidate x1_tlMasterClockXingOut.d.bits.opcode
invalidate x1_tlMasterClockXingOut.d.valid
invalidate x1_tlMasterClockXingOut.d.ready
invalidate x1_tlMasterClockXingOut.c.bits.corrupt
invalidate x1_tlMasterClockXingOut.c.bits.data
invalidate x1_tlMasterClockXingOut.c.bits.address
invalidate x1_tlMasterClockXingOut.c.bits.source
invalidate x1_tlMasterClockXingOut.c.bits.size
invalidate x1_tlMasterClockXingOut.c.bits.param
invalidate x1_tlMasterClockXingOut.c.bits.opcode
invalidate x1_tlMasterClockXingOut.c.valid
invalidate x1_tlMasterClockXingOut.c.ready
invalidate x1_tlMasterClockXingOut.b.bits.corrupt
invalidate x1_tlMasterClockXingOut.b.bits.data
invalidate x1_tlMasterClockXingOut.b.bits.mask
invalidate x1_tlMasterClockXingOut.b.bits.address
invalidate x1_tlMasterClockXingOut.b.bits.source
invalidate x1_tlMasterClockXingOut.b.bits.size
invalidate x1_tlMasterClockXingOut.b.bits.param
invalidate x1_tlMasterClockXingOut.b.bits.opcode
invalidate x1_tlMasterClockXingOut.b.valid
invalidate x1_tlMasterClockXingOut.b.ready
invalidate x1_tlMasterClockXingOut.a.bits.corrupt
invalidate x1_tlMasterClockXingOut.a.bits.data
invalidate x1_tlMasterClockXingOut.a.bits.mask
invalidate x1_tlMasterClockXingOut.a.bits.address
invalidate x1_tlMasterClockXingOut.a.bits.source
invalidate x1_tlMasterClockXingOut.a.bits.size
invalidate x1_tlMasterClockXingOut.a.bits.param
invalidate x1_tlMasterClockXingOut.a.bits.opcode
invalidate x1_tlMasterClockXingOut.a.valid
invalidate x1_tlMasterClockXingOut.a.ready
wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate tlMasterClockXingIn.d.bits.corrupt
invalidate tlMasterClockXingIn.d.bits.data
invalidate tlMasterClockXingIn.d.bits.denied
invalidate tlMasterClockXingIn.d.bits.sink
invalidate tlMasterClockXingIn.d.bits.source
invalidate tlMasterClockXingIn.d.bits.size
invalidate tlMasterClockXingIn.d.bits.param
invalidate tlMasterClockXingIn.d.bits.opcode
invalidate tlMasterClockXingIn.d.valid
invalidate tlMasterClockXingIn.d.ready
invalidate tlMasterClockXingIn.a.bits.corrupt
invalidate tlMasterClockXingIn.a.bits.data
invalidate tlMasterClockXingIn.a.bits.mask
invalidate tlMasterClockXingIn.a.bits.address
invalidate tlMasterClockXingIn.a.bits.source
invalidate tlMasterClockXingIn.a.bits.size
invalidate tlMasterClockXingIn.a.bits.param
invalidate tlMasterClockXingIn.a.bits.opcode
invalidate tlMasterClockXingIn.a.valid
invalidate tlMasterClockXingIn.a.ready
wire x1_tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate x1_tlMasterClockXingIn.e.bits.sink
invalidate x1_tlMasterClockXingIn.e.valid
invalidate x1_tlMasterClockXingIn.e.ready
invalidate x1_tlMasterClockXingIn.d.bits.corrupt
invalidate x1_tlMasterClockXingIn.d.bits.data
invalidate x1_tlMasterClockXingIn.d.bits.denied
invalidate x1_tlMasterClockXingIn.d.bits.sink
invalidate x1_tlMasterClockXingIn.d.bits.source
invalidate x1_tlMasterClockXingIn.d.bits.size
invalidate x1_tlMasterClockXingIn.d.bits.param
invalidate x1_tlMasterClockXingIn.d.bits.opcode
invalidate x1_tlMasterClockXingIn.d.valid
invalidate x1_tlMasterClockXingIn.d.ready
invalidate x1_tlMasterClockXingIn.c.bits.corrupt
invalidate x1_tlMasterClockXingIn.c.bits.data
invalidate x1_tlMasterClockXingIn.c.bits.address
invalidate x1_tlMasterClockXingIn.c.bits.source
invalidate x1_tlMasterClockXingIn.c.bits.size
invalidate x1_tlMasterClockXingIn.c.bits.param
invalidate x1_tlMasterClockXingIn.c.bits.opcode
invalidate x1_tlMasterClockXingIn.c.valid
invalidate x1_tlMasterClockXingIn.c.ready
invalidate x1_tlMasterClockXingIn.b.bits.corrupt
invalidate x1_tlMasterClockXingIn.b.bits.data
invalidate x1_tlMasterClockXingIn.b.bits.mask
invalidate x1_tlMasterClockXingIn.b.bits.address
invalidate x1_tlMasterClockXingIn.b.bits.source
invalidate x1_tlMasterClockXingIn.b.bits.size
invalidate x1_tlMasterClockXingIn.b.bits.param
invalidate x1_tlMasterClockXingIn.b.bits.opcode
invalidate x1_tlMasterClockXingIn.b.valid
invalidate x1_tlMasterClockXingIn.b.ready
invalidate x1_tlMasterClockXingIn.a.bits.corrupt
invalidate x1_tlMasterClockXingIn.a.bits.data
invalidate x1_tlMasterClockXingIn.a.bits.mask
invalidate x1_tlMasterClockXingIn.a.bits.address
invalidate x1_tlMasterClockXingIn.a.bits.source
invalidate x1_tlMasterClockXingIn.a.bits.size
invalidate x1_tlMasterClockXingIn.a.bits.param
invalidate x1_tlMasterClockXingIn.a.bits.opcode
invalidate x1_tlMasterClockXingIn.a.valid
invalidate x1_tlMasterClockXingIn.a.ready
connect tlMasterClockXingOut, tlMasterClockXingIn
connect x1_tlMasterClockXingOut, x1_tlMasterClockXingIn
wire intInClockXingOut : { sync : UInt<1>[2]}
invalidate intInClockXingOut.sync[0]
invalidate intInClockXingOut.sync[1]
wire intInClockXingIn : { sync : UInt<1>[2]}
invalidate intInClockXingIn.sync[0]
invalidate intInClockXingIn.sync[1]
connect intInClockXingOut, intInClockXingIn
wire intInClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_1.sync[0]
wire intInClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_1.sync[0]
connect intInClockXingOut_1, intInClockXingIn_1
wire intInClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intInClockXingOut_2.sync[0]
wire intInClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intInClockXingIn_2.sync[0]
connect intInClockXingOut_2, intInClockXingIn_2
wire intOutClockXingOut : { sync : UInt<1>[1]}
invalidate intOutClockXingOut.sync[0]
wire intOutClockXingIn : { sync : UInt<1>[1]}
invalidate intOutClockXingIn.sync[0]
connect intOutClockXingOut, intOutClockXingIn
wire intOutClockXingOut_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_1.sync[0]
wire intOutClockXingIn_1 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_1.sync[0]
connect intOutClockXingOut_1, intOutClockXingIn_1
wire intOutClockXingOut_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_2.sync[0]
wire intOutClockXingIn_2 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_2.sync[0]
connect intOutClockXingOut_2, intOutClockXingIn_2
wire intOutClockXingOut_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_3.sync[0]
wire intOutClockXingIn_3 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_3.sync[0]
connect intOutClockXingOut_3, intOutClockXingIn_3
wire intOutClockXingOut_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_4.sync[0]
wire intOutClockXingIn_4 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_4.sync[0]
connect intOutClockXingOut_4, intOutClockXingIn_4
wire intOutClockXingOut_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingOut_5.sync[0]
wire intOutClockXingIn_5 : { sync : UInt<1>[1]}
invalidate intOutClockXingIn_5.sync[0]
connect intOutClockXingOut_5, intOutClockXingIn_5
connect clockNode.auto.anon_in, tapClockNodeOut
connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out
connect intsource.auto.in[0], element_reset_domain.auto.rockettile_halt_out[0]
connect intsource_2.auto.in[0], element_reset_domain.auto.rockettile_cease_out[0]
connect intsource_1.auto.in[0], element_reset_domain.auto.rockettile_wfi_out[0]
connect buffer.auto.in_0, element_reset_domain.auto.rockettile_buffer_out_0
connect buffer.auto.in_1, element_reset_domain.auto.rockettile_buffer_out_1
connect buffer.auto.out_0.d, tlMasterClockXingIn.d
connect tlMasterClockXingIn.a.bits, buffer.auto.out_0.a.bits
connect tlMasterClockXingIn.a.valid, buffer.auto.out_0.a.valid
connect buffer.auto.out_0.a.ready, tlMasterClockXingIn.a.ready
connect x1_tlMasterClockXingIn.e.bits, buffer.auto.out_1.e.bits
connect x1_tlMasterClockXingIn.e.valid, buffer.auto.out_1.e.valid
connect buffer.auto.out_1.e.ready, x1_tlMasterClockXingIn.e.ready
connect buffer.auto.out_1.d, x1_tlMasterClockXingIn.d
connect x1_tlMasterClockXingIn.c.bits, buffer.auto.out_1.c.bits
connect x1_tlMasterClockXingIn.c.valid, buffer.auto.out_1.c.valid
connect buffer.auto.out_1.c.ready, x1_tlMasterClockXingIn.c.ready
connect buffer.auto.out_1.b, x1_tlMasterClockXingIn.b
connect x1_tlMasterClockXingIn.a.bits, buffer.auto.out_1.a.bits
connect x1_tlMasterClockXingIn.a.valid, buffer.auto.out_1.a.valid
connect buffer.auto.out_1.a.ready, x1_tlMasterClockXingIn.a.ready
connect element_reset_domain.auto.rockettile_int_local_in_0[0], intsink.auto.out[0]
connect element_reset_domain.auto.rockettile_int_local_in_1[0], intsink_1.auto.out[0]
connect element_reset_domain.auto.rockettile_int_local_in_1[1], intsink_1.auto.out[1]
connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0]
connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1]
connect element_reset_domain.auto.rockettile_int_local_in_2[0], intsink_2.auto.out[0]
connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0]
connect element_reset_domain.auto.rockettile_int_local_in_3[0], intsink_3.auto.out[0]
connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0]
connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0]
connect intOutClockXingIn, intOutClockXingOut_1
connect intOutClockXingIn_1, intsource.auto.out
connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0]
connect intOutClockXingIn_2, intOutClockXingOut_3
connect intOutClockXingIn_3, intsource_1.auto.out
connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0]
connect intOutClockXingIn_4, intOutClockXingOut_5
connect intOutClockXingIn_5, intsource_2.auto.out
connect tapClockNodeIn, auto.tap_clock_in
connect auto.tl_master_clock_xing_out_0, tlMasterClockXingOut
connect auto.tl_master_clock_xing_out_1, x1_tlMasterClockXingOut
connect intInClockXingIn, auto.int_in_clock_xing_in_0
connect intInClockXingIn_1, auto.int_in_clock_xing_in_1
connect intInClockXingIn_2, auto.int_in_clock_xing_in_2
connect element_reset_domain.auto.rockettile_hartid_in, auto.element_reset_domain_rockettile_hartid_in
connect element_reset_domain.auto.rockettile_reset_vector_in, auto.element_reset_domain_rockettile_reset_vector_in
connect auto.element_reset_domain_rockettile_trace_source_out.time, element_reset_domain.auto.rockettile_trace_source_out.time
connect auto.element_reset_domain_rockettile_trace_source_out.insns, element_reset_domain.auto.rockettile_trace_source_out.insns
connect auto.element_reset_domain_rockettile_trace_core_source_out.cause, element_reset_domain.auto.rockettile_trace_core_source_out.cause
connect auto.element_reset_domain_rockettile_trace_core_source_out.tval, element_reset_domain.auto.rockettile_trace_core_source_out.tval
connect auto.element_reset_domain_rockettile_trace_core_source_out.priv, element_reset_domain.auto.rockettile_trace_core_source_out.priv
connect auto.element_reset_domain_rockettile_trace_core_source_out.group, element_reset_domain.auto.rockettile_trace_core_source_out.group
connect intsink.auto.in.sync[0], auto.intsink_in.sync[0]
connect auto.intsink_out_0, intsink_4.auto.out
connect auto.intsink_out_1, intsink_5.auto.out
connect auto.intsink_out_2, intsink_6.auto.out
connect childClock, tapClockNodeIn.clock
connect childReset, tapClockNodeIn.reset
connect clock, tapClockNodeIn.clock
connect reset, tapClockNodeIn.reset | module TilePRCIDomain( // @[ClockDomain.scala:14:9]
output auto_intsink_out_1_0, // @[LazyModuleImp.scala:107:25]
input auto_intsink_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_element_reset_domain_rockettile_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input auto_element_reset_domain_rockettile_hartid_in, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_2_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_1_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_0, // @[LazyModuleImp.scala:107:25]
input auto_int_in_clock_xing_in_0_sync_1, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_tl_master_clock_xing_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_tl_master_clock_xing_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_master_clock_xing_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_master_clock_xing_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_tl_master_clock_xing_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_tl_master_clock_xing_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_master_clock_xing_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_master_clock_xing_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_tl_master_clock_xing_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_master_clock_xing_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_tl_master_clock_xing_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_tl_master_clock_xing_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_master_clock_xing_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_master_clock_xing_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_master_clock_xing_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_tl_master_clock_xing_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_master_clock_xing_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_tl_master_clock_xing_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_master_clock_xing_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_intsink_in_sync_0_0 = auto_intsink_in_sync_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_hartid_in_0 = auto_element_reset_domain_rockettile_hartid_in; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_2_sync_0_0 = auto_int_in_clock_xing_in_2_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_1_sync_0_0 = auto_int_in_clock_xing_in_1_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_0_0 = auto_int_in_clock_xing_in_0_sync_0; // @[ClockDomain.scala:14:9]
wire auto_int_in_clock_xing_in_0_sync_1_0 = auto_int_in_clock_xing_in_0_sync_1; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_a_ready_0 = auto_tl_master_clock_xing_out_1_a_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_b_valid_0 = auto_tl_master_clock_xing_out_1_b_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_1_b_bits_param_0 = auto_tl_master_clock_xing_out_1_b_bits_param; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_1_b_bits_address_0 = auto_tl_master_clock_xing_out_1_b_bits_address; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_c_ready_0 = auto_tl_master_clock_xing_out_1_c_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_d_valid_0 = auto_tl_master_clock_xing_out_1_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_1_d_bits_opcode_0 = auto_tl_master_clock_xing_out_1_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_1_d_bits_param_0 = auto_tl_master_clock_xing_out_1_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_1_d_bits_size_0 = auto_tl_master_clock_xing_out_1_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_1_d_bits_source_0 = auto_tl_master_clock_xing_out_1_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_1_d_bits_sink_0 = auto_tl_master_clock_xing_out_1_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_d_bits_denied_0 = auto_tl_master_clock_xing_out_1_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_1_d_bits_data_0 = auto_tl_master_clock_xing_out_1_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_1_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_0_a_ready_0 = auto_tl_master_clock_xing_out_0_a_ready; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_0_d_valid_0 = auto_tl_master_clock_xing_out_0_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_0_d_bits_opcode_0 = auto_tl_master_clock_xing_out_0_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_0_d_bits_param_0 = auto_tl_master_clock_xing_out_0_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_0_d_bits_size_0 = auto_tl_master_clock_xing_out_0_d_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] auto_tl_master_clock_xing_out_0_d_bits_source_0 = auto_tl_master_clock_xing_out_0_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_0_d_bits_sink_0 = auto_tl_master_clock_xing_out_0_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_0_d_bits_denied_0 = auto_tl_master_clock_xing_out_0_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_0_d_bits_data_0 = auto_tl_master_clock_xing_out_0_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_0_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_0_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_element_reset_domain_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_reset_vector_in = 32'h10000; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_1_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] x1_tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [3:0] auto_tl_master_clock_xing_out_1_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9]
wire [3:0] x1_tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17]
wire [1:0] auto_tl_master_clock_xing_out_1_b_bits_source = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] x1_tlMasterClockXingOut_b_bits_source = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlMasterClockXingIn_b_bits_source = 2'h0; // @[MixedNode.scala:551:17]
wire [15:0] auto_tl_master_clock_xing_out_1_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9]
wire [15:0] x1_tlMasterClockXingOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17]
wire [15:0] x1_tlMasterClockXingIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17]
wire [127:0] auto_tl_master_clock_xing_out_1_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9]
wire [127:0] x1_tlMasterClockXingOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17]
wire [127:0] x1_tlMasterClockXingIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17]
wire auto_tl_master_clock_xing_out_1_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire auto_intsink_out_2_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_0_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire element_reset_domain_auto_rockettile_buffer_out_1_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_cease_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_halt_out_0 = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9]
wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire x1_tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_4_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_4_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_5_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
wire intOutClockXingIn_5_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
wire [39:0] element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
wire [63:0] element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_hartid_in = auto_element_reset_domain_rockettile_hartid_in_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_2_sync_0 = auto_int_in_clock_xing_in_2_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_1_sync_0 = auto_int_in_clock_xing_in_1_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_0 = auto_int_in_clock_xing_in_0_sync_0_0; // @[ClockDomain.scala:14:9]
wire intInClockXingIn_sync_1 = auto_int_in_clock_xing_in_0_sync_1_0; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_1_a_ready_0; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] x1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] x1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_1_b_valid_0; // @[ClockDomain.scala:14:9]
wire [1:0] x1_tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_1_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] x1_tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_1_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_1_c_ready_0; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] x1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_1_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] x1_tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] x1_tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_1_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] x1_tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_1_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] x1_tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_1_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [3:0] x1_tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_1_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_1_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [127:0] x1_tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_1_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] x1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_0_a_ready_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_0_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_0_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_0_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_0_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_0_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_0_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [127:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_0_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
wire auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
wire [39:0] auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_1_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [15:0] auto_tl_master_clock_xing_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_1_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_1_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_tl_master_clock_xing_out_1_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_1_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_1_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_d_ready_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_1_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_1_e_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_tl_master_clock_xing_out_0_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_tl_master_clock_xing_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_tl_master_clock_xing_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_tl_master_clock_xing_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [15:0] auto_tl_master_clock_xing_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [127:0] auto_tl_master_clock_xing_out_0_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_0_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_tl_master_clock_xing_out_0_d_ready_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0 = element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time_0 = element_reset_domain_auto_rockettile_trace_source_out_time; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_1_a_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_a_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_1_b_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] element_reset_domain_auto_rockettile_buffer_out_1_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_1_b_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_b_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_1_c_bits_address; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_1_c_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_c_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_1_d_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_d_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_d_valid; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_1_e_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_e_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_1_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_0_a_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_0_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_0_a_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_0_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_source; // @[ClockDomain.scala:14:9]
wire [3:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_sink; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_0_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [127:0] element_reset_domain_auto_rockettile_buffer_out_0_d_bits_data; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_0_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_0_d_ready; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_buffer_out_0_d_valid; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_wfi_out_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_3_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_2_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_1_1; // @[ClockDomain.scala:14:9]
wire element_reset_domain_auto_rockettile_int_local_in_0_0; // @[ClockDomain.scala:14:9]
wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31]
wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31]
assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17]
wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9]
assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9]
assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17]
assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_0_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9]
wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [4:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlMasterClockXingIn_a_ready = x1_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_valid_0 = x1_tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] x1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_opcode_0 = x1_tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] x1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_param_0 = x1_tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] x1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_size_0 = x1_tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] x1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_source_0 = x1_tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] x1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_address_0 = x1_tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9]
wire [15:0] x1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_mask_0 = x1_tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [127:0] x1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_data_0 = x1_tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_a_bits_corrupt_0 = x1_tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_b_ready_0 = x1_tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingIn_b_valid = x1_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlMasterClockXingIn_b_bits_param = x1_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] x1_tlMasterClockXingIn_b_bits_address = x1_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlMasterClockXingIn_c_ready = x1_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_valid_0 = x1_tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] x1_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_bits_opcode_0 = x1_tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] x1_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_bits_param_0 = x1_tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] x1_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_bits_size_0 = x1_tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] x1_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_bits_source_0 = x1_tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] x1_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_bits_address_0 = x1_tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9]
wire [127:0] x1_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_bits_data_0 = x1_tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_c_bits_corrupt_0 = x1_tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_d_ready_0 = x1_tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9]
wire x1_tlMasterClockXingIn_d_valid = x1_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlMasterClockXingIn_d_bits_opcode = x1_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlMasterClockXingIn_d_bits_param = x1_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlMasterClockXingIn_d_bits_size = x1_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlMasterClockXingIn_d_bits_source = x1_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlMasterClockXingIn_d_bits_sink = x1_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlMasterClockXingIn_d_bits_denied = x1_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] x1_tlMasterClockXingIn_d_bits_data = x1_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlMasterClockXingIn_d_bits_corrupt = x1_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_e_valid_0 = x1_tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9]
wire [3:0] x1_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign auto_tl_master_clock_xing_out_1_e_bits_sink_0 = x1_tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9]
assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_valid = x1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_opcode = x1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_param = x1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_size = x1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_source = x1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_address = x1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_mask = x1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_data = x1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_a_bits_corrupt = x1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_b_ready = x1_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_valid = x1_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_bits_opcode = x1_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_bits_param = x1_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_bits_size = x1_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_bits_source = x1_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_bits_address = x1_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_bits_data = x1_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_c_bits_corrupt = x1_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_d_ready = x1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_e_valid = x1_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlMasterClockXingOut_e_bits_sink = x1_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17]
wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17]
assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intInClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
assign intInClockXingOut_2_sync_0 = intInClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_2_sync_0; // @[MixedNode.scala:551:17]
wire intOutClockXingOut_2_sync_0; // @[MixedNode.scala:542:17]
wire intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17]
assign intOutClockXingOut_2_sync_0 = intOutClockXingIn_2_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intOutClockXingIn_3_sync_0; // @[MixedNode.scala:551:17]
assign intOutClockXingIn_2_sync_0 = intOutClockXingOut_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign intOutClockXingOut_3_sync_0 = intOutClockXingIn_3_sync_0; // @[MixedNode.scala:542:17, :551:17]
RocketTile element_reset_domain_rockettile ( // @[HasTiles.scala:164:59]
.clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31]
.reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_out_1_a_ready (element_reset_domain_auto_rockettile_buffer_out_1_a_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_a_valid (element_reset_domain_auto_rockettile_buffer_out_1_a_valid),
.auto_buffer_out_1_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_opcode),
.auto_buffer_out_1_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_param),
.auto_buffer_out_1_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_size),
.auto_buffer_out_1_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_source),
.auto_buffer_out_1_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_address),
.auto_buffer_out_1_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_mask),
.auto_buffer_out_1_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_data),
.auto_buffer_out_1_b_ready (element_reset_domain_auto_rockettile_buffer_out_1_b_ready),
.auto_buffer_out_1_b_valid (element_reset_domain_auto_rockettile_buffer_out_1_b_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_address), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_mask), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_c_ready (element_reset_domain_auto_rockettile_buffer_out_1_c_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_c_valid (element_reset_domain_auto_rockettile_buffer_out_1_c_valid),
.auto_buffer_out_1_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_opcode),
.auto_buffer_out_1_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_param),
.auto_buffer_out_1_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_size),
.auto_buffer_out_1_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_source),
.auto_buffer_out_1_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_address),
.auto_buffer_out_1_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_data),
.auto_buffer_out_1_d_ready (element_reset_domain_auto_rockettile_buffer_out_1_d_ready),
.auto_buffer_out_1_d_valid (element_reset_domain_auto_rockettile_buffer_out_1_d_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_sink), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_denied), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_e_ready (element_reset_domain_auto_rockettile_buffer_out_1_e_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_1_e_valid (element_reset_domain_auto_rockettile_buffer_out_1_e_valid),
.auto_buffer_out_1_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_1_e_bits_sink),
.auto_buffer_out_0_a_ready (element_reset_domain_auto_rockettile_buffer_out_0_a_ready), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_a_valid (element_reset_domain_auto_rockettile_buffer_out_0_a_valid),
.auto_buffer_out_0_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_opcode),
.auto_buffer_out_0_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_param),
.auto_buffer_out_0_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_size),
.auto_buffer_out_0_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_source),
.auto_buffer_out_0_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_address),
.auto_buffer_out_0_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_mask),
.auto_buffer_out_0_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_data),
.auto_buffer_out_0_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_corrupt),
.auto_buffer_out_0_d_ready (element_reset_domain_auto_rockettile_buffer_out_0_d_ready),
.auto_buffer_out_0_d_valid (element_reset_domain_auto_rockettile_buffer_out_0_d_valid), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_param), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_size), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_source), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_sink), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_denied), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_data), // @[ClockDomain.scala:14:9]
.auto_buffer_out_0_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_wfi_out_0 (element_reset_domain_auto_rockettile_wfi_out_0),
.auto_int_local_in_3_0 (element_reset_domain_auto_rockettile_int_local_in_3_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_2_0 (element_reset_domain_auto_rockettile_int_local_in_2_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_0 (element_reset_domain_auto_rockettile_int_local_in_1_0), // @[ClockDomain.scala:14:9]
.auto_int_local_in_1_1 (element_reset_domain_auto_rockettile_int_local_in_1_1), // @[ClockDomain.scala:14:9]
.auto_int_local_in_0_0 (element_reset_domain_auto_rockettile_int_local_in_0_0), // @[ClockDomain.scala:14:9]
.auto_trace_source_out_insns_0_valid (element_reset_domain_auto_rockettile_trace_source_out_insns_0_valid),
.auto_trace_source_out_insns_0_iaddr (element_reset_domain_auto_rockettile_trace_source_out_insns_0_iaddr),
.auto_trace_source_out_insns_0_insn (element_reset_domain_auto_rockettile_trace_source_out_insns_0_insn),
.auto_trace_source_out_insns_0_priv (element_reset_domain_auto_rockettile_trace_source_out_insns_0_priv),
.auto_trace_source_out_insns_0_exception (element_reset_domain_auto_rockettile_trace_source_out_insns_0_exception),
.auto_trace_source_out_insns_0_interrupt (element_reset_domain_auto_rockettile_trace_source_out_insns_0_interrupt),
.auto_trace_source_out_insns_0_cause (element_reset_domain_auto_rockettile_trace_source_out_insns_0_cause),
.auto_trace_source_out_insns_0_tval (element_reset_domain_auto_rockettile_trace_source_out_insns_0_tval),
.auto_trace_source_out_time (element_reset_domain_auto_rockettile_trace_source_out_time),
.auto_hartid_in (element_reset_domain_auto_rockettile_hartid_in) // @[ClockDomain.scala:14:9]
); // @[HasTiles.scala:164:59]
TLBuffer_a32d128s5k4z4u_2 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_1_a_ready (element_reset_domain_auto_rockettile_buffer_out_1_a_ready),
.auto_in_1_a_valid (element_reset_domain_auto_rockettile_buffer_out_1_a_valid), // @[ClockDomain.scala:14:9]
.auto_in_1_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_1_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_1_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_1_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_1_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_1_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_mask), // @[ClockDomain.scala:14:9]
.auto_in_1_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_a_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_1_b_ready (element_reset_domain_auto_rockettile_buffer_out_1_b_ready), // @[ClockDomain.scala:14:9]
.auto_in_1_b_valid (element_reset_domain_auto_rockettile_buffer_out_1_b_valid),
.auto_in_1_b_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_opcode),
.auto_in_1_b_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_param),
.auto_in_1_b_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_size),
.auto_in_1_b_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_source),
.auto_in_1_b_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_address),
.auto_in_1_b_bits_mask (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_mask),
.auto_in_1_b_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_data),
.auto_in_1_b_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_b_bits_corrupt),
.auto_in_1_c_ready (element_reset_domain_auto_rockettile_buffer_out_1_c_ready),
.auto_in_1_c_valid (element_reset_domain_auto_rockettile_buffer_out_1_c_valid), // @[ClockDomain.scala:14:9]
.auto_in_1_c_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_1_c_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_1_c_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_1_c_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_1_c_bits_address (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_1_c_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_c_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_1_d_ready (element_reset_domain_auto_rockettile_buffer_out_1_d_ready), // @[ClockDomain.scala:14:9]
.auto_in_1_d_valid (element_reset_domain_auto_rockettile_buffer_out_1_d_valid),
.auto_in_1_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_opcode),
.auto_in_1_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_param),
.auto_in_1_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_size),
.auto_in_1_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_source),
.auto_in_1_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_sink),
.auto_in_1_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_denied),
.auto_in_1_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_data),
.auto_in_1_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_1_d_bits_corrupt),
.auto_in_1_e_ready (element_reset_domain_auto_rockettile_buffer_out_1_e_ready),
.auto_in_1_e_valid (element_reset_domain_auto_rockettile_buffer_out_1_e_valid), // @[ClockDomain.scala:14:9]
.auto_in_1_e_bits_sink (element_reset_domain_auto_rockettile_buffer_out_1_e_bits_sink), // @[ClockDomain.scala:14:9]
.auto_in_0_a_ready (element_reset_domain_auto_rockettile_buffer_out_0_a_ready),
.auto_in_0_a_valid (element_reset_domain_auto_rockettile_buffer_out_0_a_valid), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_opcode), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_param), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_size), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_source), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_address (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_address), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_mask (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_mask), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_data), // @[ClockDomain.scala:14:9]
.auto_in_0_a_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_a_bits_corrupt), // @[ClockDomain.scala:14:9]
.auto_in_0_d_ready (element_reset_domain_auto_rockettile_buffer_out_0_d_ready), // @[ClockDomain.scala:14:9]
.auto_in_0_d_valid (element_reset_domain_auto_rockettile_buffer_out_0_d_valid),
.auto_in_0_d_bits_opcode (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_opcode),
.auto_in_0_d_bits_param (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_param),
.auto_in_0_d_bits_size (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_size),
.auto_in_0_d_bits_source (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_source),
.auto_in_0_d_bits_sink (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_sink),
.auto_in_0_d_bits_denied (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_denied),
.auto_in_0_d_bits_data (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_data),
.auto_in_0_d_bits_corrupt (element_reset_domain_auto_rockettile_buffer_out_0_d_bits_corrupt),
.auto_out_1_a_ready (x1_tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_1_a_valid (x1_tlMasterClockXingIn_a_valid),
.auto_out_1_a_bits_opcode (x1_tlMasterClockXingIn_a_bits_opcode),
.auto_out_1_a_bits_param (x1_tlMasterClockXingIn_a_bits_param),
.auto_out_1_a_bits_size (x1_tlMasterClockXingIn_a_bits_size),
.auto_out_1_a_bits_source (x1_tlMasterClockXingIn_a_bits_source),
.auto_out_1_a_bits_address (x1_tlMasterClockXingIn_a_bits_address),
.auto_out_1_a_bits_mask (x1_tlMasterClockXingIn_a_bits_mask),
.auto_out_1_a_bits_data (x1_tlMasterClockXingIn_a_bits_data),
.auto_out_1_a_bits_corrupt (x1_tlMasterClockXingIn_a_bits_corrupt),
.auto_out_1_b_ready (x1_tlMasterClockXingIn_b_ready),
.auto_out_1_b_valid (x1_tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17]
.auto_out_1_b_bits_param (x1_tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_out_1_b_bits_address (x1_tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_out_1_c_ready (x1_tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17]
.auto_out_1_c_valid (x1_tlMasterClockXingIn_c_valid),
.auto_out_1_c_bits_opcode (x1_tlMasterClockXingIn_c_bits_opcode),
.auto_out_1_c_bits_param (x1_tlMasterClockXingIn_c_bits_param),
.auto_out_1_c_bits_size (x1_tlMasterClockXingIn_c_bits_size),
.auto_out_1_c_bits_source (x1_tlMasterClockXingIn_c_bits_source),
.auto_out_1_c_bits_address (x1_tlMasterClockXingIn_c_bits_address),
.auto_out_1_c_bits_data (x1_tlMasterClockXingIn_c_bits_data),
.auto_out_1_c_bits_corrupt (x1_tlMasterClockXingIn_c_bits_corrupt),
.auto_out_1_d_ready (x1_tlMasterClockXingIn_d_ready),
.auto_out_1_d_valid (x1_tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_opcode (x1_tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_param (x1_tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_size (x1_tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_source (x1_tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_sink (x1_tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_denied (x1_tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_data (x1_tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_1_d_bits_corrupt (x1_tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_out_1_e_valid (x1_tlMasterClockXingIn_e_valid),
.auto_out_1_e_bits_sink (x1_tlMasterClockXingIn_e_bits_sink),
.auto_out_0_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_0_a_valid (tlMasterClockXingIn_a_valid),
.auto_out_0_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode),
.auto_out_0_a_bits_param (tlMasterClockXingIn_a_bits_param),
.auto_out_0_a_bits_size (tlMasterClockXingIn_a_bits_size),
.auto_out_0_a_bits_source (tlMasterClockXingIn_a_bits_source),
.auto_out_0_a_bits_address (tlMasterClockXingIn_a_bits_address),
.auto_out_0_a_bits_mask (tlMasterClockXingIn_a_bits_mask),
.auto_out_0_a_bits_data (tlMasterClockXingIn_a_bits_data),
.auto_out_0_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt),
.auto_out_0_d_ready (tlMasterClockXingIn_d_ready),
.auto_out_0_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_0_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Buffer.scala:75:28]
TLBuffer_2 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
IntSyncAsyncCrossingSink_n1x1 intsink ( // @[Crossing.scala:86:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_sync_0 (auto_intsink_in_sync_0_0), // @[ClockDomain.scala:14:9]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_0_0)
); // @[Crossing.scala:86:29]
IntSyncSyncCrossingSink_n1x2 intsink_1 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_in_sync_1 (intInClockXingOut_sync_1), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_1_0),
.auto_out_1 (element_reset_domain_auto_rockettile_int_local_in_1_1)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1 intsink_2 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_1_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_2_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_1 intsink_3 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intInClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (element_reset_domain_auto_rockettile_int_local_in_3_0)
); // @[Crossing.scala:109:29]
IntSyncSyncCrossingSink_n1x1_2 intsink_4 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1 intsource ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_3 intsink_5 ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intOutClockXingOut_2_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (auto_intsink_out_1_0_0)
); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_1 intsource_1 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_0 (element_reset_domain_auto_rockettile_wfi_out_0), // @[ClockDomain.scala:14:9]
.auto_out_sync_0 (intOutClockXingIn_3_sync_0)
); // @[Crossing.scala:29:31]
IntSyncSyncCrossingSink_n1x1_4 intsink_6 (); // @[Crossing.scala:109:29]
IntSyncCrossingSource_n1x1_2 intsource_2 ( // @[Crossing.scala:29:31]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Crossing.scala:29:31]
assign auto_intsink_out_1_0 = auto_intsink_out_1_0_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid = auto_element_reset_domain_rockettile_trace_source_out_insns_0_valid_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr = auto_element_reset_domain_rockettile_trace_source_out_insns_0_iaddr_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn = auto_element_reset_domain_rockettile_trace_source_out_insns_0_insn_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv = auto_element_reset_domain_rockettile_trace_source_out_insns_0_priv_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception = auto_element_reset_domain_rockettile_trace_source_out_insns_0_exception_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt = auto_element_reset_domain_rockettile_trace_source_out_insns_0_interrupt_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause = auto_element_reset_domain_rockettile_trace_source_out_insns_0_cause_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval = auto_element_reset_domain_rockettile_trace_source_out_insns_0_tval_0; // @[ClockDomain.scala:14:9]
assign auto_element_reset_domain_rockettile_trace_source_out_time = auto_element_reset_domain_rockettile_trace_source_out_time_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_valid = auto_tl_master_clock_xing_out_1_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_opcode = auto_tl_master_clock_xing_out_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_param = auto_tl_master_clock_xing_out_1_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_size = auto_tl_master_clock_xing_out_1_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_source = auto_tl_master_clock_xing_out_1_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_address = auto_tl_master_clock_xing_out_1_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_mask = auto_tl_master_clock_xing_out_1_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_data = auto_tl_master_clock_xing_out_1_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_a_bits_corrupt = auto_tl_master_clock_xing_out_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_b_ready = auto_tl_master_clock_xing_out_1_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_valid = auto_tl_master_clock_xing_out_1_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_bits_opcode = auto_tl_master_clock_xing_out_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_bits_param = auto_tl_master_clock_xing_out_1_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_bits_size = auto_tl_master_clock_xing_out_1_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_bits_source = auto_tl_master_clock_xing_out_1_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_bits_address = auto_tl_master_clock_xing_out_1_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_bits_data = auto_tl_master_clock_xing_out_1_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_c_bits_corrupt = auto_tl_master_clock_xing_out_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_d_ready = auto_tl_master_clock_xing_out_1_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_e_valid = auto_tl_master_clock_xing_out_1_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_1_e_bits_sink = auto_tl_master_clock_xing_out_1_e_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_valid = auto_tl_master_clock_xing_out_0_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_opcode = auto_tl_master_clock_xing_out_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_param = auto_tl_master_clock_xing_out_0_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_size = auto_tl_master_clock_xing_out_0_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_source = auto_tl_master_clock_xing_out_0_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_address = auto_tl_master_clock_xing_out_0_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_mask = auto_tl_master_clock_xing_out_0_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_data = auto_tl_master_clock_xing_out_0_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_a_bits_corrupt = auto_tl_master_clock_xing_out_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_tl_master_clock_xing_out_0_d_ready = auto_tl_master_clock_xing_out_0_d_ready_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PartiallyPortedRF_2 :
input clock : Clock
input reset : Reset
output io : { flip arb_read_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<6>}[8], rrd_read_resps : UInt<64>[8], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<64>}}[4]}
node _T = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr)
node _T_4 = or(_T_2, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _T_8 = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_9 = eq(io.write_ports[2].valid, UInt<1>(0h0))
node _T_10 = or(_T_8, _T_9)
node _T_11 = neq(io.write_ports[0].bits.addr, io.write_ports[2].bits.addr)
node _T_12 = or(_T_10, _T_11)
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_1
assert(clock, _T_12, UInt<1>(0h1), "") : assert_1
node _T_16 = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_17 = eq(io.write_ports[3].valid, UInt<1>(0h0))
node _T_18 = or(_T_16, _T_17)
node _T_19 = neq(io.write_ports[0].bits.addr, io.write_ports[3].bits.addr)
node _T_20 = or(_T_18, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_2
assert(clock, _T_20, UInt<1>(0h1), "") : assert_2
node _T_24 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_25 = eq(io.write_ports[2].valid, UInt<1>(0h0))
node _T_26 = or(_T_24, _T_25)
node _T_27 = neq(io.write_ports[1].bits.addr, io.write_ports[2].bits.addr)
node _T_28 = or(_T_26, _T_27)
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_3
assert(clock, _T_28, UInt<1>(0h1), "") : assert_3
node _T_32 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_33 = eq(io.write_ports[3].valid, UInt<1>(0h0))
node _T_34 = or(_T_32, _T_33)
node _T_35 = neq(io.write_ports[1].bits.addr, io.write_ports[3].bits.addr)
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_4
assert(clock, _T_36, UInt<1>(0h1), "") : assert_4
node _T_40 = eq(io.write_ports[2].valid, UInt<1>(0h0))
node _T_41 = eq(io.write_ports[3].valid, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = neq(io.write_ports[2].bits.addr, io.write_ports[3].bits.addr)
node _T_44 = or(_T_42, _T_43)
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
node _T_47 = eq(_T_44, UInt<1>(0h0))
when _T_47 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_5
assert(clock, _T_44, UInt<1>(0h1), "") : assert_5
inst rf of FullyPortedRF_2
connect rf.clock, clock
connect rf.reset, reset
connect rf.io.write_ports[0].bits.data, io.write_ports[0].bits.data
connect rf.io.write_ports[0].bits.addr, io.write_ports[0].bits.addr
connect rf.io.write_ports[0].valid, io.write_ports[0].valid
connect rf.io.write_ports[1].bits.data, io.write_ports[1].bits.data
connect rf.io.write_ports[1].bits.addr, io.write_ports[1].bits.addr
connect rf.io.write_ports[1].valid, io.write_ports[1].valid
connect rf.io.write_ports[2].bits.data, io.write_ports[2].bits.data
connect rf.io.write_ports[2].bits.addr, io.write_ports[2].bits.addr
connect rf.io.write_ports[2].valid, io.write_ports[2].valid
connect rf.io.write_ports[3].bits.data, io.write_ports[3].bits.data
connect rf.io.write_ports[3].bits.addr, io.write_ports[3].bits.addr
connect rf.io.write_ports[3].valid, io.write_ports[3].valid
wire data_sels : UInt<5>[8]
invalidate data_sels[0]
invalidate data_sels[1]
invalidate data_sels[2]
invalidate data_sels[3]
invalidate data_sels[4]
invalidate data_sels[5]
invalidate data_sels[6]
invalidate data_sels[7]
wire issue_read : UInt<1>
connect issue_read, UInt<1>(0h0)
wire use_port : UInt<1>
connect use_port, UInt<1>(0h0)
node _T_48 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_49 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
node _T_51 = and(_T_50, io.arb_read_reqs[0].valid)
when _T_51 :
connect issue_read, UInt<1>(0h1)
connect use_port, UInt<1>(0h1)
node _data_sels_0_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[0], _data_sels_0_T
node _T_52 = or(use_port, UInt<1>(0h0))
node _T_53 = eq(use_port, UInt<1>(0h0))
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = mux(_T_54, UInt<1>(0h0), io.arb_read_reqs[0].bits)
node _T_56 = or(UInt<6>(0h0), _T_55)
node _T_57 = or(issue_read, UInt<1>(0h0))
wire issue_read_1 : UInt<1>
connect issue_read_1, UInt<1>(0h0)
wire use_port_1 : UInt<1>
connect use_port_1, UInt<1>(0h0)
node _T_58 = eq(_T_57, UInt<1>(0h0))
node _T_59 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_60 = and(_T_58, _T_59)
node _T_61 = and(_T_60, io.arb_read_reqs[0].valid)
when _T_61 :
connect issue_read_1, UInt<1>(0h1)
connect use_port_1, UInt<1>(0h1)
node _data_sels_0_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[0], _data_sels_0_T_1
node _T_62 = or(use_port_1, UInt<1>(0h0))
node _T_63 = eq(use_port_1, UInt<1>(0h0))
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = mux(_T_64, UInt<1>(0h0), io.arb_read_reqs[0].bits)
node _T_66 = or(UInt<6>(0h0), _T_65)
node _T_67 = or(issue_read_1, _T_57)
wire issue_read_2 : UInt<1>
connect issue_read_2, UInt<1>(0h0)
wire use_port_2 : UInt<1>
connect use_port_2, UInt<1>(0h0)
node _T_68 = eq(_T_67, UInt<1>(0h0))
node _T_69 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_70 = and(_T_68, _T_69)
node _T_71 = and(_T_70, io.arb_read_reqs[0].valid)
when _T_71 :
connect issue_read_2, UInt<1>(0h1)
connect use_port_2, UInt<1>(0h1)
node _data_sels_0_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[0], _data_sels_0_T_2
node _T_72 = or(use_port_2, UInt<1>(0h0))
node _T_73 = eq(use_port_2, UInt<1>(0h0))
node _T_74 = or(UInt<1>(0h0), _T_73)
node _T_75 = mux(_T_74, UInt<1>(0h0), io.arb_read_reqs[0].bits)
node _T_76 = or(UInt<6>(0h0), _T_75)
node _T_77 = or(issue_read_2, _T_67)
wire issue_read_3 : UInt<1>
connect issue_read_3, UInt<1>(0h0)
wire use_port_3 : UInt<1>
connect use_port_3, UInt<1>(0h0)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_80 = and(_T_78, _T_79)
node _T_81 = and(_T_80, io.arb_read_reqs[0].valid)
when _T_81 :
connect issue_read_3, UInt<1>(0h1)
connect use_port_3, UInt<1>(0h1)
node _data_sels_0_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[0], _data_sels_0_T_3
node _T_82 = or(use_port_3, UInt<1>(0h0))
node _T_83 = eq(use_port_3, UInt<1>(0h0))
node _T_84 = or(UInt<1>(0h0), _T_83)
node _T_85 = mux(_T_84, UInt<1>(0h0), io.arb_read_reqs[0].bits)
node _T_86 = or(UInt<6>(0h0), _T_85)
node _T_87 = or(issue_read_3, _T_77)
wire issue_read_4 : UInt<1>
connect issue_read_4, UInt<1>(0h0)
wire use_port_4 : UInt<1>
connect use_port_4, UInt<1>(0h0)
node _T_88 = eq(_T_87, UInt<1>(0h0))
node _T_89 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_90 = and(_T_88, _T_89)
node _T_91 = and(_T_90, io.arb_read_reqs[0].valid)
when _T_91 :
connect issue_read_4, UInt<1>(0h1)
connect use_port_4, UInt<1>(0h1)
node _data_sels_0_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[0], _data_sels_0_T_4
node _T_92 = or(use_port_4, UInt<1>(0h0))
node _T_93 = eq(use_port_4, UInt<1>(0h0))
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = mux(_T_94, UInt<1>(0h0), io.arb_read_reqs[0].bits)
node _T_96 = or(UInt<6>(0h0), _T_95)
node _T_97 = or(issue_read_4, _T_87)
node _io_arb_read_reqs_0_ready_T = lt(UInt<1>(0h0), UInt<3>(0h5))
connect io.arb_read_reqs[0].ready, _io_arb_read_reqs_0_ready_T
node _T_98 = and(io.arb_read_reqs[0].ready, io.arb_read_reqs[0].valid)
node _T_99 = eq(_T_97, UInt<1>(0h0))
node _T_100 = and(_T_98, _T_99)
node _T_101 = eq(_T_100, UInt<1>(0h0))
node _T_102 = asUInt(reset)
node _T_103 = eq(_T_102, UInt<1>(0h0))
when _T_103 :
node _T_104 = eq(_T_101, UInt<1>(0h0))
when _T_104 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_6
assert(clock, _T_101, UInt<1>(0h1), "") : assert_6
wire issue_read_5 : UInt<1>
connect issue_read_5, UInt<1>(0h0)
wire use_port_5 : UInt<1>
connect use_port_5, UInt<1>(0h0)
node _T_105 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_106 = eq(_T_52, UInt<1>(0h0))
node _T_107 = and(_T_105, _T_106)
node _T_108 = and(_T_107, io.arb_read_reqs[1].valid)
when _T_108 :
connect issue_read_5, UInt<1>(0h1)
connect use_port_5, UInt<1>(0h1)
node _data_sels_1_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[1], _data_sels_1_T
node _T_109 = or(use_port_5, _T_52)
node _T_110 = eq(use_port_5, UInt<1>(0h0))
node _T_111 = or(_T_52, _T_110)
node _T_112 = mux(_T_111, UInt<1>(0h0), io.arb_read_reqs[1].bits)
node _T_113 = or(_T_56, _T_112)
node _T_114 = or(issue_read_5, UInt<1>(0h0))
wire issue_read_6 : UInt<1>
connect issue_read_6, UInt<1>(0h0)
wire use_port_6 : UInt<1>
connect use_port_6, UInt<1>(0h0)
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = eq(_T_62, UInt<1>(0h0))
node _T_117 = and(_T_115, _T_116)
node _T_118 = and(_T_117, io.arb_read_reqs[1].valid)
when _T_118 :
connect issue_read_6, UInt<1>(0h1)
connect use_port_6, UInt<1>(0h1)
node _data_sels_1_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[1], _data_sels_1_T_1
node _T_119 = or(use_port_6, _T_62)
node _T_120 = eq(use_port_6, UInt<1>(0h0))
node _T_121 = or(_T_62, _T_120)
node _T_122 = mux(_T_121, UInt<1>(0h0), io.arb_read_reqs[1].bits)
node _T_123 = or(_T_66, _T_122)
node _T_124 = or(issue_read_6, _T_114)
wire issue_read_7 : UInt<1>
connect issue_read_7, UInt<1>(0h0)
wire use_port_7 : UInt<1>
connect use_port_7, UInt<1>(0h0)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = eq(_T_72, UInt<1>(0h0))
node _T_127 = and(_T_125, _T_126)
node _T_128 = and(_T_127, io.arb_read_reqs[1].valid)
when _T_128 :
connect issue_read_7, UInt<1>(0h1)
connect use_port_7, UInt<1>(0h1)
node _data_sels_1_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[1], _data_sels_1_T_2
node _T_129 = or(use_port_7, _T_72)
node _T_130 = eq(use_port_7, UInt<1>(0h0))
node _T_131 = or(_T_72, _T_130)
node _T_132 = mux(_T_131, UInt<1>(0h0), io.arb_read_reqs[1].bits)
node _T_133 = or(_T_76, _T_132)
node _T_134 = or(issue_read_7, _T_124)
wire issue_read_8 : UInt<1>
connect issue_read_8, UInt<1>(0h0)
wire use_port_8 : UInt<1>
connect use_port_8, UInt<1>(0h0)
node _T_135 = eq(_T_134, UInt<1>(0h0))
node _T_136 = eq(_T_82, UInt<1>(0h0))
node _T_137 = and(_T_135, _T_136)
node _T_138 = and(_T_137, io.arb_read_reqs[1].valid)
when _T_138 :
connect issue_read_8, UInt<1>(0h1)
connect use_port_8, UInt<1>(0h1)
node _data_sels_1_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[1], _data_sels_1_T_3
node _T_139 = or(use_port_8, _T_82)
node _T_140 = eq(use_port_8, UInt<1>(0h0))
node _T_141 = or(_T_82, _T_140)
node _T_142 = mux(_T_141, UInt<1>(0h0), io.arb_read_reqs[1].bits)
node _T_143 = or(_T_86, _T_142)
node _T_144 = or(issue_read_8, _T_134)
wire issue_read_9 : UInt<1>
connect issue_read_9, UInt<1>(0h0)
wire use_port_9 : UInt<1>
connect use_port_9, UInt<1>(0h0)
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = eq(_T_92, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = and(_T_147, io.arb_read_reqs[1].valid)
when _T_148 :
connect issue_read_9, UInt<1>(0h1)
connect use_port_9, UInt<1>(0h1)
node _data_sels_1_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[1], _data_sels_1_T_4
node _T_149 = or(use_port_9, _T_92)
node _T_150 = eq(use_port_9, UInt<1>(0h0))
node _T_151 = or(_T_92, _T_150)
node _T_152 = mux(_T_151, UInt<1>(0h0), io.arb_read_reqs[1].bits)
node _T_153 = or(_T_96, _T_152)
node _T_154 = or(issue_read_9, _T_144)
node _io_arb_read_reqs_1_ready_T = lt(io.arb_read_reqs[0].valid, UInt<3>(0h5))
connect io.arb_read_reqs[1].ready, _io_arb_read_reqs_1_ready_T
node _T_155 = and(io.arb_read_reqs[1].ready, io.arb_read_reqs[1].valid)
node _T_156 = eq(_T_154, UInt<1>(0h0))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(_T_157, UInt<1>(0h0))
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_7
assert(clock, _T_158, UInt<1>(0h1), "") : assert_7
wire issue_read_10 : UInt<1>
connect issue_read_10, UInt<1>(0h0)
wire use_port_10 : UInt<1>
connect use_port_10, UInt<1>(0h0)
node _T_162 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_163 = eq(_T_109, UInt<1>(0h0))
node _T_164 = and(_T_162, _T_163)
node _T_165 = and(_T_164, io.arb_read_reqs[2].valid)
when _T_165 :
connect issue_read_10, UInt<1>(0h1)
connect use_port_10, UInt<1>(0h1)
node _data_sels_2_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[2], _data_sels_2_T
node _T_166 = or(use_port_10, _T_109)
node _T_167 = eq(use_port_10, UInt<1>(0h0))
node _T_168 = or(_T_109, _T_167)
node _T_169 = mux(_T_168, UInt<1>(0h0), io.arb_read_reqs[2].bits)
node _T_170 = or(_T_113, _T_169)
node _T_171 = or(issue_read_10, UInt<1>(0h0))
wire issue_read_11 : UInt<1>
connect issue_read_11, UInt<1>(0h0)
wire use_port_11 : UInt<1>
connect use_port_11, UInt<1>(0h0)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = eq(_T_119, UInt<1>(0h0))
node _T_174 = and(_T_172, _T_173)
node _T_175 = and(_T_174, io.arb_read_reqs[2].valid)
when _T_175 :
connect issue_read_11, UInt<1>(0h1)
connect use_port_11, UInt<1>(0h1)
node _data_sels_2_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[2], _data_sels_2_T_1
node _T_176 = or(use_port_11, _T_119)
node _T_177 = eq(use_port_11, UInt<1>(0h0))
node _T_178 = or(_T_119, _T_177)
node _T_179 = mux(_T_178, UInt<1>(0h0), io.arb_read_reqs[2].bits)
node _T_180 = or(_T_123, _T_179)
node _T_181 = or(issue_read_11, _T_171)
wire issue_read_12 : UInt<1>
connect issue_read_12, UInt<1>(0h0)
wire use_port_12 : UInt<1>
connect use_port_12, UInt<1>(0h0)
node _T_182 = eq(_T_181, UInt<1>(0h0))
node _T_183 = eq(_T_129, UInt<1>(0h0))
node _T_184 = and(_T_182, _T_183)
node _T_185 = and(_T_184, io.arb_read_reqs[2].valid)
when _T_185 :
connect issue_read_12, UInt<1>(0h1)
connect use_port_12, UInt<1>(0h1)
node _data_sels_2_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[2], _data_sels_2_T_2
node _T_186 = or(use_port_12, _T_129)
node _T_187 = eq(use_port_12, UInt<1>(0h0))
node _T_188 = or(_T_129, _T_187)
node _T_189 = mux(_T_188, UInt<1>(0h0), io.arb_read_reqs[2].bits)
node _T_190 = or(_T_133, _T_189)
node _T_191 = or(issue_read_12, _T_181)
wire issue_read_13 : UInt<1>
connect issue_read_13, UInt<1>(0h0)
wire use_port_13 : UInt<1>
connect use_port_13, UInt<1>(0h0)
node _T_192 = eq(_T_191, UInt<1>(0h0))
node _T_193 = eq(_T_139, UInt<1>(0h0))
node _T_194 = and(_T_192, _T_193)
node _T_195 = and(_T_194, io.arb_read_reqs[2].valid)
when _T_195 :
connect issue_read_13, UInt<1>(0h1)
connect use_port_13, UInt<1>(0h1)
node _data_sels_2_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[2], _data_sels_2_T_3
node _T_196 = or(use_port_13, _T_139)
node _T_197 = eq(use_port_13, UInt<1>(0h0))
node _T_198 = or(_T_139, _T_197)
node _T_199 = mux(_T_198, UInt<1>(0h0), io.arb_read_reqs[2].bits)
node _T_200 = or(_T_143, _T_199)
node _T_201 = or(issue_read_13, _T_191)
wire issue_read_14 : UInt<1>
connect issue_read_14, UInt<1>(0h0)
wire use_port_14 : UInt<1>
connect use_port_14, UInt<1>(0h0)
node _T_202 = eq(_T_201, UInt<1>(0h0))
node _T_203 = eq(_T_149, UInt<1>(0h0))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_204, io.arb_read_reqs[2].valid)
when _T_205 :
connect issue_read_14, UInt<1>(0h1)
connect use_port_14, UInt<1>(0h1)
node _data_sels_2_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[2], _data_sels_2_T_4
node _T_206 = or(use_port_14, _T_149)
node _T_207 = eq(use_port_14, UInt<1>(0h0))
node _T_208 = or(_T_149, _T_207)
node _T_209 = mux(_T_208, UInt<1>(0h0), io.arb_read_reqs[2].bits)
node _T_210 = or(_T_153, _T_209)
node _T_211 = or(issue_read_14, _T_201)
node _io_arb_read_reqs_2_ready_T = add(io.arb_read_reqs[0].valid, io.arb_read_reqs[1].valid)
node _io_arb_read_reqs_2_ready_T_1 = bits(_io_arb_read_reqs_2_ready_T, 1, 0)
node _io_arb_read_reqs_2_ready_T_2 = lt(_io_arb_read_reqs_2_ready_T_1, UInt<3>(0h5))
connect io.arb_read_reqs[2].ready, _io_arb_read_reqs_2_ready_T_2
node _T_212 = and(io.arb_read_reqs[2].ready, io.arb_read_reqs[2].valid)
node _T_213 = eq(_T_211, UInt<1>(0h0))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(_T_214, UInt<1>(0h0))
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_8
assert(clock, _T_215, UInt<1>(0h1), "") : assert_8
wire issue_read_15 : UInt<1>
connect issue_read_15, UInt<1>(0h0)
wire use_port_15 : UInt<1>
connect use_port_15, UInt<1>(0h0)
node _T_219 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_220 = eq(_T_166, UInt<1>(0h0))
node _T_221 = and(_T_219, _T_220)
node _T_222 = and(_T_221, io.arb_read_reqs[3].valid)
when _T_222 :
connect issue_read_15, UInt<1>(0h1)
connect use_port_15, UInt<1>(0h1)
node _data_sels_3_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[3], _data_sels_3_T
node _T_223 = or(use_port_15, _T_166)
node _T_224 = eq(use_port_15, UInt<1>(0h0))
node _T_225 = or(_T_166, _T_224)
node _T_226 = mux(_T_225, UInt<1>(0h0), io.arb_read_reqs[3].bits)
node _T_227 = or(_T_170, _T_226)
node _T_228 = or(issue_read_15, UInt<1>(0h0))
wire issue_read_16 : UInt<1>
connect issue_read_16, UInt<1>(0h0)
wire use_port_16 : UInt<1>
connect use_port_16, UInt<1>(0h0)
node _T_229 = eq(_T_228, UInt<1>(0h0))
node _T_230 = eq(_T_176, UInt<1>(0h0))
node _T_231 = and(_T_229, _T_230)
node _T_232 = and(_T_231, io.arb_read_reqs[3].valid)
when _T_232 :
connect issue_read_16, UInt<1>(0h1)
connect use_port_16, UInt<1>(0h1)
node _data_sels_3_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[3], _data_sels_3_T_1
node _T_233 = or(use_port_16, _T_176)
node _T_234 = eq(use_port_16, UInt<1>(0h0))
node _T_235 = or(_T_176, _T_234)
node _T_236 = mux(_T_235, UInt<1>(0h0), io.arb_read_reqs[3].bits)
node _T_237 = or(_T_180, _T_236)
node _T_238 = or(issue_read_16, _T_228)
wire issue_read_17 : UInt<1>
connect issue_read_17, UInt<1>(0h0)
wire use_port_17 : UInt<1>
connect use_port_17, UInt<1>(0h0)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = eq(_T_186, UInt<1>(0h0))
node _T_241 = and(_T_239, _T_240)
node _T_242 = and(_T_241, io.arb_read_reqs[3].valid)
when _T_242 :
connect issue_read_17, UInt<1>(0h1)
connect use_port_17, UInt<1>(0h1)
node _data_sels_3_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[3], _data_sels_3_T_2
node _T_243 = or(use_port_17, _T_186)
node _T_244 = eq(use_port_17, UInt<1>(0h0))
node _T_245 = or(_T_186, _T_244)
node _T_246 = mux(_T_245, UInt<1>(0h0), io.arb_read_reqs[3].bits)
node _T_247 = or(_T_190, _T_246)
node _T_248 = or(issue_read_17, _T_238)
wire issue_read_18 : UInt<1>
connect issue_read_18, UInt<1>(0h0)
wire use_port_18 : UInt<1>
connect use_port_18, UInt<1>(0h0)
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = eq(_T_196, UInt<1>(0h0))
node _T_251 = and(_T_249, _T_250)
node _T_252 = and(_T_251, io.arb_read_reqs[3].valid)
when _T_252 :
connect issue_read_18, UInt<1>(0h1)
connect use_port_18, UInt<1>(0h1)
node _data_sels_3_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[3], _data_sels_3_T_3
node _T_253 = or(use_port_18, _T_196)
node _T_254 = eq(use_port_18, UInt<1>(0h0))
node _T_255 = or(_T_196, _T_254)
node _T_256 = mux(_T_255, UInt<1>(0h0), io.arb_read_reqs[3].bits)
node _T_257 = or(_T_200, _T_256)
node _T_258 = or(issue_read_18, _T_248)
wire issue_read_19 : UInt<1>
connect issue_read_19, UInt<1>(0h0)
wire use_port_19 : UInt<1>
connect use_port_19, UInt<1>(0h0)
node _T_259 = eq(_T_258, UInt<1>(0h0))
node _T_260 = eq(_T_206, UInt<1>(0h0))
node _T_261 = and(_T_259, _T_260)
node _T_262 = and(_T_261, io.arb_read_reqs[3].valid)
when _T_262 :
connect issue_read_19, UInt<1>(0h1)
connect use_port_19, UInt<1>(0h1)
node _data_sels_3_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[3], _data_sels_3_T_4
node _T_263 = or(use_port_19, _T_206)
node _T_264 = eq(use_port_19, UInt<1>(0h0))
node _T_265 = or(_T_206, _T_264)
node _T_266 = mux(_T_265, UInt<1>(0h0), io.arb_read_reqs[3].bits)
node _T_267 = or(_T_210, _T_266)
node _T_268 = or(issue_read_19, _T_258)
node _io_arb_read_reqs_3_ready_T = add(io.arb_read_reqs[1].valid, io.arb_read_reqs[2].valid)
node _io_arb_read_reqs_3_ready_T_1 = bits(_io_arb_read_reqs_3_ready_T, 1, 0)
node _io_arb_read_reqs_3_ready_T_2 = add(io.arb_read_reqs[0].valid, _io_arb_read_reqs_3_ready_T_1)
node _io_arb_read_reqs_3_ready_T_3 = bits(_io_arb_read_reqs_3_ready_T_2, 1, 0)
node _io_arb_read_reqs_3_ready_T_4 = lt(_io_arb_read_reqs_3_ready_T_3, UInt<3>(0h5))
connect io.arb_read_reqs[3].ready, _io_arb_read_reqs_3_ready_T_4
node _T_269 = and(io.arb_read_reqs[3].ready, io.arb_read_reqs[3].valid)
node _T_270 = eq(_T_268, UInt<1>(0h0))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(_T_271, UInt<1>(0h0))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_9
assert(clock, _T_272, UInt<1>(0h1), "") : assert_9
wire issue_read_20 : UInt<1>
connect issue_read_20, UInt<1>(0h0)
wire use_port_20 : UInt<1>
connect use_port_20, UInt<1>(0h0)
node _T_276 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_277 = eq(_T_223, UInt<1>(0h0))
node _T_278 = and(_T_276, _T_277)
node _T_279 = and(_T_278, io.arb_read_reqs[4].valid)
when _T_279 :
connect issue_read_20, UInt<1>(0h1)
connect use_port_20, UInt<1>(0h1)
node _data_sels_4_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[4], _data_sels_4_T
node _T_280 = or(use_port_20, _T_223)
node _T_281 = eq(use_port_20, UInt<1>(0h0))
node _T_282 = or(_T_223, _T_281)
node _T_283 = mux(_T_282, UInt<1>(0h0), io.arb_read_reqs[4].bits)
node _T_284 = or(_T_227, _T_283)
node _T_285 = or(issue_read_20, UInt<1>(0h0))
wire issue_read_21 : UInt<1>
connect issue_read_21, UInt<1>(0h0)
wire use_port_21 : UInt<1>
connect use_port_21, UInt<1>(0h0)
node _T_286 = eq(_T_285, UInt<1>(0h0))
node _T_287 = eq(_T_233, UInt<1>(0h0))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_288, io.arb_read_reqs[4].valid)
when _T_289 :
connect issue_read_21, UInt<1>(0h1)
connect use_port_21, UInt<1>(0h1)
node _data_sels_4_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[4], _data_sels_4_T_1
node _T_290 = or(use_port_21, _T_233)
node _T_291 = eq(use_port_21, UInt<1>(0h0))
node _T_292 = or(_T_233, _T_291)
node _T_293 = mux(_T_292, UInt<1>(0h0), io.arb_read_reqs[4].bits)
node _T_294 = or(_T_237, _T_293)
node _T_295 = or(issue_read_21, _T_285)
wire issue_read_22 : UInt<1>
connect issue_read_22, UInt<1>(0h0)
wire use_port_22 : UInt<1>
connect use_port_22, UInt<1>(0h0)
node _T_296 = eq(_T_295, UInt<1>(0h0))
node _T_297 = eq(_T_243, UInt<1>(0h0))
node _T_298 = and(_T_296, _T_297)
node _T_299 = and(_T_298, io.arb_read_reqs[4].valid)
when _T_299 :
connect issue_read_22, UInt<1>(0h1)
connect use_port_22, UInt<1>(0h1)
node _data_sels_4_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[4], _data_sels_4_T_2
node _T_300 = or(use_port_22, _T_243)
node _T_301 = eq(use_port_22, UInt<1>(0h0))
node _T_302 = or(_T_243, _T_301)
node _T_303 = mux(_T_302, UInt<1>(0h0), io.arb_read_reqs[4].bits)
node _T_304 = or(_T_247, _T_303)
node _T_305 = or(issue_read_22, _T_295)
wire issue_read_23 : UInt<1>
connect issue_read_23, UInt<1>(0h0)
wire use_port_23 : UInt<1>
connect use_port_23, UInt<1>(0h0)
node _T_306 = eq(_T_305, UInt<1>(0h0))
node _T_307 = eq(_T_253, UInt<1>(0h0))
node _T_308 = and(_T_306, _T_307)
node _T_309 = and(_T_308, io.arb_read_reqs[4].valid)
when _T_309 :
connect issue_read_23, UInt<1>(0h1)
connect use_port_23, UInt<1>(0h1)
node _data_sels_4_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[4], _data_sels_4_T_3
node _T_310 = or(use_port_23, _T_253)
node _T_311 = eq(use_port_23, UInt<1>(0h0))
node _T_312 = or(_T_253, _T_311)
node _T_313 = mux(_T_312, UInt<1>(0h0), io.arb_read_reqs[4].bits)
node _T_314 = or(_T_257, _T_313)
node _T_315 = or(issue_read_23, _T_305)
wire issue_read_24 : UInt<1>
connect issue_read_24, UInt<1>(0h0)
wire use_port_24 : UInt<1>
connect use_port_24, UInt<1>(0h0)
node _T_316 = eq(_T_315, UInt<1>(0h0))
node _T_317 = eq(_T_263, UInt<1>(0h0))
node _T_318 = and(_T_316, _T_317)
node _T_319 = and(_T_318, io.arb_read_reqs[4].valid)
when _T_319 :
connect issue_read_24, UInt<1>(0h1)
connect use_port_24, UInt<1>(0h1)
node _data_sels_4_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[4], _data_sels_4_T_4
node _T_320 = or(use_port_24, _T_263)
node _T_321 = eq(use_port_24, UInt<1>(0h0))
node _T_322 = or(_T_263, _T_321)
node _T_323 = mux(_T_322, UInt<1>(0h0), io.arb_read_reqs[4].bits)
node _T_324 = or(_T_267, _T_323)
node _T_325 = or(issue_read_24, _T_315)
node _io_arb_read_reqs_4_ready_T = add(io.arb_read_reqs[0].valid, io.arb_read_reqs[1].valid)
node _io_arb_read_reqs_4_ready_T_1 = bits(_io_arb_read_reqs_4_ready_T, 1, 0)
node _io_arb_read_reqs_4_ready_T_2 = add(io.arb_read_reqs[2].valid, io.arb_read_reqs[3].valid)
node _io_arb_read_reqs_4_ready_T_3 = bits(_io_arb_read_reqs_4_ready_T_2, 1, 0)
node _io_arb_read_reqs_4_ready_T_4 = add(_io_arb_read_reqs_4_ready_T_1, _io_arb_read_reqs_4_ready_T_3)
node _io_arb_read_reqs_4_ready_T_5 = bits(_io_arb_read_reqs_4_ready_T_4, 2, 0)
node _io_arb_read_reqs_4_ready_T_6 = lt(_io_arb_read_reqs_4_ready_T_5, UInt<3>(0h5))
connect io.arb_read_reqs[4].ready, _io_arb_read_reqs_4_ready_T_6
node _T_326 = and(io.arb_read_reqs[4].ready, io.arb_read_reqs[4].valid)
node _T_327 = eq(_T_325, UInt<1>(0h0))
node _T_328 = and(_T_326, _T_327)
node _T_329 = eq(_T_328, UInt<1>(0h0))
node _T_330 = asUInt(reset)
node _T_331 = eq(_T_330, UInt<1>(0h0))
when _T_331 :
node _T_332 = eq(_T_329, UInt<1>(0h0))
when _T_332 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_10
assert(clock, _T_329, UInt<1>(0h1), "") : assert_10
wire issue_read_25 : UInt<1>
connect issue_read_25, UInt<1>(0h0)
wire use_port_25 : UInt<1>
connect use_port_25, UInt<1>(0h0)
node _T_333 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = eq(_T_280, UInt<1>(0h0))
node _T_335 = and(_T_333, _T_334)
node _T_336 = and(_T_335, io.arb_read_reqs[5].valid)
when _T_336 :
connect issue_read_25, UInt<1>(0h1)
connect use_port_25, UInt<1>(0h1)
node _data_sels_5_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[5], _data_sels_5_T
node _T_337 = or(use_port_25, _T_280)
node _T_338 = eq(use_port_25, UInt<1>(0h0))
node _T_339 = or(_T_280, _T_338)
node _T_340 = mux(_T_339, UInt<1>(0h0), io.arb_read_reqs[5].bits)
node _T_341 = or(_T_284, _T_340)
node _T_342 = or(issue_read_25, UInt<1>(0h0))
wire issue_read_26 : UInt<1>
connect issue_read_26, UInt<1>(0h0)
wire use_port_26 : UInt<1>
connect use_port_26, UInt<1>(0h0)
node _T_343 = eq(_T_342, UInt<1>(0h0))
node _T_344 = eq(_T_290, UInt<1>(0h0))
node _T_345 = and(_T_343, _T_344)
node _T_346 = and(_T_345, io.arb_read_reqs[5].valid)
when _T_346 :
connect issue_read_26, UInt<1>(0h1)
connect use_port_26, UInt<1>(0h1)
node _data_sels_5_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[5], _data_sels_5_T_1
node _T_347 = or(use_port_26, _T_290)
node _T_348 = eq(use_port_26, UInt<1>(0h0))
node _T_349 = or(_T_290, _T_348)
node _T_350 = mux(_T_349, UInt<1>(0h0), io.arb_read_reqs[5].bits)
node _T_351 = or(_T_294, _T_350)
node _T_352 = or(issue_read_26, _T_342)
wire issue_read_27 : UInt<1>
connect issue_read_27, UInt<1>(0h0)
wire use_port_27 : UInt<1>
connect use_port_27, UInt<1>(0h0)
node _T_353 = eq(_T_352, UInt<1>(0h0))
node _T_354 = eq(_T_300, UInt<1>(0h0))
node _T_355 = and(_T_353, _T_354)
node _T_356 = and(_T_355, io.arb_read_reqs[5].valid)
when _T_356 :
connect issue_read_27, UInt<1>(0h1)
connect use_port_27, UInt<1>(0h1)
node _data_sels_5_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[5], _data_sels_5_T_2
node _T_357 = or(use_port_27, _T_300)
node _T_358 = eq(use_port_27, UInt<1>(0h0))
node _T_359 = or(_T_300, _T_358)
node _T_360 = mux(_T_359, UInt<1>(0h0), io.arb_read_reqs[5].bits)
node _T_361 = or(_T_304, _T_360)
node _T_362 = or(issue_read_27, _T_352)
wire issue_read_28 : UInt<1>
connect issue_read_28, UInt<1>(0h0)
wire use_port_28 : UInt<1>
connect use_port_28, UInt<1>(0h0)
node _T_363 = eq(_T_362, UInt<1>(0h0))
node _T_364 = eq(_T_310, UInt<1>(0h0))
node _T_365 = and(_T_363, _T_364)
node _T_366 = and(_T_365, io.arb_read_reqs[5].valid)
when _T_366 :
connect issue_read_28, UInt<1>(0h1)
connect use_port_28, UInt<1>(0h1)
node _data_sels_5_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[5], _data_sels_5_T_3
node _T_367 = or(use_port_28, _T_310)
node _T_368 = eq(use_port_28, UInt<1>(0h0))
node _T_369 = or(_T_310, _T_368)
node _T_370 = mux(_T_369, UInt<1>(0h0), io.arb_read_reqs[5].bits)
node _T_371 = or(_T_314, _T_370)
node _T_372 = or(issue_read_28, _T_362)
wire issue_read_29 : UInt<1>
connect issue_read_29, UInt<1>(0h0)
wire use_port_29 : UInt<1>
connect use_port_29, UInt<1>(0h0)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = eq(_T_320, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
node _T_376 = and(_T_375, io.arb_read_reqs[5].valid)
when _T_376 :
connect issue_read_29, UInt<1>(0h1)
connect use_port_29, UInt<1>(0h1)
node _data_sels_5_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[5], _data_sels_5_T_4
node _T_377 = or(use_port_29, _T_320)
node _T_378 = eq(use_port_29, UInt<1>(0h0))
node _T_379 = or(_T_320, _T_378)
node _T_380 = mux(_T_379, UInt<1>(0h0), io.arb_read_reqs[5].bits)
node _T_381 = or(_T_324, _T_380)
node _T_382 = or(issue_read_29, _T_372)
node _io_arb_read_reqs_5_ready_T = add(io.arb_read_reqs[0].valid, io.arb_read_reqs[1].valid)
node _io_arb_read_reqs_5_ready_T_1 = bits(_io_arb_read_reqs_5_ready_T, 1, 0)
node _io_arb_read_reqs_5_ready_T_2 = add(io.arb_read_reqs[3].valid, io.arb_read_reqs[4].valid)
node _io_arb_read_reqs_5_ready_T_3 = bits(_io_arb_read_reqs_5_ready_T_2, 1, 0)
node _io_arb_read_reqs_5_ready_T_4 = add(io.arb_read_reqs[2].valid, _io_arb_read_reqs_5_ready_T_3)
node _io_arb_read_reqs_5_ready_T_5 = bits(_io_arb_read_reqs_5_ready_T_4, 1, 0)
node _io_arb_read_reqs_5_ready_T_6 = add(_io_arb_read_reqs_5_ready_T_1, _io_arb_read_reqs_5_ready_T_5)
node _io_arb_read_reqs_5_ready_T_7 = bits(_io_arb_read_reqs_5_ready_T_6, 2, 0)
node _io_arb_read_reqs_5_ready_T_8 = lt(_io_arb_read_reqs_5_ready_T_7, UInt<3>(0h5))
connect io.arb_read_reqs[5].ready, _io_arb_read_reqs_5_ready_T_8
node _T_383 = and(io.arb_read_reqs[5].ready, io.arb_read_reqs[5].valid)
node _T_384 = eq(_T_382, UInt<1>(0h0))
node _T_385 = and(_T_383, _T_384)
node _T_386 = eq(_T_385, UInt<1>(0h0))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_11
assert(clock, _T_386, UInt<1>(0h1), "") : assert_11
wire issue_read_30 : UInt<1>
connect issue_read_30, UInt<1>(0h0)
wire use_port_30 : UInt<1>
connect use_port_30, UInt<1>(0h0)
node _T_390 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_391 = eq(_T_337, UInt<1>(0h0))
node _T_392 = and(_T_390, _T_391)
node _T_393 = and(_T_392, io.arb_read_reqs[6].valid)
when _T_393 :
connect issue_read_30, UInt<1>(0h1)
connect use_port_30, UInt<1>(0h1)
node _data_sels_6_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[6], _data_sels_6_T
node _T_394 = or(use_port_30, _T_337)
node _T_395 = eq(use_port_30, UInt<1>(0h0))
node _T_396 = or(_T_337, _T_395)
node _T_397 = mux(_T_396, UInt<1>(0h0), io.arb_read_reqs[6].bits)
node _T_398 = or(_T_341, _T_397)
node _T_399 = or(issue_read_30, UInt<1>(0h0))
wire issue_read_31 : UInt<1>
connect issue_read_31, UInt<1>(0h0)
wire use_port_31 : UInt<1>
connect use_port_31, UInt<1>(0h0)
node _T_400 = eq(_T_399, UInt<1>(0h0))
node _T_401 = eq(_T_347, UInt<1>(0h0))
node _T_402 = and(_T_400, _T_401)
node _T_403 = and(_T_402, io.arb_read_reqs[6].valid)
when _T_403 :
connect issue_read_31, UInt<1>(0h1)
connect use_port_31, UInt<1>(0h1)
node _data_sels_6_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[6], _data_sels_6_T_1
node _T_404 = or(use_port_31, _T_347)
node _T_405 = eq(use_port_31, UInt<1>(0h0))
node _T_406 = or(_T_347, _T_405)
node _T_407 = mux(_T_406, UInt<1>(0h0), io.arb_read_reqs[6].bits)
node _T_408 = or(_T_351, _T_407)
node _T_409 = or(issue_read_31, _T_399)
wire issue_read_32 : UInt<1>
connect issue_read_32, UInt<1>(0h0)
wire use_port_32 : UInt<1>
connect use_port_32, UInt<1>(0h0)
node _T_410 = eq(_T_409, UInt<1>(0h0))
node _T_411 = eq(_T_357, UInt<1>(0h0))
node _T_412 = and(_T_410, _T_411)
node _T_413 = and(_T_412, io.arb_read_reqs[6].valid)
when _T_413 :
connect issue_read_32, UInt<1>(0h1)
connect use_port_32, UInt<1>(0h1)
node _data_sels_6_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[6], _data_sels_6_T_2
node _T_414 = or(use_port_32, _T_357)
node _T_415 = eq(use_port_32, UInt<1>(0h0))
node _T_416 = or(_T_357, _T_415)
node _T_417 = mux(_T_416, UInt<1>(0h0), io.arb_read_reqs[6].bits)
node _T_418 = or(_T_361, _T_417)
node _T_419 = or(issue_read_32, _T_409)
wire issue_read_33 : UInt<1>
connect issue_read_33, UInt<1>(0h0)
wire use_port_33 : UInt<1>
connect use_port_33, UInt<1>(0h0)
node _T_420 = eq(_T_419, UInt<1>(0h0))
node _T_421 = eq(_T_367, UInt<1>(0h0))
node _T_422 = and(_T_420, _T_421)
node _T_423 = and(_T_422, io.arb_read_reqs[6].valid)
when _T_423 :
connect issue_read_33, UInt<1>(0h1)
connect use_port_33, UInt<1>(0h1)
node _data_sels_6_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[6], _data_sels_6_T_3
node _T_424 = or(use_port_33, _T_367)
node _T_425 = eq(use_port_33, UInt<1>(0h0))
node _T_426 = or(_T_367, _T_425)
node _T_427 = mux(_T_426, UInt<1>(0h0), io.arb_read_reqs[6].bits)
node _T_428 = or(_T_371, _T_427)
node _T_429 = or(issue_read_33, _T_419)
wire issue_read_34 : UInt<1>
connect issue_read_34, UInt<1>(0h0)
wire use_port_34 : UInt<1>
connect use_port_34, UInt<1>(0h0)
node _T_430 = eq(_T_429, UInt<1>(0h0))
node _T_431 = eq(_T_377, UInt<1>(0h0))
node _T_432 = and(_T_430, _T_431)
node _T_433 = and(_T_432, io.arb_read_reqs[6].valid)
when _T_433 :
connect issue_read_34, UInt<1>(0h1)
connect use_port_34, UInt<1>(0h1)
node _data_sels_6_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[6], _data_sels_6_T_4
node _T_434 = or(use_port_34, _T_377)
node _T_435 = eq(use_port_34, UInt<1>(0h0))
node _T_436 = or(_T_377, _T_435)
node _T_437 = mux(_T_436, UInt<1>(0h0), io.arb_read_reqs[6].bits)
node _T_438 = or(_T_381, _T_437)
node _T_439 = or(issue_read_34, _T_429)
node _io_arb_read_reqs_6_ready_T = add(io.arb_read_reqs[1].valid, io.arb_read_reqs[2].valid)
node _io_arb_read_reqs_6_ready_T_1 = bits(_io_arb_read_reqs_6_ready_T, 1, 0)
node _io_arb_read_reqs_6_ready_T_2 = add(io.arb_read_reqs[0].valid, _io_arb_read_reqs_6_ready_T_1)
node _io_arb_read_reqs_6_ready_T_3 = bits(_io_arb_read_reqs_6_ready_T_2, 1, 0)
node _io_arb_read_reqs_6_ready_T_4 = add(io.arb_read_reqs[4].valid, io.arb_read_reqs[5].valid)
node _io_arb_read_reqs_6_ready_T_5 = bits(_io_arb_read_reqs_6_ready_T_4, 1, 0)
node _io_arb_read_reqs_6_ready_T_6 = add(io.arb_read_reqs[3].valid, _io_arb_read_reqs_6_ready_T_5)
node _io_arb_read_reqs_6_ready_T_7 = bits(_io_arb_read_reqs_6_ready_T_6, 1, 0)
node _io_arb_read_reqs_6_ready_T_8 = add(_io_arb_read_reqs_6_ready_T_3, _io_arb_read_reqs_6_ready_T_7)
node _io_arb_read_reqs_6_ready_T_9 = bits(_io_arb_read_reqs_6_ready_T_8, 2, 0)
node _io_arb_read_reqs_6_ready_T_10 = lt(_io_arb_read_reqs_6_ready_T_9, UInt<3>(0h5))
connect io.arb_read_reqs[6].ready, _io_arb_read_reqs_6_ready_T_10
node _T_440 = and(io.arb_read_reqs[6].ready, io.arb_read_reqs[6].valid)
node _T_441 = eq(_T_439, UInt<1>(0h0))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(_T_442, UInt<1>(0h0))
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_12
assert(clock, _T_443, UInt<1>(0h1), "") : assert_12
wire issue_read_35 : UInt<1>
connect issue_read_35, UInt<1>(0h0)
wire use_port_35 : UInt<1>
connect use_port_35, UInt<1>(0h0)
node _T_447 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_448 = eq(_T_394, UInt<1>(0h0))
node _T_449 = and(_T_447, _T_448)
node _T_450 = and(_T_449, io.arb_read_reqs[7].valid)
when _T_450 :
connect issue_read_35, UInt<1>(0h1)
connect use_port_35, UInt<1>(0h1)
node _data_sels_7_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
connect data_sels[7], _data_sels_7_T
node _T_451 = or(use_port_35, _T_394)
node _T_452 = eq(use_port_35, UInt<1>(0h0))
node _T_453 = or(_T_394, _T_452)
node _T_454 = mux(_T_453, UInt<1>(0h0), io.arb_read_reqs[7].bits)
node _T_455 = or(_T_398, _T_454)
node _T_456 = or(issue_read_35, UInt<1>(0h0))
wire issue_read_36 : UInt<1>
connect issue_read_36, UInt<1>(0h0)
wire use_port_36 : UInt<1>
connect use_port_36, UInt<1>(0h0)
node _T_457 = eq(_T_456, UInt<1>(0h0))
node _T_458 = eq(_T_404, UInt<1>(0h0))
node _T_459 = and(_T_457, _T_458)
node _T_460 = and(_T_459, io.arb_read_reqs[7].valid)
when _T_460 :
connect issue_read_36, UInt<1>(0h1)
connect use_port_36, UInt<1>(0h1)
node _data_sels_7_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1))
connect data_sels[7], _data_sels_7_T_1
node _T_461 = or(use_port_36, _T_404)
node _T_462 = eq(use_port_36, UInt<1>(0h0))
node _T_463 = or(_T_404, _T_462)
node _T_464 = mux(_T_463, UInt<1>(0h0), io.arb_read_reqs[7].bits)
node _T_465 = or(_T_408, _T_464)
node _T_466 = or(issue_read_36, _T_456)
wire issue_read_37 : UInt<1>
connect issue_read_37, UInt<1>(0h0)
wire use_port_37 : UInt<1>
connect use_port_37, UInt<1>(0h0)
node _T_467 = eq(_T_466, UInt<1>(0h0))
node _T_468 = eq(_T_414, UInt<1>(0h0))
node _T_469 = and(_T_467, _T_468)
node _T_470 = and(_T_469, io.arb_read_reqs[7].valid)
when _T_470 :
connect issue_read_37, UInt<1>(0h1)
connect use_port_37, UInt<1>(0h1)
node _data_sels_7_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
connect data_sels[7], _data_sels_7_T_2
node _T_471 = or(use_port_37, _T_414)
node _T_472 = eq(use_port_37, UInt<1>(0h0))
node _T_473 = or(_T_414, _T_472)
node _T_474 = mux(_T_473, UInt<1>(0h0), io.arb_read_reqs[7].bits)
node _T_475 = or(_T_418, _T_474)
node _T_476 = or(issue_read_37, _T_466)
wire issue_read_38 : UInt<1>
connect issue_read_38, UInt<1>(0h0)
wire use_port_38 : UInt<1>
connect use_port_38, UInt<1>(0h0)
node _T_477 = eq(_T_476, UInt<1>(0h0))
node _T_478 = eq(_T_424, UInt<1>(0h0))
node _T_479 = and(_T_477, _T_478)
node _T_480 = and(_T_479, io.arb_read_reqs[7].valid)
when _T_480 :
connect issue_read_38, UInt<1>(0h1)
connect use_port_38, UInt<1>(0h1)
node _data_sels_7_T_3 = dshl(UInt<1>(0h1), UInt<2>(0h3))
connect data_sels[7], _data_sels_7_T_3
node _T_481 = or(use_port_38, _T_424)
node _T_482 = eq(use_port_38, UInt<1>(0h0))
node _T_483 = or(_T_424, _T_482)
node _T_484 = mux(_T_483, UInt<1>(0h0), io.arb_read_reqs[7].bits)
node _T_485 = or(_T_428, _T_484)
node _T_486 = or(issue_read_38, _T_476)
wire issue_read_39 : UInt<1>
connect issue_read_39, UInt<1>(0h0)
wire use_port_39 : UInt<1>
connect use_port_39, UInt<1>(0h0)
node _T_487 = eq(_T_486, UInt<1>(0h0))
node _T_488 = eq(_T_434, UInt<1>(0h0))
node _T_489 = and(_T_487, _T_488)
node _T_490 = and(_T_489, io.arb_read_reqs[7].valid)
when _T_490 :
connect issue_read_39, UInt<1>(0h1)
connect use_port_39, UInt<1>(0h1)
node _data_sels_7_T_4 = dshl(UInt<1>(0h1), UInt<3>(0h4))
connect data_sels[7], _data_sels_7_T_4
node _T_491 = or(use_port_39, _T_434)
node _T_492 = eq(use_port_39, UInt<1>(0h0))
node _T_493 = or(_T_434, _T_492)
node _T_494 = mux(_T_493, UInt<1>(0h0), io.arb_read_reqs[7].bits)
node _T_495 = or(_T_438, _T_494)
node _T_496 = or(issue_read_39, _T_486)
node _io_arb_read_reqs_7_ready_T = add(io.arb_read_reqs[1].valid, io.arb_read_reqs[2].valid)
node _io_arb_read_reqs_7_ready_T_1 = bits(_io_arb_read_reqs_7_ready_T, 1, 0)
node _io_arb_read_reqs_7_ready_T_2 = add(io.arb_read_reqs[0].valid, _io_arb_read_reqs_7_ready_T_1)
node _io_arb_read_reqs_7_ready_T_3 = bits(_io_arb_read_reqs_7_ready_T_2, 1, 0)
node _io_arb_read_reqs_7_ready_T_4 = add(io.arb_read_reqs[3].valid, io.arb_read_reqs[4].valid)
node _io_arb_read_reqs_7_ready_T_5 = bits(_io_arb_read_reqs_7_ready_T_4, 1, 0)
node _io_arb_read_reqs_7_ready_T_6 = add(io.arb_read_reqs[5].valid, io.arb_read_reqs[6].valid)
node _io_arb_read_reqs_7_ready_T_7 = bits(_io_arb_read_reqs_7_ready_T_6, 1, 0)
node _io_arb_read_reqs_7_ready_T_8 = add(_io_arb_read_reqs_7_ready_T_5, _io_arb_read_reqs_7_ready_T_7)
node _io_arb_read_reqs_7_ready_T_9 = bits(_io_arb_read_reqs_7_ready_T_8, 2, 0)
node _io_arb_read_reqs_7_ready_T_10 = add(_io_arb_read_reqs_7_ready_T_3, _io_arb_read_reqs_7_ready_T_9)
node _io_arb_read_reqs_7_ready_T_11 = bits(_io_arb_read_reqs_7_ready_T_10, 2, 0)
node _io_arb_read_reqs_7_ready_T_12 = lt(_io_arb_read_reqs_7_ready_T_11, UInt<3>(0h5))
connect io.arb_read_reqs[7].ready, _io_arb_read_reqs_7_ready_T_12
node _T_497 = and(io.arb_read_reqs[7].ready, io.arb_read_reqs[7].valid)
node _T_498 = eq(_T_496, UInt<1>(0h0))
node _T_499 = and(_T_497, _T_498)
node _T_500 = eq(_T_499, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:168 assert(!(io.arb_read_reqs(i).fire && !read_issued))\n") : printf_13
assert(clock, _T_500, UInt<1>(0h1), "") : assert_13
connect rf.io.arb_read_reqs[0].valid, _T_451
connect rf.io.arb_read_reqs[0].bits, _T_455
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(rf.io.arb_read_reqs[0].ready, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:174 assert(rf.io.arb_read_reqs(j).ready)\n") : printf_14
assert(clock, rf.io.arb_read_reqs[0].ready, UInt<1>(0h1), "") : assert_14
connect rf.io.arb_read_reqs[1].valid, _T_461
connect rf.io.arb_read_reqs[1].bits, _T_465
node _T_507 = asUInt(reset)
node _T_508 = eq(_T_507, UInt<1>(0h0))
when _T_508 :
node _T_509 = eq(rf.io.arb_read_reqs[1].ready, UInt<1>(0h0))
when _T_509 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:174 assert(rf.io.arb_read_reqs(j).ready)\n") : printf_15
assert(clock, rf.io.arb_read_reqs[1].ready, UInt<1>(0h1), "") : assert_15
connect rf.io.arb_read_reqs[2].valid, _T_471
connect rf.io.arb_read_reqs[2].bits, _T_475
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(rf.io.arb_read_reqs[2].ready, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:174 assert(rf.io.arb_read_reqs(j).ready)\n") : printf_16
assert(clock, rf.io.arb_read_reqs[2].ready, UInt<1>(0h1), "") : assert_16
connect rf.io.arb_read_reqs[3].valid, _T_481
connect rf.io.arb_read_reqs[3].bits, _T_485
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(rf.io.arb_read_reqs[3].ready, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:174 assert(rf.io.arb_read_reqs(j).ready)\n") : printf_17
assert(clock, rf.io.arb_read_reqs[3].ready, UInt<1>(0h1), "") : assert_17
connect rf.io.arb_read_reqs[4].valid, _T_491
connect rf.io.arb_read_reqs[4].bits, _T_495
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(rf.io.arb_read_reqs[4].ready, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at regfile.scala:174 assert(rf.io.arb_read_reqs(j).ready)\n") : printf_18
assert(clock, rf.io.arb_read_reqs[4].ready, UInt<1>(0h1), "") : assert_18
reg rrd_data_sels : UInt<5>[8], clock
connect rrd_data_sels, data_sels
node _io_rrd_read_resps_0_T = bits(rrd_data_sels[0], 0, 0)
node _io_rrd_read_resps_0_T_1 = bits(rrd_data_sels[0], 1, 1)
node _io_rrd_read_resps_0_T_2 = bits(rrd_data_sels[0], 2, 2)
node _io_rrd_read_resps_0_T_3 = bits(rrd_data_sels[0], 3, 3)
node _io_rrd_read_resps_0_T_4 = bits(rrd_data_sels[0], 4, 4)
node _io_rrd_read_resps_0_T_5 = mux(_io_rrd_read_resps_0_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_0_T_6 = mux(_io_rrd_read_resps_0_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_0_T_7 = mux(_io_rrd_read_resps_0_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_0_T_8 = mux(_io_rrd_read_resps_0_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_0_T_9 = mux(_io_rrd_read_resps_0_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_0_T_10 = or(_io_rrd_read_resps_0_T_5, _io_rrd_read_resps_0_T_6)
node _io_rrd_read_resps_0_T_11 = or(_io_rrd_read_resps_0_T_10, _io_rrd_read_resps_0_T_7)
node _io_rrd_read_resps_0_T_12 = or(_io_rrd_read_resps_0_T_11, _io_rrd_read_resps_0_T_8)
node _io_rrd_read_resps_0_T_13 = or(_io_rrd_read_resps_0_T_12, _io_rrd_read_resps_0_T_9)
wire _io_rrd_read_resps_0_WIRE : UInt<64>
connect _io_rrd_read_resps_0_WIRE, _io_rrd_read_resps_0_T_13
connect io.rrd_read_resps[0], _io_rrd_read_resps_0_WIRE
node _io_rrd_read_resps_1_T = bits(rrd_data_sels[1], 0, 0)
node _io_rrd_read_resps_1_T_1 = bits(rrd_data_sels[1], 1, 1)
node _io_rrd_read_resps_1_T_2 = bits(rrd_data_sels[1], 2, 2)
node _io_rrd_read_resps_1_T_3 = bits(rrd_data_sels[1], 3, 3)
node _io_rrd_read_resps_1_T_4 = bits(rrd_data_sels[1], 4, 4)
node _io_rrd_read_resps_1_T_5 = mux(_io_rrd_read_resps_1_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_1_T_6 = mux(_io_rrd_read_resps_1_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_1_T_7 = mux(_io_rrd_read_resps_1_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_1_T_8 = mux(_io_rrd_read_resps_1_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_1_T_9 = mux(_io_rrd_read_resps_1_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_1_T_10 = or(_io_rrd_read_resps_1_T_5, _io_rrd_read_resps_1_T_6)
node _io_rrd_read_resps_1_T_11 = or(_io_rrd_read_resps_1_T_10, _io_rrd_read_resps_1_T_7)
node _io_rrd_read_resps_1_T_12 = or(_io_rrd_read_resps_1_T_11, _io_rrd_read_resps_1_T_8)
node _io_rrd_read_resps_1_T_13 = or(_io_rrd_read_resps_1_T_12, _io_rrd_read_resps_1_T_9)
wire _io_rrd_read_resps_1_WIRE : UInt<64>
connect _io_rrd_read_resps_1_WIRE, _io_rrd_read_resps_1_T_13
connect io.rrd_read_resps[1], _io_rrd_read_resps_1_WIRE
node _io_rrd_read_resps_2_T = bits(rrd_data_sels[2], 0, 0)
node _io_rrd_read_resps_2_T_1 = bits(rrd_data_sels[2], 1, 1)
node _io_rrd_read_resps_2_T_2 = bits(rrd_data_sels[2], 2, 2)
node _io_rrd_read_resps_2_T_3 = bits(rrd_data_sels[2], 3, 3)
node _io_rrd_read_resps_2_T_4 = bits(rrd_data_sels[2], 4, 4)
node _io_rrd_read_resps_2_T_5 = mux(_io_rrd_read_resps_2_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_2_T_6 = mux(_io_rrd_read_resps_2_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_2_T_7 = mux(_io_rrd_read_resps_2_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_2_T_8 = mux(_io_rrd_read_resps_2_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_2_T_9 = mux(_io_rrd_read_resps_2_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_2_T_10 = or(_io_rrd_read_resps_2_T_5, _io_rrd_read_resps_2_T_6)
node _io_rrd_read_resps_2_T_11 = or(_io_rrd_read_resps_2_T_10, _io_rrd_read_resps_2_T_7)
node _io_rrd_read_resps_2_T_12 = or(_io_rrd_read_resps_2_T_11, _io_rrd_read_resps_2_T_8)
node _io_rrd_read_resps_2_T_13 = or(_io_rrd_read_resps_2_T_12, _io_rrd_read_resps_2_T_9)
wire _io_rrd_read_resps_2_WIRE : UInt<64>
connect _io_rrd_read_resps_2_WIRE, _io_rrd_read_resps_2_T_13
connect io.rrd_read_resps[2], _io_rrd_read_resps_2_WIRE
node _io_rrd_read_resps_3_T = bits(rrd_data_sels[3], 0, 0)
node _io_rrd_read_resps_3_T_1 = bits(rrd_data_sels[3], 1, 1)
node _io_rrd_read_resps_3_T_2 = bits(rrd_data_sels[3], 2, 2)
node _io_rrd_read_resps_3_T_3 = bits(rrd_data_sels[3], 3, 3)
node _io_rrd_read_resps_3_T_4 = bits(rrd_data_sels[3], 4, 4)
node _io_rrd_read_resps_3_T_5 = mux(_io_rrd_read_resps_3_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_3_T_6 = mux(_io_rrd_read_resps_3_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_3_T_7 = mux(_io_rrd_read_resps_3_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_3_T_8 = mux(_io_rrd_read_resps_3_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_3_T_9 = mux(_io_rrd_read_resps_3_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_3_T_10 = or(_io_rrd_read_resps_3_T_5, _io_rrd_read_resps_3_T_6)
node _io_rrd_read_resps_3_T_11 = or(_io_rrd_read_resps_3_T_10, _io_rrd_read_resps_3_T_7)
node _io_rrd_read_resps_3_T_12 = or(_io_rrd_read_resps_3_T_11, _io_rrd_read_resps_3_T_8)
node _io_rrd_read_resps_3_T_13 = or(_io_rrd_read_resps_3_T_12, _io_rrd_read_resps_3_T_9)
wire _io_rrd_read_resps_3_WIRE : UInt<64>
connect _io_rrd_read_resps_3_WIRE, _io_rrd_read_resps_3_T_13
connect io.rrd_read_resps[3], _io_rrd_read_resps_3_WIRE
node _io_rrd_read_resps_4_T = bits(rrd_data_sels[4], 0, 0)
node _io_rrd_read_resps_4_T_1 = bits(rrd_data_sels[4], 1, 1)
node _io_rrd_read_resps_4_T_2 = bits(rrd_data_sels[4], 2, 2)
node _io_rrd_read_resps_4_T_3 = bits(rrd_data_sels[4], 3, 3)
node _io_rrd_read_resps_4_T_4 = bits(rrd_data_sels[4], 4, 4)
node _io_rrd_read_resps_4_T_5 = mux(_io_rrd_read_resps_4_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_4_T_6 = mux(_io_rrd_read_resps_4_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_4_T_7 = mux(_io_rrd_read_resps_4_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_4_T_8 = mux(_io_rrd_read_resps_4_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_4_T_9 = mux(_io_rrd_read_resps_4_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_4_T_10 = or(_io_rrd_read_resps_4_T_5, _io_rrd_read_resps_4_T_6)
node _io_rrd_read_resps_4_T_11 = or(_io_rrd_read_resps_4_T_10, _io_rrd_read_resps_4_T_7)
node _io_rrd_read_resps_4_T_12 = or(_io_rrd_read_resps_4_T_11, _io_rrd_read_resps_4_T_8)
node _io_rrd_read_resps_4_T_13 = or(_io_rrd_read_resps_4_T_12, _io_rrd_read_resps_4_T_9)
wire _io_rrd_read_resps_4_WIRE : UInt<64>
connect _io_rrd_read_resps_4_WIRE, _io_rrd_read_resps_4_T_13
connect io.rrd_read_resps[4], _io_rrd_read_resps_4_WIRE
node _io_rrd_read_resps_5_T = bits(rrd_data_sels[5], 0, 0)
node _io_rrd_read_resps_5_T_1 = bits(rrd_data_sels[5], 1, 1)
node _io_rrd_read_resps_5_T_2 = bits(rrd_data_sels[5], 2, 2)
node _io_rrd_read_resps_5_T_3 = bits(rrd_data_sels[5], 3, 3)
node _io_rrd_read_resps_5_T_4 = bits(rrd_data_sels[5], 4, 4)
node _io_rrd_read_resps_5_T_5 = mux(_io_rrd_read_resps_5_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_5_T_6 = mux(_io_rrd_read_resps_5_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_5_T_7 = mux(_io_rrd_read_resps_5_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_5_T_8 = mux(_io_rrd_read_resps_5_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_5_T_9 = mux(_io_rrd_read_resps_5_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_5_T_10 = or(_io_rrd_read_resps_5_T_5, _io_rrd_read_resps_5_T_6)
node _io_rrd_read_resps_5_T_11 = or(_io_rrd_read_resps_5_T_10, _io_rrd_read_resps_5_T_7)
node _io_rrd_read_resps_5_T_12 = or(_io_rrd_read_resps_5_T_11, _io_rrd_read_resps_5_T_8)
node _io_rrd_read_resps_5_T_13 = or(_io_rrd_read_resps_5_T_12, _io_rrd_read_resps_5_T_9)
wire _io_rrd_read_resps_5_WIRE : UInt<64>
connect _io_rrd_read_resps_5_WIRE, _io_rrd_read_resps_5_T_13
connect io.rrd_read_resps[5], _io_rrd_read_resps_5_WIRE
node _io_rrd_read_resps_6_T = bits(rrd_data_sels[6], 0, 0)
node _io_rrd_read_resps_6_T_1 = bits(rrd_data_sels[6], 1, 1)
node _io_rrd_read_resps_6_T_2 = bits(rrd_data_sels[6], 2, 2)
node _io_rrd_read_resps_6_T_3 = bits(rrd_data_sels[6], 3, 3)
node _io_rrd_read_resps_6_T_4 = bits(rrd_data_sels[6], 4, 4)
node _io_rrd_read_resps_6_T_5 = mux(_io_rrd_read_resps_6_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_6_T_6 = mux(_io_rrd_read_resps_6_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_6_T_7 = mux(_io_rrd_read_resps_6_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_6_T_8 = mux(_io_rrd_read_resps_6_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_6_T_9 = mux(_io_rrd_read_resps_6_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_6_T_10 = or(_io_rrd_read_resps_6_T_5, _io_rrd_read_resps_6_T_6)
node _io_rrd_read_resps_6_T_11 = or(_io_rrd_read_resps_6_T_10, _io_rrd_read_resps_6_T_7)
node _io_rrd_read_resps_6_T_12 = or(_io_rrd_read_resps_6_T_11, _io_rrd_read_resps_6_T_8)
node _io_rrd_read_resps_6_T_13 = or(_io_rrd_read_resps_6_T_12, _io_rrd_read_resps_6_T_9)
wire _io_rrd_read_resps_6_WIRE : UInt<64>
connect _io_rrd_read_resps_6_WIRE, _io_rrd_read_resps_6_T_13
connect io.rrd_read_resps[6], _io_rrd_read_resps_6_WIRE
node _io_rrd_read_resps_7_T = bits(rrd_data_sels[7], 0, 0)
node _io_rrd_read_resps_7_T_1 = bits(rrd_data_sels[7], 1, 1)
node _io_rrd_read_resps_7_T_2 = bits(rrd_data_sels[7], 2, 2)
node _io_rrd_read_resps_7_T_3 = bits(rrd_data_sels[7], 3, 3)
node _io_rrd_read_resps_7_T_4 = bits(rrd_data_sels[7], 4, 4)
node _io_rrd_read_resps_7_T_5 = mux(_io_rrd_read_resps_7_T, rf.io.rrd_read_resps[0], UInt<1>(0h0))
node _io_rrd_read_resps_7_T_6 = mux(_io_rrd_read_resps_7_T_1, rf.io.rrd_read_resps[1], UInt<1>(0h0))
node _io_rrd_read_resps_7_T_7 = mux(_io_rrd_read_resps_7_T_2, rf.io.rrd_read_resps[2], UInt<1>(0h0))
node _io_rrd_read_resps_7_T_8 = mux(_io_rrd_read_resps_7_T_3, rf.io.rrd_read_resps[3], UInt<1>(0h0))
node _io_rrd_read_resps_7_T_9 = mux(_io_rrd_read_resps_7_T_4, rf.io.rrd_read_resps[4], UInt<1>(0h0))
node _io_rrd_read_resps_7_T_10 = or(_io_rrd_read_resps_7_T_5, _io_rrd_read_resps_7_T_6)
node _io_rrd_read_resps_7_T_11 = or(_io_rrd_read_resps_7_T_10, _io_rrd_read_resps_7_T_7)
node _io_rrd_read_resps_7_T_12 = or(_io_rrd_read_resps_7_T_11, _io_rrd_read_resps_7_T_8)
node _io_rrd_read_resps_7_T_13 = or(_io_rrd_read_resps_7_T_12, _io_rrd_read_resps_7_T_9)
wire _io_rrd_read_resps_7_WIRE : UInt<64>
connect _io_rrd_read_resps_7_WIRE, _io_rrd_read_resps_7_T_13
connect io.rrd_read_resps[7], _io_rrd_read_resps_7_WIRE | module PartiallyPortedRF_2( // @[regfile.scala:128:7]
input clock, // @[regfile.scala:128:7]
input reset, // @[regfile.scala:128:7]
input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_2_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_2_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_3_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_3_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_4_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_4_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_4_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_5_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_5_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_5_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_6_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_6_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_6_bits, // @[regfile.scala:31:14]
output io_arb_read_reqs_7_ready, // @[regfile.scala:31:14]
input io_arb_read_reqs_7_valid, // @[regfile.scala:31:14]
input [5:0] io_arb_read_reqs_7_bits, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_0, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_1, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_2, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_3, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_4, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_5, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_6, // @[regfile.scala:31:14]
output [63:0] io_rrd_read_resps_7, // @[regfile.scala:31:14]
input io_write_ports_0_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_0_bits_data, // @[regfile.scala:31:14]
input io_write_ports_1_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_1_bits_data, // @[regfile.scala:31:14]
input io_write_ports_2_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_2_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_2_bits_data, // @[regfile.scala:31:14]
input io_write_ports_3_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_3_bits_addr, // @[regfile.scala:31:14]
input [63:0] io_write_ports_3_bits_data // @[regfile.scala:31:14]
);
wire [63:0] _rf_io_rrd_read_resps_0; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_1; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_2; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_3; // @[regfile.scala:138:18]
wire [63:0] _rf_io_rrd_read_resps_4; // @[regfile.scala:138:18]
wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_2_valid_0 = io_arb_read_reqs_2_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_2_bits_0 = io_arb_read_reqs_2_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_3_valid_0 = io_arb_read_reqs_3_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_3_bits_0 = io_arb_read_reqs_3_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_4_valid_0 = io_arb_read_reqs_4_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_4_bits_0 = io_arb_read_reqs_4_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_5_valid_0 = io_arb_read_reqs_5_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_5_bits_0 = io_arb_read_reqs_5_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_6_valid_0 = io_arb_read_reqs_6_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_6_bits_0 = io_arb_read_reqs_6_bits; // @[regfile.scala:128:7]
wire io_arb_read_reqs_7_valid_0 = io_arb_read_reqs_7_valid; // @[regfile.scala:128:7]
wire [5:0] io_arb_read_reqs_7_bits_0 = io_arb_read_reqs_7_bits; // @[regfile.scala:128:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:128:7]
wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:128:7]
wire io_write_ports_2_valid_0 = io_write_ports_2_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_2_bits_addr_0 = io_write_ports_2_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_2_bits_data_0 = io_write_ports_2_bits_data; // @[regfile.scala:128:7]
wire io_write_ports_3_valid_0 = io_write_ports_3_valid; // @[regfile.scala:128:7]
wire [6:0] io_write_ports_3_bits_addr_0 = io_write_ports_3_bits_addr; // @[regfile.scala:128:7]
wire [63:0] io_write_ports_3_bits_data_0 = io_write_ports_3_bits_data; // @[regfile.scala:128:7]
wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:128:7]
wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:128:7]
wire io_arb_read_reqs_2_ready = 1'h1; // @[regfile.scala:128:7]
wire io_arb_read_reqs_3_ready = 1'h1; // @[regfile.scala:128:7]
wire _io_arb_read_reqs_0_ready_T = 1'h1; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_1_ready_T = 1'h1; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_2_ready_T_2 = 1'h1; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_3_ready_T_4 = 1'h1; // @[regfile.scala:167:82]
wire [7:0] _data_sels_0_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_1_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_2_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_3_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_4_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_5_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_6_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [7:0] _data_sels_7_T_4 = 8'h10; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_0_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_1_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_2_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_3_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_4_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_5_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_6_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_7_T_3 = 4'h8; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_0_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_1_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_2_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_3_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_4_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_5_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_6_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [3:0] _data_sels_7_T_2 = 4'h4; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_0_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_1_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_2_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_3_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_4_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_5_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_6_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_7_T_1 = 2'h2; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_0_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_1_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_2_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_3_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_4_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_5_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_6_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _data_sels_7_T = 2'h1; // @[OneHot.scala:58:35]
wire issue_read = io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :155:32]
wire use_port = io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :156:30]
wire _io_arb_read_reqs_4_ready_T_6; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_5_ready_T_8; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_6_ready_T_10; // @[regfile.scala:167:82]
wire _io_arb_read_reqs_7_ready_T_12; // @[regfile.scala:167:82]
wire [63:0] _io_rrd_read_resps_0_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_1_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_2_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_3_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_4_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_5_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_6_WIRE; // @[Mux.scala:30:73]
wire [63:0] _io_rrd_read_resps_7_WIRE; // @[Mux.scala:30:73]
wire io_arb_read_reqs_4_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_5_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_6_ready_0; // @[regfile.scala:128:7]
wire io_arb_read_reqs_7_ready_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_0_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_1_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_2_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_3_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_4_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_5_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_6_0; // @[regfile.scala:128:7]
wire [63:0] io_rrd_read_resps_7_0; // @[regfile.scala:128:7]
wire [4:0] data_sels_0; // @[regfile.scala:149:25]
wire [4:0] data_sels_1; // @[regfile.scala:149:25]
wire [4:0] data_sels_2; // @[regfile.scala:149:25]
wire [4:0] data_sels_3; // @[regfile.scala:149:25]
wire [4:0] data_sels_4; // @[regfile.scala:149:25]
wire [4:0] data_sels_5; // @[regfile.scala:149:25]
wire [4:0] data_sels_6; // @[regfile.scala:149:25]
wire [4:0] data_sels_7; // @[regfile.scala:149:25]
wire issue_read_1; // @[regfile.scala:155:32]
wire use_port_1; // @[regfile.scala:156:30]
wire _T_61 = ~issue_read & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,45}]
assign issue_read_1 = _T_61; // @[regfile.scala:155:32, :157:45]
assign use_port_1 = _T_61; // @[regfile.scala:156:30, :157:45]
wire _T_67 = issue_read_1 | issue_read; // @[regfile.scala:155:32, :165:32]
wire issue_read_2; // @[regfile.scala:155:32]
wire use_port_2; // @[regfile.scala:156:30]
wire _T_71 = ~_T_67 & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :157:{13,45}, :165:32]
assign issue_read_2 = _T_71; // @[regfile.scala:155:32, :157:45]
assign use_port_2 = _T_71; // @[regfile.scala:156:30, :157:45]
wire _T_77 = issue_read_2 | _T_67; // @[regfile.scala:155:32, :165:32]
wire issue_read_3; // @[regfile.scala:155:32]
wire use_port_3; // @[regfile.scala:156:30]
wire _T_81 = ~_T_77 & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :157:{13,45}, :165:32]
assign issue_read_3 = _T_81; // @[regfile.scala:155:32, :157:45]
assign use_port_3 = _T_81; // @[regfile.scala:156:30, :157:45]
wire _T_87 = issue_read_3 | _T_77; // @[regfile.scala:155:32, :165:32]
wire issue_read_4; // @[regfile.scala:155:32]
wire use_port_4; // @[regfile.scala:156:30]
wire _T_91 = ~_T_87 & io_arb_read_reqs_0_valid_0; // @[regfile.scala:128:7, :157:{13,45}, :165:32]
assign issue_read_4 = _T_91; // @[regfile.scala:155:32, :157:45]
assign use_port_4 = _T_91; // @[regfile.scala:156:30, :157:45]
assign data_sels_0 = _T_91 ? 5'h10 : _T_81 ? 5'h8 : _T_71 ? 5'h4 : _T_61 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{45,75}, :160:22]
wire issue_read_5; // @[regfile.scala:155:32]
wire use_port_5; // @[regfile.scala:156:30]
wire _T_108 = ~use_port & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{29,45}]
assign issue_read_5 = _T_108; // @[regfile.scala:155:32, :157:45]
assign use_port_5 = _T_108; // @[regfile.scala:156:30, :157:45]
wire _T_109 = use_port_5 | use_port; // @[regfile.scala:156:30, :163:33]
wire issue_read_6; // @[regfile.scala:155:32]
wire use_port_6; // @[regfile.scala:156:30]
wire _T_118 = ~issue_read_5 & ~use_port_1 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :155:32, :156:30, :157:{13,26,29,45}]
assign issue_read_6 = _T_118; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_6 = _T_118; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_119 = use_port_6 | use_port_1; // @[regfile.scala:156:30, :163:33]
wire _T_124 = issue_read_6 | issue_read_5; // @[regfile.scala:155:32, :165:32]
wire issue_read_7; // @[regfile.scala:155:32]
wire use_port_7; // @[regfile.scala:156:30]
wire _T_128 = ~_T_124 & ~use_port_2 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{13,26,29,45}, :165:32]
assign issue_read_7 = _T_128; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_7 = _T_128; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_129 = use_port_7 | use_port_2; // @[regfile.scala:156:30, :163:33]
wire _T_134 = issue_read_7 | _T_124; // @[regfile.scala:155:32, :165:32]
wire issue_read_8; // @[regfile.scala:155:32]
wire use_port_8; // @[regfile.scala:156:30]
wire _T_138 = ~_T_134 & ~use_port_3 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{13,26,29,45}, :165:32]
assign issue_read_8 = _T_138; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_8 = _T_138; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_139 = use_port_8 | use_port_3; // @[regfile.scala:156:30, :163:33]
wire _T_144 = issue_read_8 | _T_134; // @[regfile.scala:155:32, :165:32]
wire issue_read_9; // @[regfile.scala:155:32]
wire use_port_9; // @[regfile.scala:156:30]
wire _T_148 = ~_T_144 & ~use_port_4 & io_arb_read_reqs_1_valid_0; // @[regfile.scala:128:7, :156:30, :157:{13,26,29,45}, :165:32]
assign issue_read_9 = _T_148; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_9 = _T_148; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_1 = _T_148 ? 5'h10 : _T_138 ? 5'h8 : _T_128 ? 5'h4 : _T_118 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_149 = use_port_9 | use_port_4; // @[regfile.scala:156:30, :163:33]
wire issue_read_10; // @[regfile.scala:155:32]
wire use_port_10; // @[regfile.scala:156:30]
wire _T_165 = ~_T_109 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_10 = _T_165; // @[regfile.scala:155:32, :157:45]
assign use_port_10 = _T_165; // @[regfile.scala:156:30, :157:45]
wire _T_166 = use_port_10 | _T_109; // @[regfile.scala:156:30, :163:33]
wire issue_read_11; // @[regfile.scala:155:32]
wire use_port_11; // @[regfile.scala:156:30]
wire _T_175 = ~issue_read_10 & ~_T_119 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_11 = _T_175; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_11 = _T_175; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_176 = use_port_11 | _T_119; // @[regfile.scala:156:30, :163:33]
wire _T_181 = issue_read_11 | issue_read_10; // @[regfile.scala:155:32, :165:32]
wire issue_read_12; // @[regfile.scala:155:32]
wire use_port_12; // @[regfile.scala:156:30]
wire _T_185 = ~_T_181 & ~_T_129 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_12 = _T_185; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_12 = _T_185; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_186 = use_port_12 | _T_129; // @[regfile.scala:156:30, :163:33]
wire _T_191 = issue_read_12 | _T_181; // @[regfile.scala:155:32, :165:32]
wire issue_read_13; // @[regfile.scala:155:32]
wire use_port_13; // @[regfile.scala:156:30]
wire _T_195 = ~_T_191 & ~_T_139 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_13 = _T_195; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_13 = _T_195; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_196 = use_port_13 | _T_139; // @[regfile.scala:156:30, :163:33]
wire _T_201 = issue_read_13 | _T_191; // @[regfile.scala:155:32, :165:32]
wire issue_read_14; // @[regfile.scala:155:32]
wire use_port_14; // @[regfile.scala:156:30]
wire _T_205 = ~_T_201 & ~_T_149 & io_arb_read_reqs_2_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_14 = _T_205; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_14 = _T_205; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_2 = _T_205 ? 5'h10 : _T_195 ? 5'h8 : _T_185 ? 5'h4 : _T_175 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_206 = use_port_14 | _T_149; // @[regfile.scala:156:30, :163:33]
wire [1:0] _GEN = {1'h0, io_arb_read_reqs_1_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_0 = {1'h0, io_arb_read_reqs_0_valid_0} + _GEN; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_2_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_2_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_4_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_4_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_5_ready_T = _GEN_0; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_2_ready_T_1 = _io_arb_read_reqs_2_ready_T; // @[regfile.scala:167:42]
wire issue_read_15; // @[regfile.scala:155:32]
wire use_port_15; // @[regfile.scala:156:30]
wire _T_222 = ~_T_166 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_15 = _T_222; // @[regfile.scala:155:32, :157:45]
assign use_port_15 = _T_222; // @[regfile.scala:156:30, :157:45]
wire _T_223 = use_port_15 | _T_166; // @[regfile.scala:156:30, :163:33]
wire issue_read_16; // @[regfile.scala:155:32]
wire use_port_16; // @[regfile.scala:156:30]
wire _T_232 = ~issue_read_15 & ~_T_176 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_16 = _T_232; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_16 = _T_232; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_233 = use_port_16 | _T_176; // @[regfile.scala:156:30, :163:33]
wire _T_238 = issue_read_16 | issue_read_15; // @[regfile.scala:155:32, :165:32]
wire issue_read_17; // @[regfile.scala:155:32]
wire use_port_17; // @[regfile.scala:156:30]
wire _T_242 = ~_T_238 & ~_T_186 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_17 = _T_242; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_17 = _T_242; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_243 = use_port_17 | _T_186; // @[regfile.scala:156:30, :163:33]
wire _T_248 = issue_read_17 | _T_238; // @[regfile.scala:155:32, :165:32]
wire issue_read_18; // @[regfile.scala:155:32]
wire use_port_18; // @[regfile.scala:156:30]
wire _T_252 = ~_T_248 & ~_T_196 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_18 = _T_252; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_18 = _T_252; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_253 = use_port_18 | _T_196; // @[regfile.scala:156:30, :163:33]
wire _T_258 = issue_read_18 | _T_248; // @[regfile.scala:155:32, :165:32]
wire issue_read_19; // @[regfile.scala:155:32]
wire use_port_19; // @[regfile.scala:156:30]
wire _T_262 = ~_T_258 & ~_T_206 & io_arb_read_reqs_3_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_19 = _T_262; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_19 = _T_262; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_3 = _T_262 ? 5'h10 : _T_252 ? 5'h8 : _T_242 ? 5'h4 : _T_232 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_263 = use_port_19 | _T_206; // @[regfile.scala:156:30, :163:33]
wire [1:0] _GEN_1 = {1'h0, io_arb_read_reqs_2_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_2 = _GEN + _GEN_1; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_3_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_3_ready_T = _GEN_2; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_6_ready_T = _GEN_2; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_7_ready_T = _GEN_2; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_3_ready_T_1 = _io_arb_read_reqs_3_ready_T; // @[regfile.scala:167:42]
wire [2:0] _GEN_3 = {2'h0, io_arb_read_reqs_0_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [2:0] _io_arb_read_reqs_3_ready_T_2 = _GEN_3 + {1'h0, _io_arb_read_reqs_3_ready_T_1}; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_3_ready_T_3 = _io_arb_read_reqs_3_ready_T_2[1:0]; // @[regfile.scala:167:42]
wire issue_read_20; // @[regfile.scala:155:32]
wire use_port_20; // @[regfile.scala:156:30]
wire _T_279 = ~_T_223 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_20 = _T_279; // @[regfile.scala:155:32, :157:45]
assign use_port_20 = _T_279; // @[regfile.scala:156:30, :157:45]
wire _T_280 = use_port_20 | _T_223; // @[regfile.scala:156:30, :163:33]
wire issue_read_21; // @[regfile.scala:155:32]
wire use_port_21; // @[regfile.scala:156:30]
wire _T_289 = ~issue_read_20 & ~_T_233 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_21 = _T_289; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_21 = _T_289; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_290 = use_port_21 | _T_233; // @[regfile.scala:156:30, :163:33]
wire _T_295 = issue_read_21 | issue_read_20; // @[regfile.scala:155:32, :165:32]
wire issue_read_22; // @[regfile.scala:155:32]
wire use_port_22; // @[regfile.scala:156:30]
wire _T_299 = ~_T_295 & ~_T_243 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_22 = _T_299; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_22 = _T_299; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_300 = use_port_22 | _T_243; // @[regfile.scala:156:30, :163:33]
wire _T_305 = issue_read_22 | _T_295; // @[regfile.scala:155:32, :165:32]
wire issue_read_23; // @[regfile.scala:155:32]
wire use_port_23; // @[regfile.scala:156:30]
wire _T_309 = ~_T_305 & ~_T_253 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_23 = _T_309; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_23 = _T_309; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_310 = use_port_23 | _T_253; // @[regfile.scala:156:30, :163:33]
wire _T_315 = issue_read_23 | _T_305; // @[regfile.scala:155:32, :165:32]
wire issue_read_24; // @[regfile.scala:155:32]
wire use_port_24; // @[regfile.scala:156:30]
wire _T_319 = ~_T_315 & ~_T_263 & io_arb_read_reqs_4_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_24 = _T_319; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_24 = _T_319; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_4 = _T_319 ? 5'h10 : _T_309 ? 5'h8 : _T_299 ? 5'h4 : _T_289 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_320 = use_port_24 | _T_263; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_4_ready_T_1 = _io_arb_read_reqs_4_ready_T; // @[regfile.scala:167:42]
wire [1:0] _GEN_4 = {1'h0, io_arb_read_reqs_3_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_4_ready_T_2 = _GEN_1 + _GEN_4; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_4_ready_T_3 = _io_arb_read_reqs_4_ready_T_2; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_4_ready_T_4 = {1'h0, _io_arb_read_reqs_4_ready_T_1} + {1'h0, _io_arb_read_reqs_4_ready_T_3}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_4_ready_T_5 = _io_arb_read_reqs_4_ready_T_4; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_4_ready_T_6 = _io_arb_read_reqs_4_ready_T_5 < 3'h5; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_4_ready_0 = _io_arb_read_reqs_4_ready_T_6; // @[regfile.scala:128:7, :167:82]
wire issue_read_25; // @[regfile.scala:155:32]
wire use_port_25; // @[regfile.scala:156:30]
wire _T_336 = ~_T_280 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_25 = _T_336; // @[regfile.scala:155:32, :157:45]
assign use_port_25 = _T_336; // @[regfile.scala:156:30, :157:45]
wire _T_337 = use_port_25 | _T_280; // @[regfile.scala:156:30, :163:33]
wire issue_read_26; // @[regfile.scala:155:32]
wire use_port_26; // @[regfile.scala:156:30]
wire _T_346 = ~issue_read_25 & ~_T_290 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_26 = _T_346; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_26 = _T_346; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_347 = use_port_26 | _T_290; // @[regfile.scala:156:30, :163:33]
wire _T_352 = issue_read_26 | issue_read_25; // @[regfile.scala:155:32, :165:32]
wire issue_read_27; // @[regfile.scala:155:32]
wire use_port_27; // @[regfile.scala:156:30]
wire _T_356 = ~_T_352 & ~_T_300 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_27 = _T_356; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_27 = _T_356; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_357 = use_port_27 | _T_300; // @[regfile.scala:156:30, :163:33]
wire _T_362 = issue_read_27 | _T_352; // @[regfile.scala:155:32, :165:32]
wire issue_read_28; // @[regfile.scala:155:32]
wire use_port_28; // @[regfile.scala:156:30]
wire _T_366 = ~_T_362 & ~_T_310 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_28 = _T_366; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_28 = _T_366; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_367 = use_port_28 | _T_310; // @[regfile.scala:156:30, :163:33]
wire _T_372 = issue_read_28 | _T_362; // @[regfile.scala:155:32, :165:32]
wire issue_read_29; // @[regfile.scala:155:32]
wire use_port_29; // @[regfile.scala:156:30]
wire _T_376 = ~_T_372 & ~_T_320 & io_arb_read_reqs_5_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_29 = _T_376; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_29 = _T_376; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_5 = _T_376 ? 5'h10 : _T_366 ? 5'h8 : _T_356 ? 5'h4 : _T_346 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_377 = use_port_29 | _T_320; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_5_ready_T_1 = _io_arb_read_reqs_5_ready_T; // @[regfile.scala:167:42]
wire [1:0] _GEN_5 = {1'h0, io_arb_read_reqs_4_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _GEN_6 = _GEN_4 + _GEN_5; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T_2; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_5_ready_T_2 = _GEN_6; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_4; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_7_ready_T_4 = _GEN_6; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T_3 = _io_arb_read_reqs_5_ready_T_2; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_5_ready_T_4 = {2'h0, io_arb_read_reqs_2_valid_0} + {1'h0, _io_arb_read_reqs_5_ready_T_3}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_5_ready_T_5 = _io_arb_read_reqs_5_ready_T_4[1:0]; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_5_ready_T_6 = {1'h0, _io_arb_read_reqs_5_ready_T_1} + {1'h0, _io_arb_read_reqs_5_ready_T_5}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_5_ready_T_7 = _io_arb_read_reqs_5_ready_T_6; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_5_ready_T_8 = _io_arb_read_reqs_5_ready_T_7 < 3'h5; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_5_ready_0 = _io_arb_read_reqs_5_ready_T_8; // @[regfile.scala:128:7, :167:82]
wire issue_read_30; // @[regfile.scala:155:32]
wire use_port_30; // @[regfile.scala:156:30]
wire _T_393 = ~_T_337 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_30 = _T_393; // @[regfile.scala:155:32, :157:45]
assign use_port_30 = _T_393; // @[regfile.scala:156:30, :157:45]
wire _T_394 = use_port_30 | _T_337; // @[regfile.scala:156:30, :163:33]
wire issue_read_31; // @[regfile.scala:155:32]
wire use_port_31; // @[regfile.scala:156:30]
wire _T_403 = ~issue_read_30 & ~_T_347 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_31 = _T_403; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_31 = _T_403; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_404 = use_port_31 | _T_347; // @[regfile.scala:156:30, :163:33]
wire _T_409 = issue_read_31 | issue_read_30; // @[regfile.scala:155:32, :165:32]
wire issue_read_32; // @[regfile.scala:155:32]
wire use_port_32; // @[regfile.scala:156:30]
wire _T_413 = ~_T_409 & ~_T_357 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_32 = _T_413; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_32 = _T_413; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_414 = use_port_32 | _T_357; // @[regfile.scala:156:30, :163:33]
wire _T_419 = issue_read_32 | _T_409; // @[regfile.scala:155:32, :165:32]
wire issue_read_33; // @[regfile.scala:155:32]
wire use_port_33; // @[regfile.scala:156:30]
wire _T_423 = ~_T_419 & ~_T_367 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_33 = _T_423; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_33 = _T_423; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_424 = use_port_33 | _T_367; // @[regfile.scala:156:30, :163:33]
wire _T_429 = issue_read_33 | _T_419; // @[regfile.scala:155:32, :165:32]
wire issue_read_34; // @[regfile.scala:155:32]
wire use_port_34; // @[regfile.scala:156:30]
wire _T_433 = ~_T_429 & ~_T_377 & io_arb_read_reqs_6_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_34 = _T_433; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_34 = _T_433; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_6 = _T_433 ? 5'h10 : _T_423 ? 5'h8 : _T_413 ? 5'h4 : _T_403 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire _T_434 = use_port_34 | _T_377; // @[regfile.scala:156:30, :163:33]
wire [1:0] _io_arb_read_reqs_6_ready_T_1 = _io_arb_read_reqs_6_ready_T; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_2 = _GEN_3 + {1'h0, _io_arb_read_reqs_6_ready_T_1}; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_3 = _io_arb_read_reqs_6_ready_T_2[1:0]; // @[regfile.scala:167:42]
wire [1:0] _GEN_7 = {1'h0, io_arb_read_reqs_5_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_4 = _GEN_5 + _GEN_7; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_5 = _io_arb_read_reqs_6_ready_T_4; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_6 = {2'h0, io_arb_read_reqs_3_valid_0} + {1'h0, _io_arb_read_reqs_6_ready_T_5}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_6_ready_T_7 = _io_arb_read_reqs_6_ready_T_6[1:0]; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_8 = {1'h0, _io_arb_read_reqs_6_ready_T_3} + {1'h0, _io_arb_read_reqs_6_ready_T_7}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_6_ready_T_9 = _io_arb_read_reqs_6_ready_T_8; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_6_ready_T_10 = _io_arb_read_reqs_6_ready_T_9 < 3'h5; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_6_ready_0 = _io_arb_read_reqs_6_ready_T_10; // @[regfile.scala:128:7, :167:82]
wire issue_read_35; // @[regfile.scala:155:32]
wire use_port_35; // @[regfile.scala:156:30]
wire _T_450 = ~_T_394 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{29,45}, :163:33]
assign issue_read_35 = _T_450; // @[regfile.scala:155:32, :157:45]
assign use_port_35 = _T_450; // @[regfile.scala:156:30, :157:45]
wire issue_read_36; // @[regfile.scala:155:32]
wire use_port_36; // @[regfile.scala:156:30]
wire _T_460 = ~issue_read_35 & ~_T_404 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :155:32, :157:{13,26,29,45}, :163:33]
assign issue_read_36 = _T_460; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_36 = _T_460; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_466 = issue_read_36 | issue_read_35; // @[regfile.scala:155:32, :165:32]
wire issue_read_37; // @[regfile.scala:155:32]
wire use_port_37; // @[regfile.scala:156:30]
wire _T_470 = ~_T_466 & ~_T_414 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_37 = _T_470; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_37 = _T_470; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_476 = issue_read_37 | _T_466; // @[regfile.scala:155:32, :165:32]
wire issue_read_38; // @[regfile.scala:155:32]
wire use_port_38; // @[regfile.scala:156:30]
wire _T_480 = ~_T_476 & ~_T_424 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_38 = _T_480; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_38 = _T_480; // @[regfile.scala:156:30, :157:{26,45}]
wire _T_486 = issue_read_38 | _T_476; // @[regfile.scala:155:32, :165:32]
wire issue_read_39; // @[regfile.scala:155:32]
wire use_port_39; // @[regfile.scala:156:30]
wire _T_490 = ~_T_486 & ~_T_434 & io_arb_read_reqs_7_valid_0; // @[regfile.scala:128:7, :157:{13,26,29,45}, :163:33, :165:32]
assign issue_read_39 = _T_490; // @[regfile.scala:155:32, :157:{26,45}]
assign use_port_39 = _T_490; // @[regfile.scala:156:30, :157:{26,45}]
assign data_sels_7 = _T_490 ? 5'h10 : _T_480 ? 5'h8 : _T_470 ? 5'h4 : _T_460 ? 5'h2 : 5'h1; // @[regfile.scala:149:25, :157:{26,45,75}, :160:22]
wire [1:0] _io_arb_read_reqs_7_ready_T_1 = _io_arb_read_reqs_7_ready_T; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_2 = _GEN_3 + {1'h0, _io_arb_read_reqs_7_ready_T_1}; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_3 = _io_arb_read_reqs_7_ready_T_2[1:0]; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_5 = _io_arb_read_reqs_7_ready_T_4; // @[regfile.scala:167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_6 = _GEN_7 + {1'h0, io_arb_read_reqs_6_valid_0}; // @[regfile.scala:128:7, :167:42]
wire [1:0] _io_arb_read_reqs_7_ready_T_7 = _io_arb_read_reqs_7_ready_T_6; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_8 = {1'h0, _io_arb_read_reqs_7_ready_T_5} + {1'h0, _io_arb_read_reqs_7_ready_T_7}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_9 = _io_arb_read_reqs_7_ready_T_8; // @[regfile.scala:167:42]
wire [3:0] _io_arb_read_reqs_7_ready_T_10 = {2'h0, _io_arb_read_reqs_7_ready_T_3} + {1'h0, _io_arb_read_reqs_7_ready_T_9}; // @[regfile.scala:167:42]
wire [2:0] _io_arb_read_reqs_7_ready_T_11 = _io_arb_read_reqs_7_ready_T_10[2:0]; // @[regfile.scala:167:42]
assign _io_arb_read_reqs_7_ready_T_12 = _io_arb_read_reqs_7_ready_T_11 < 3'h5; // @[regfile.scala:167:{42,82}]
assign io_arb_read_reqs_7_ready_0 = _io_arb_read_reqs_7_ready_T_12; // @[regfile.scala:128:7, :167:82] |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a21d64s10k1z3u :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a21d64s10k1z3u( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [20:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [20:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [9:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [20:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [9:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [20:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [9:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [20:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [9:0] saved_source; // @[Repeater.scala:21:18]
reg [20:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<7>(0h40))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<7>(0h40))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<7>(0h40))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [6:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 7'h40; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 7'h40; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_430 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_430( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_40 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_48
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_40( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_48 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_3 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_6
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_3
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<4>(0hd), io.in.bits.egress_id)
node _T_1 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _T_4 = eq(UInt<5>(0h13), io.in.bits.egress_id)
node _T_5 = or(_T, _T_1)
node _T_6 = or(_T_5, _T_2)
node _T_7 = or(_T_6, _T_3)
node _T_8 = or(_T_7, _T_4)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = and(io.in.valid, _T_9)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_11, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h1)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hd), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h13), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h4), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h8), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h7), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7)
node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8)
node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hd), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h13), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h1))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6]
connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7]
connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8]
connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
node _T_15 = and(io.in.ready, io.in.valid)
node _T_16 = and(_T_15, io.in.bits.head)
node _T_17 = and(_T_16, at_dest)
when _T_17 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
node _T_18 = eq(UInt<3>(0h4), io.in.bits.egress_id)
when _T_18 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_19 = eq(UInt<3>(0h5), io.in.bits.egress_id)
when _T_19 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_21 = and(route_q.io.enq.valid, _T_20)
node _T_22 = eq(_T_21, UInt<1>(0h0))
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
node _T_25 = eq(_T_22, UInt<1>(0h0))
when _T_25 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_22, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_7
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_3
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_27 = and(vcalloc_q.io.enq.valid, _T_26)
node _T_28 = eq(_T_27, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node c_lo = cat(c_lo_hi, c_lo_lo)
node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8])
node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node c_hi = cat(c_hi_hi, c_hi_lo)
node _c_T = cat(c_hi, c_lo)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node _c_T_1 = cat(c_hi_1, _c_T)
node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2])
node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1)
node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5])
node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8])
node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7])
node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1)
node _c_T_2 = cat(c_hi_2, c_lo_1)
node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _c_T_3 = cat(c_hi_3, _c_T_2)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8])
node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9])
node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo)
node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8])
node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo)
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2)
node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0)
node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3)
node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3)
node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1)
node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7)
node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8)
node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12)
node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_14, _out_bundle_bits_out_virt_channel_T_13)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_15
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_3( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'hA; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h13; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_id_T_3, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0) | {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, 2'h0} | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_4}}}; // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'h1; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'h1; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE : UInt<1>[3]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
connect _source_ok_WIRE[2], _source_ok_T_2
node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_23 = cvt(_T_22)
node _T_24 = and(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = asSInt(_T_24)
node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = or(_T_21, _T_26)
node _T_28 = and(_T_11, _T_19)
node _T_29 = and(_T_28, _T_27)
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_29, UInt<1>(0h1), "") : assert_1
node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_33 :
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_40 = or(_T_37, _T_38)
node _T_41 = or(_T_40, _T_39)
node _T_42 = and(_T_36, _T_41)
node _T_43 = or(UInt<1>(0h0), _T_42)
node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<13>(0h1000)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_56 = cvt(_T_55)
node _T_57 = and(_T_56, asSInt(UInt<17>(0h10000)))
node _T_58 = asSInt(_T_57)
node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0)))
node _T_60 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_61 = cvt(_T_60)
node _T_62 = and(_T_61, asSInt(UInt<18>(0h2f000)))
node _T_63 = asSInt(_T_62)
node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0)))
node _T_65 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<13>(0h1000)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<27>(0h4000000)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = or(_T_49, _T_54)
node _T_86 = or(_T_85, _T_59)
node _T_87 = or(_T_86, _T_64)
node _T_88 = or(_T_87, _T_69)
node _T_89 = or(_T_88, _T_74)
node _T_90 = or(_T_89, _T_79)
node _T_91 = or(_T_90, _T_84)
node _T_92 = and(_T_44, _T_91)
node _T_93 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<29>(0h10000000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = and(_T_94, _T_105)
node _T_107 = or(UInt<1>(0h0), _T_92)
node _T_108 = or(_T_107, _T_106)
node _T_109 = and(_T_43, _T_108)
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_109, UInt<1>(0h1), "") : assert_2
node _T_113 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_114 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_115 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE : UInt<1>[3]
connect _WIRE[0], _T_113
connect _WIRE[1], _T_114
connect _WIRE[2], _T_115
node _T_116 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_117 = mux(_WIRE[0], _T_116, UInt<1>(0h0))
node _T_118 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_119 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_120 = or(_T_117, _T_118)
node _T_121 = or(_T_120, _T_119)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_121
node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_124 = and(_T_122, _T_123)
node _T_125 = or(UInt<1>(0h0), _T_124)
node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = or(_T_130, _T_135)
node _T_177 = or(_T_176, _T_140)
node _T_178 = or(_T_177, _T_145)
node _T_179 = or(_T_178, _T_150)
node _T_180 = or(_T_179, _T_155)
node _T_181 = or(_T_180, _T_160)
node _T_182 = or(_T_181, _T_165)
node _T_183 = or(_T_182, _T_170)
node _T_184 = or(_T_183, _T_175)
node _T_185 = and(_T_125, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(_WIRE_1, _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_187, UInt<1>(0h1), "") : assert_3
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(source_ok, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_194 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_194, UInt<1>(0h1), "") : assert_5
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(is_aligned, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_201, UInt<1>(0h1), "") : assert_7
node _T_205 = not(io.in.a.bits.mask)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_206, UInt<1>(0h1), "") : assert_8
node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_210, UInt<1>(0h1), "") : assert_9
node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_214 :
node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_219 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_220 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_221 = or(_T_218, _T_219)
node _T_222 = or(_T_221, _T_220)
node _T_223 = and(_T_217, _T_222)
node _T_224 = or(UInt<1>(0h0), _T_223)
node _T_225 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<14>(0h2000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<17>(0h10000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<18>(0h2f000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_252 = cvt(_T_251)
node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000)))
node _T_254 = asSInt(_T_253)
node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<27>(0h4000000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_230, _T_235)
node _T_267 = or(_T_266, _T_240)
node _T_268 = or(_T_267, _T_245)
node _T_269 = or(_T_268, _T_250)
node _T_270 = or(_T_269, _T_255)
node _T_271 = or(_T_270, _T_260)
node _T_272 = or(_T_271, _T_265)
node _T_273 = and(_T_225, _T_272)
node _T_274 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_275 = or(UInt<1>(0h0), _T_274)
node _T_276 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_277 = cvt(_T_276)
node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000)))
node _T_279 = asSInt(_T_278)
node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0)))
node _T_281 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<29>(0h10000000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = or(_T_280, _T_285)
node _T_287 = and(_T_275, _T_286)
node _T_288 = or(UInt<1>(0h0), _T_273)
node _T_289 = or(_T_288, _T_287)
node _T_290 = and(_T_224, _T_289)
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_290, UInt<1>(0h1), "") : assert_10
node _T_294 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_295 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_296 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE_2 : UInt<1>[3]
connect _WIRE_2[0], _T_294
connect _WIRE_2[1], _T_295
connect _WIRE_2[2], _T_296
node _T_297 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_298 = mux(_WIRE_2[0], _T_297, UInt<1>(0h0))
node _T_299 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_300 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = or(_T_298, _T_299)
node _T_302 = or(_T_301, _T_300)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_302
node _T_303 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_304 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_305 = and(_T_303, _T_304)
node _T_306 = or(UInt<1>(0h0), _T_305)
node _T_307 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<14>(0h2000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<17>(0h10000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<18>(0h2f000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_328 = cvt(_T_327)
node _T_329 = and(_T_328, asSInt(UInt<17>(0h10000)))
node _T_330 = asSInt(_T_329)
node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0)))
node _T_332 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<17>(0h10000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<27>(0h4000000)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<13>(0h1000)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_353 = cvt(_T_352)
node _T_354 = and(_T_353, asSInt(UInt<29>(0h10000000)))
node _T_355 = asSInt(_T_354)
node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0)))
node _T_357 = or(_T_311, _T_316)
node _T_358 = or(_T_357, _T_321)
node _T_359 = or(_T_358, _T_326)
node _T_360 = or(_T_359, _T_331)
node _T_361 = or(_T_360, _T_336)
node _T_362 = or(_T_361, _T_341)
node _T_363 = or(_T_362, _T_346)
node _T_364 = or(_T_363, _T_351)
node _T_365 = or(_T_364, _T_356)
node _T_366 = and(_T_306, _T_365)
node _T_367 = or(UInt<1>(0h0), _T_366)
node _T_368 = and(_WIRE_3, _T_367)
node _T_369 = asUInt(reset)
node _T_370 = eq(_T_369, UInt<1>(0h0))
when _T_370 :
node _T_371 = eq(_T_368, UInt<1>(0h0))
when _T_371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_368, UInt<1>(0h1), "") : assert_11
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(source_ok, UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_375 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_375, UInt<1>(0h1), "") : assert_13
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(is_aligned, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_382 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_382, UInt<1>(0h1), "") : assert_15
node _T_386 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_386, UInt<1>(0h1), "") : assert_16
node _T_390 = not(io.in.a.bits.mask)
node _T_391 = eq(_T_390, UInt<1>(0h0))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_391, UInt<1>(0h1), "") : assert_17
node _T_395 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_T_395, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_395, UInt<1>(0h1), "") : assert_18
node _T_399 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_399 :
node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_401 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_402 = and(_T_400, _T_401)
node _T_403 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_404 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_405 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_406 = or(_T_403, _T_404)
node _T_407 = or(_T_406, _T_405)
node _T_408 = and(_T_402, _T_407)
node _T_409 = or(UInt<1>(0h0), _T_408)
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_409, UInt<1>(0h1), "") : assert_19
node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_415 = and(_T_413, _T_414)
node _T_416 = or(UInt<1>(0h0), _T_415)
node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_418 = cvt(_T_417)
node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000)))
node _T_420 = asSInt(_T_419)
node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0)))
node _T_422 = and(_T_416, _T_421)
node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_425 = and(_T_423, _T_424)
node _T_426 = or(UInt<1>(0h0), _T_425)
node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_433 = cvt(_T_432)
node _T_434 = and(_T_433, asSInt(UInt<17>(0h10000)))
node _T_435 = asSInt(_T_434)
node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0)))
node _T_437 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_438 = cvt(_T_437)
node _T_439 = and(_T_438, asSInt(UInt<18>(0h2f000)))
node _T_440 = asSInt(_T_439)
node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0)))
node _T_442 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_443 = cvt(_T_442)
node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000)))
node _T_445 = asSInt(_T_444)
node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0)))
node _T_447 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_453 = cvt(_T_452)
node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000)))
node _T_455 = asSInt(_T_454)
node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0)))
node _T_457 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<27>(0h4000000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<29>(0h10000000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = or(_T_431, _T_436)
node _T_473 = or(_T_472, _T_441)
node _T_474 = or(_T_473, _T_446)
node _T_475 = or(_T_474, _T_451)
node _T_476 = or(_T_475, _T_456)
node _T_477 = or(_T_476, _T_461)
node _T_478 = or(_T_477, _T_466)
node _T_479 = or(_T_478, _T_471)
node _T_480 = and(_T_426, _T_479)
node _T_481 = or(UInt<1>(0h0), _T_422)
node _T_482 = or(_T_481, _T_480)
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_482, UInt<1>(0h1), "") : assert_20
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(source_ok, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(is_aligned, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_492 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_492, UInt<1>(0h1), "") : assert_23
node _T_496 = eq(io.in.a.bits.mask, mask)
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_496, UInt<1>(0h1), "") : assert_24
node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_500, UInt<1>(0h1), "") : assert_25
node _T_504 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_504 :
node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_509 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_510 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_511 = or(_T_508, _T_509)
node _T_512 = or(_T_511, _T_510)
node _T_513 = and(_T_507, _T_512)
node _T_514 = or(UInt<1>(0h0), _T_513)
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_517 = and(_T_515, _T_516)
node _T_518 = or(UInt<1>(0h0), _T_517)
node _T_519 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = and(_T_518, _T_523)
node _T_525 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_526 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_527 = and(_T_525, _T_526)
node _T_528 = or(UInt<1>(0h0), _T_527)
node _T_529 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<14>(0h2000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<18>(0h2f000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<13>(0h1000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<17>(0h10000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<27>(0h4000000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<29>(0h10000000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = or(_T_533, _T_538)
node _T_570 = or(_T_569, _T_543)
node _T_571 = or(_T_570, _T_548)
node _T_572 = or(_T_571, _T_553)
node _T_573 = or(_T_572, _T_558)
node _T_574 = or(_T_573, _T_563)
node _T_575 = or(_T_574, _T_568)
node _T_576 = and(_T_528, _T_575)
node _T_577 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_578 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_579 = cvt(_T_578)
node _T_580 = and(_T_579, asSInt(UInt<17>(0h10000)))
node _T_581 = asSInt(_T_580)
node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0)))
node _T_583 = and(_T_577, _T_582)
node _T_584 = or(UInt<1>(0h0), _T_524)
node _T_585 = or(_T_584, _T_576)
node _T_586 = or(_T_585, _T_583)
node _T_587 = and(_T_514, _T_586)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_587, UInt<1>(0h1), "") : assert_26
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(source_ok, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(is_aligned, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_597 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_597, UInt<1>(0h1), "") : assert_29
node _T_601 = eq(io.in.a.bits.mask, mask)
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_601, UInt<1>(0h1), "") : assert_30
node _T_605 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_605 :
node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_607 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_608 = and(_T_606, _T_607)
node _T_609 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_610 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_611 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_612 = or(_T_609, _T_610)
node _T_613 = or(_T_612, _T_611)
node _T_614 = and(_T_608, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_618 = and(_T_616, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_618)
node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = and(_T_619, _T_624)
node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_628 = and(_T_626, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_628)
node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_646 = cvt(_T_645)
node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000)))
node _T_648 = asSInt(_T_647)
node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0)))
node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_656 = cvt(_T_655)
node _T_657 = and(_T_656, asSInt(UInt<27>(0h4000000)))
node _T_658 = asSInt(_T_657)
node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0)))
node _T_660 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<29>(0h10000000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = or(_T_634, _T_639)
node _T_671 = or(_T_670, _T_644)
node _T_672 = or(_T_671, _T_649)
node _T_673 = or(_T_672, _T_654)
node _T_674 = or(_T_673, _T_659)
node _T_675 = or(_T_674, _T_664)
node _T_676 = or(_T_675, _T_669)
node _T_677 = and(_T_629, _T_676)
node _T_678 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_679 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_680 = cvt(_T_679)
node _T_681 = and(_T_680, asSInt(UInt<17>(0h10000)))
node _T_682 = asSInt(_T_681)
node _T_683 = eq(_T_682, asSInt(UInt<1>(0h0)))
node _T_684 = and(_T_678, _T_683)
node _T_685 = or(UInt<1>(0h0), _T_625)
node _T_686 = or(_T_685, _T_677)
node _T_687 = or(_T_686, _T_684)
node _T_688 = and(_T_615, _T_687)
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_688, UInt<1>(0h1), "") : assert_31
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(source_ok, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(is_aligned, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(_T_698, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_698, UInt<1>(0h1), "") : assert_34
node _T_702 = not(mask)
node _T_703 = and(io.in.a.bits.mask, _T_702)
node _T_704 = eq(_T_703, UInt<1>(0h0))
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_704, UInt<1>(0h1), "") : assert_35
node _T_708 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_708 :
node _T_709 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_710 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_711 = and(_T_709, _T_710)
node _T_712 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_713 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_714 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_715 = or(_T_712, _T_713)
node _T_716 = or(_T_715, _T_714)
node _T_717 = and(_T_711, _T_716)
node _T_718 = or(UInt<1>(0h0), _T_717)
node _T_719 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_720 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<14>(0h2000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_744 = cvt(_T_743)
node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000)))
node _T_746 = asSInt(_T_745)
node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0)))
node _T_748 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_749 = cvt(_T_748)
node _T_750 = and(_T_749, asSInt(UInt<17>(0h10000)))
node _T_751 = asSInt(_T_750)
node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0)))
node _T_753 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<27>(0h4000000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_759 = cvt(_T_758)
node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000)))
node _T_761 = asSInt(_T_760)
node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0)))
node _T_763 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_764 = cvt(_T_763)
node _T_765 = and(_T_764, asSInt(UInt<29>(0h10000000)))
node _T_766 = asSInt(_T_765)
node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0)))
node _T_768 = or(_T_727, _T_732)
node _T_769 = or(_T_768, _T_737)
node _T_770 = or(_T_769, _T_742)
node _T_771 = or(_T_770, _T_747)
node _T_772 = or(_T_771, _T_752)
node _T_773 = or(_T_772, _T_757)
node _T_774 = or(_T_773, _T_762)
node _T_775 = or(_T_774, _T_767)
node _T_776 = and(_T_722, _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<17>(0h10000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_776)
node _T_785 = or(_T_784, _T_783)
node _T_786 = and(_T_718, _T_785)
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_786, UInt<1>(0h1), "") : assert_36
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(source_ok, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(is_aligned, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_796 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_796, UInt<1>(0h1), "") : assert_39
node _T_800 = eq(io.in.a.bits.mask, mask)
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_800, UInt<1>(0h1), "") : assert_40
node _T_804 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_809 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_810 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_811 = or(_T_808, _T_809)
node _T_812 = or(_T_811, _T_810)
node _T_813 = and(_T_807, _T_812)
node _T_814 = or(UInt<1>(0h0), _T_813)
node _T_815 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_816 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_817 = and(_T_815, _T_816)
node _T_818 = or(UInt<1>(0h0), _T_817)
node _T_819 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<14>(0h2000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_825 = cvt(_T_824)
node _T_826 = and(_T_825, asSInt(UInt<13>(0h1000)))
node _T_827 = asSInt(_T_826)
node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0)))
node _T_829 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<18>(0h2f000)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<17>(0h10000)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<17>(0h10000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<27>(0h4000000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<13>(0h1000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<29>(0h10000000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = or(_T_823, _T_828)
node _T_865 = or(_T_864, _T_833)
node _T_866 = or(_T_865, _T_838)
node _T_867 = or(_T_866, _T_843)
node _T_868 = or(_T_867, _T_848)
node _T_869 = or(_T_868, _T_853)
node _T_870 = or(_T_869, _T_858)
node _T_871 = or(_T_870, _T_863)
node _T_872 = and(_T_818, _T_871)
node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = and(_T_873, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_872)
node _T_881 = or(_T_880, _T_879)
node _T_882 = and(_T_814, _T_881)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_882, UInt<1>(0h1), "") : assert_41
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(is_aligned, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_892, UInt<1>(0h1), "") : assert_44
node _T_896 = eq(io.in.a.bits.mask, mask)
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_896, UInt<1>(0h1), "") : assert_45
node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_900 :
node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_903 = and(_T_901, _T_902)
node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_907 = or(_T_904, _T_905)
node _T_908 = or(_T_907, _T_906)
node _T_909 = and(_T_903, _T_908)
node _T_910 = or(UInt<1>(0h0), _T_909)
node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_912 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_913 = and(_T_911, _T_912)
node _T_914 = or(UInt<1>(0h0), _T_913)
node _T_915 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<13>(0h1000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = and(_T_914, _T_919)
node _T_921 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_922 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_923 = cvt(_T_922)
node _T_924 = and(_T_923, asSInt(UInt<14>(0h2000)))
node _T_925 = asSInt(_T_924)
node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0)))
node _T_927 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_928 = cvt(_T_927)
node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000)))
node _T_930 = asSInt(_T_929)
node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0)))
node _T_932 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_933 = cvt(_T_932)
node _T_934 = and(_T_933, asSInt(UInt<18>(0h2f000)))
node _T_935 = asSInt(_T_934)
node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0)))
node _T_937 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<13>(0h1000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_948 = cvt(_T_947)
node _T_949 = and(_T_948, asSInt(UInt<27>(0h4000000)))
node _T_950 = asSInt(_T_949)
node _T_951 = eq(_T_950, asSInt(UInt<1>(0h0)))
node _T_952 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_953 = cvt(_T_952)
node _T_954 = and(_T_953, asSInt(UInt<13>(0h1000)))
node _T_955 = asSInt(_T_954)
node _T_956 = eq(_T_955, asSInt(UInt<1>(0h0)))
node _T_957 = or(_T_926, _T_931)
node _T_958 = or(_T_957, _T_936)
node _T_959 = or(_T_958, _T_941)
node _T_960 = or(_T_959, _T_946)
node _T_961 = or(_T_960, _T_951)
node _T_962 = or(_T_961, _T_956)
node _T_963 = and(_T_921, _T_962)
node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_965 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_966 = and(_T_964, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_969 = cvt(_T_968)
node _T_970 = and(_T_969, asSInt(UInt<17>(0h10000)))
node _T_971 = asSInt(_T_970)
node _T_972 = eq(_T_971, asSInt(UInt<1>(0h0)))
node _T_973 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_974 = cvt(_T_973)
node _T_975 = and(_T_974, asSInt(UInt<29>(0h10000000)))
node _T_976 = asSInt(_T_975)
node _T_977 = eq(_T_976, asSInt(UInt<1>(0h0)))
node _T_978 = or(_T_972, _T_977)
node _T_979 = and(_T_967, _T_978)
node _T_980 = or(UInt<1>(0h0), _T_920)
node _T_981 = or(_T_980, _T_963)
node _T_982 = or(_T_981, _T_979)
node _T_983 = and(_T_910, _T_982)
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_983, UInt<1>(0h1), "") : assert_46
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(source_ok, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(is_aligned, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_993 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_993, UInt<1>(0h1), "") : assert_49
node _T_997 = eq(io.in.a.bits.mask, mask)
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_997, UInt<1>(0h1), "") : assert_50
node _T_1001 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1005 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_52
node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1))
node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_1 : UInt<1>[3]
connect _source_ok_WIRE_1[0], _source_ok_T_4
connect _source_ok_WIRE_1[1], _source_ok_T_5
connect _source_ok_WIRE_1[2], _source_ok_T_6
node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1009 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1009 :
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(source_ok_1, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_54
node _T_1017 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_55
node _T_1021 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_56
node _T_1025 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_57
node _T_1029 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1029 :
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(source_ok_1, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(sink_ok, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1036 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_60
node _T_1040 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_61
node _T_1044 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_62
node _T_1048 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_63
node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1053 = or(UInt<1>(0h1), _T_1052)
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_64
node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1057 :
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(source_ok_1, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(sink_ok, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1064 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_67
node _T_1068 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_68
node _T_1072 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_69
node _T_1076 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1077 = or(_T_1076, io.in.d.bits.corrupt)
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_70
node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1082 = or(UInt<1>(0h1), _T_1081)
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_71
node _T_1086 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(source_ok_1, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1090 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_73
node _T_1094 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_74
node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1099 = or(UInt<1>(0h1), _T_1098)
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_75
node _T_1103 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1103 :
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(source_ok_1, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1107 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_77
node _T_1111 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1112 = or(_T_1111, io.in.d.bits.corrupt)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_78
node _T_1116 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1117 = or(UInt<1>(0h1), _T_1116)
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_79
node _T_1121 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1121 :
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(source_ok_1, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1125 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_81
node _T_1129 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_82
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(UInt<1>(0h1), _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1138 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_84
node _T_1142 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
node _T_1144 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1145 = cvt(_T_1144)
node _T_1146 = and(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = asSInt(_T_1146)
node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = or(_T_1143, _T_1148)
node _T_1150 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
node _T_1152 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<1>(0h0)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = or(_T_1151, _T_1156)
node _T_1158 = eq(io.in.b.bits.source, UInt<2>(0h2))
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
node _T_1160 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1161 = cvt(_T_1160)
node _T_1162 = and(_T_1161, asSInt(UInt<1>(0h0)))
node _T_1163 = asSInt(_T_1162)
node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0)))
node _T_1165 = or(_T_1159, _T_1164)
node _T_1166 = and(_T_1149, _T_1157)
node _T_1167 = and(_T_1166, _T_1165)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _legal_source_WIRE : UInt<1>[3]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
connect _legal_source_WIRE[2], _legal_source_T_2
node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0))
node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4)
node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5)
wire _legal_source_WIRE_1 : UInt<2>
connect _legal_source_WIRE_1, _legal_source_T_7
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1171 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1171 :
node _T_1172 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1173 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1174 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _WIRE_4 : UInt<1>[3]
connect _WIRE_4[0], _T_1172
connect _WIRE_4[1], _T_1173
connect _WIRE_4[2], _T_1174
node _T_1175 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1176 = mux(_WIRE_4[0], _T_1175, UInt<1>(0h0))
node _T_1177 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1178 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1179 = or(_T_1176, _T_1177)
node _T_1180 = or(_T_1179, _T_1178)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1180
node _T_1181 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1182 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1183 = and(_T_1181, _T_1182)
node _T_1184 = or(UInt<1>(0h0), _T_1183)
node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<14>(0h2000)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1191 = cvt(_T_1190)
node _T_1192 = and(_T_1191, asSInt(UInt<13>(0h1000)))
node _T_1193 = asSInt(_T_1192)
node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0)))
node _T_1195 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1196 = cvt(_T_1195)
node _T_1197 = and(_T_1196, asSInt(UInt<17>(0h10000)))
node _T_1198 = asSInt(_T_1197)
node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0)))
node _T_1200 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1201 = cvt(_T_1200)
node _T_1202 = and(_T_1201, asSInt(UInt<18>(0h2f000)))
node _T_1203 = asSInt(_T_1202)
node _T_1204 = eq(_T_1203, asSInt(UInt<1>(0h0)))
node _T_1205 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1206 = cvt(_T_1205)
node _T_1207 = and(_T_1206, asSInt(UInt<17>(0h10000)))
node _T_1208 = asSInt(_T_1207)
node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0)))
node _T_1210 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1211 = cvt(_T_1210)
node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000)))
node _T_1213 = asSInt(_T_1212)
node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1216 = cvt(_T_1215)
node _T_1217 = and(_T_1216, asSInt(UInt<17>(0h10000)))
node _T_1218 = asSInt(_T_1217)
node _T_1219 = eq(_T_1218, asSInt(UInt<1>(0h0)))
node _T_1220 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1221 = cvt(_T_1220)
node _T_1222 = and(_T_1221, asSInt(UInt<27>(0h4000000)))
node _T_1223 = asSInt(_T_1222)
node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0)))
node _T_1225 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1226 = cvt(_T_1225)
node _T_1227 = and(_T_1226, asSInt(UInt<13>(0h1000)))
node _T_1228 = asSInt(_T_1227)
node _T_1229 = eq(_T_1228, asSInt(UInt<1>(0h0)))
node _T_1230 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1231 = cvt(_T_1230)
node _T_1232 = and(_T_1231, asSInt(UInt<29>(0h10000000)))
node _T_1233 = asSInt(_T_1232)
node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0)))
node _T_1235 = or(_T_1189, _T_1194)
node _T_1236 = or(_T_1235, _T_1199)
node _T_1237 = or(_T_1236, _T_1204)
node _T_1238 = or(_T_1237, _T_1209)
node _T_1239 = or(_T_1238, _T_1214)
node _T_1240 = or(_T_1239, _T_1219)
node _T_1241 = or(_T_1240, _T_1224)
node _T_1242 = or(_T_1241, _T_1229)
node _T_1243 = or(_T_1242, _T_1234)
node _T_1244 = and(_T_1184, _T_1243)
node _T_1245 = or(UInt<1>(0h0), _T_1244)
node _T_1246 = and(_WIRE_5, _T_1245)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_86
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(address_ok, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(legal_source, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1259 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1260 = asUInt(reset)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
when _T_1261 :
node _T_1262 = eq(_T_1259, UInt<1>(0h0))
when _T_1262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1259, UInt<1>(0h1), "") : assert_90
node _T_1263 = eq(io.in.b.bits.mask, mask_1)
node _T_1264 = asUInt(reset)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
when _T_1265 :
node _T_1266 = eq(_T_1263, UInt<1>(0h0))
when _T_1266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1263, UInt<1>(0h1), "") : assert_91
node _T_1267 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1268 = asUInt(reset)
node _T_1269 = eq(_T_1268, UInt<1>(0h0))
when _T_1269 :
node _T_1270 = eq(_T_1267, UInt<1>(0h0))
when _T_1270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1267, UInt<1>(0h1), "") : assert_92
node _T_1271 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1271 :
node _T_1272 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1273 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = or(UInt<1>(0h0), _T_1274)
node _T_1276 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1277 = cvt(_T_1276)
node _T_1278 = and(_T_1277, asSInt(UInt<14>(0h2000)))
node _T_1279 = asSInt(_T_1278)
node _T_1280 = eq(_T_1279, asSInt(UInt<1>(0h0)))
node _T_1281 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1282 = cvt(_T_1281)
node _T_1283 = and(_T_1282, asSInt(UInt<13>(0h1000)))
node _T_1284 = asSInt(_T_1283)
node _T_1285 = eq(_T_1284, asSInt(UInt<1>(0h0)))
node _T_1286 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1287 = cvt(_T_1286)
node _T_1288 = and(_T_1287, asSInt(UInt<17>(0h10000)))
node _T_1289 = asSInt(_T_1288)
node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0)))
node _T_1291 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1292 = cvt(_T_1291)
node _T_1293 = and(_T_1292, asSInt(UInt<18>(0h2f000)))
node _T_1294 = asSInt(_T_1293)
node _T_1295 = eq(_T_1294, asSInt(UInt<1>(0h0)))
node _T_1296 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1297 = cvt(_T_1296)
node _T_1298 = and(_T_1297, asSInt(UInt<17>(0h10000)))
node _T_1299 = asSInt(_T_1298)
node _T_1300 = eq(_T_1299, asSInt(UInt<1>(0h0)))
node _T_1301 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1302 = cvt(_T_1301)
node _T_1303 = and(_T_1302, asSInt(UInt<13>(0h1000)))
node _T_1304 = asSInt(_T_1303)
node _T_1305 = eq(_T_1304, asSInt(UInt<1>(0h0)))
node _T_1306 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1307 = cvt(_T_1306)
node _T_1308 = and(_T_1307, asSInt(UInt<17>(0h10000)))
node _T_1309 = asSInt(_T_1308)
node _T_1310 = eq(_T_1309, asSInt(UInt<1>(0h0)))
node _T_1311 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1312 = cvt(_T_1311)
node _T_1313 = and(_T_1312, asSInt(UInt<27>(0h4000000)))
node _T_1314 = asSInt(_T_1313)
node _T_1315 = eq(_T_1314, asSInt(UInt<1>(0h0)))
node _T_1316 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1317 = cvt(_T_1316)
node _T_1318 = and(_T_1317, asSInt(UInt<13>(0h1000)))
node _T_1319 = asSInt(_T_1318)
node _T_1320 = eq(_T_1319, asSInt(UInt<1>(0h0)))
node _T_1321 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1322 = cvt(_T_1321)
node _T_1323 = and(_T_1322, asSInt(UInt<29>(0h10000000)))
node _T_1324 = asSInt(_T_1323)
node _T_1325 = eq(_T_1324, asSInt(UInt<1>(0h0)))
node _T_1326 = or(_T_1280, _T_1285)
node _T_1327 = or(_T_1326, _T_1290)
node _T_1328 = or(_T_1327, _T_1295)
node _T_1329 = or(_T_1328, _T_1300)
node _T_1330 = or(_T_1329, _T_1305)
node _T_1331 = or(_T_1330, _T_1310)
node _T_1332 = or(_T_1331, _T_1315)
node _T_1333 = or(_T_1332, _T_1320)
node _T_1334 = or(_T_1333, _T_1325)
node _T_1335 = and(_T_1275, _T_1334)
node _T_1336 = or(UInt<1>(0h0), _T_1335)
node _T_1337 = and(UInt<1>(0h0), _T_1336)
node _T_1338 = asUInt(reset)
node _T_1339 = eq(_T_1338, UInt<1>(0h0))
when _T_1339 :
node _T_1340 = eq(_T_1337, UInt<1>(0h0))
when _T_1340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1337, UInt<1>(0h1), "") : assert_93
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(address_ok, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(legal_source, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1347 = asUInt(reset)
node _T_1348 = eq(_T_1347, UInt<1>(0h0))
when _T_1348 :
node _T_1349 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1350 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_97
node _T_1354 = eq(io.in.b.bits.mask, mask_1)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_98
node _T_1358 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_99
node _T_1362 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1364 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1365 = and(_T_1363, _T_1364)
node _T_1366 = or(UInt<1>(0h0), _T_1365)
node _T_1367 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1368 = cvt(_T_1367)
node _T_1369 = and(_T_1368, asSInt(UInt<14>(0h2000)))
node _T_1370 = asSInt(_T_1369)
node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0)))
node _T_1372 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1373 = cvt(_T_1372)
node _T_1374 = and(_T_1373, asSInt(UInt<13>(0h1000)))
node _T_1375 = asSInt(_T_1374)
node _T_1376 = eq(_T_1375, asSInt(UInt<1>(0h0)))
node _T_1377 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1378 = cvt(_T_1377)
node _T_1379 = and(_T_1378, asSInt(UInt<17>(0h10000)))
node _T_1380 = asSInt(_T_1379)
node _T_1381 = eq(_T_1380, asSInt(UInt<1>(0h0)))
node _T_1382 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1383 = cvt(_T_1382)
node _T_1384 = and(_T_1383, asSInt(UInt<18>(0h2f000)))
node _T_1385 = asSInt(_T_1384)
node _T_1386 = eq(_T_1385, asSInt(UInt<1>(0h0)))
node _T_1387 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1388 = cvt(_T_1387)
node _T_1389 = and(_T_1388, asSInt(UInt<17>(0h10000)))
node _T_1390 = asSInt(_T_1389)
node _T_1391 = eq(_T_1390, asSInt(UInt<1>(0h0)))
node _T_1392 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1393 = cvt(_T_1392)
node _T_1394 = and(_T_1393, asSInt(UInt<13>(0h1000)))
node _T_1395 = asSInt(_T_1394)
node _T_1396 = eq(_T_1395, asSInt(UInt<1>(0h0)))
node _T_1397 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1398 = cvt(_T_1397)
node _T_1399 = and(_T_1398, asSInt(UInt<17>(0h10000)))
node _T_1400 = asSInt(_T_1399)
node _T_1401 = eq(_T_1400, asSInt(UInt<1>(0h0)))
node _T_1402 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1403 = cvt(_T_1402)
node _T_1404 = and(_T_1403, asSInt(UInt<27>(0h4000000)))
node _T_1405 = asSInt(_T_1404)
node _T_1406 = eq(_T_1405, asSInt(UInt<1>(0h0)))
node _T_1407 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1408 = cvt(_T_1407)
node _T_1409 = and(_T_1408, asSInt(UInt<13>(0h1000)))
node _T_1410 = asSInt(_T_1409)
node _T_1411 = eq(_T_1410, asSInt(UInt<1>(0h0)))
node _T_1412 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1413 = cvt(_T_1412)
node _T_1414 = and(_T_1413, asSInt(UInt<29>(0h10000000)))
node _T_1415 = asSInt(_T_1414)
node _T_1416 = eq(_T_1415, asSInt(UInt<1>(0h0)))
node _T_1417 = or(_T_1371, _T_1376)
node _T_1418 = or(_T_1417, _T_1381)
node _T_1419 = or(_T_1418, _T_1386)
node _T_1420 = or(_T_1419, _T_1391)
node _T_1421 = or(_T_1420, _T_1396)
node _T_1422 = or(_T_1421, _T_1401)
node _T_1423 = or(_T_1422, _T_1406)
node _T_1424 = or(_T_1423, _T_1411)
node _T_1425 = or(_T_1424, _T_1416)
node _T_1426 = and(_T_1366, _T_1425)
node _T_1427 = or(UInt<1>(0h0), _T_1426)
node _T_1428 = and(UInt<1>(0h0), _T_1427)
node _T_1429 = asUInt(reset)
node _T_1430 = eq(_T_1429, UInt<1>(0h0))
when _T_1430 :
node _T_1431 = eq(_T_1428, UInt<1>(0h0))
when _T_1431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1428, UInt<1>(0h1), "") : assert_100
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(address_ok, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1435 = asUInt(reset)
node _T_1436 = eq(_T_1435, UInt<1>(0h0))
when _T_1436 :
node _T_1437 = eq(legal_source, UInt<1>(0h0))
when _T_1437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1438 = asUInt(reset)
node _T_1439 = eq(_T_1438, UInt<1>(0h0))
when _T_1439 :
node _T_1440 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1441 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_104
node _T_1445 = eq(io.in.b.bits.mask, mask_1)
node _T_1446 = asUInt(reset)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = eq(_T_1445, UInt<1>(0h0))
when _T_1448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1445, UInt<1>(0h1), "") : assert_105
node _T_1449 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1449 :
node _T_1450 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1451 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1452 = and(_T_1450, _T_1451)
node _T_1453 = or(UInt<1>(0h0), _T_1452)
node _T_1454 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1455 = cvt(_T_1454)
node _T_1456 = and(_T_1455, asSInt(UInt<14>(0h2000)))
node _T_1457 = asSInt(_T_1456)
node _T_1458 = eq(_T_1457, asSInt(UInt<1>(0h0)))
node _T_1459 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1460 = cvt(_T_1459)
node _T_1461 = and(_T_1460, asSInt(UInt<13>(0h1000)))
node _T_1462 = asSInt(_T_1461)
node _T_1463 = eq(_T_1462, asSInt(UInt<1>(0h0)))
node _T_1464 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1465 = cvt(_T_1464)
node _T_1466 = and(_T_1465, asSInt(UInt<17>(0h10000)))
node _T_1467 = asSInt(_T_1466)
node _T_1468 = eq(_T_1467, asSInt(UInt<1>(0h0)))
node _T_1469 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1470 = cvt(_T_1469)
node _T_1471 = and(_T_1470, asSInt(UInt<18>(0h2f000)))
node _T_1472 = asSInt(_T_1471)
node _T_1473 = eq(_T_1472, asSInt(UInt<1>(0h0)))
node _T_1474 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1475 = cvt(_T_1474)
node _T_1476 = and(_T_1475, asSInt(UInt<17>(0h10000)))
node _T_1477 = asSInt(_T_1476)
node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0)))
node _T_1479 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1480 = cvt(_T_1479)
node _T_1481 = and(_T_1480, asSInt(UInt<13>(0h1000)))
node _T_1482 = asSInt(_T_1481)
node _T_1483 = eq(_T_1482, asSInt(UInt<1>(0h0)))
node _T_1484 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1485 = cvt(_T_1484)
node _T_1486 = and(_T_1485, asSInt(UInt<17>(0h10000)))
node _T_1487 = asSInt(_T_1486)
node _T_1488 = eq(_T_1487, asSInt(UInt<1>(0h0)))
node _T_1489 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1490 = cvt(_T_1489)
node _T_1491 = and(_T_1490, asSInt(UInt<27>(0h4000000)))
node _T_1492 = asSInt(_T_1491)
node _T_1493 = eq(_T_1492, asSInt(UInt<1>(0h0)))
node _T_1494 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1495 = cvt(_T_1494)
node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000)))
node _T_1497 = asSInt(_T_1496)
node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0)))
node _T_1499 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1500 = cvt(_T_1499)
node _T_1501 = and(_T_1500, asSInt(UInt<29>(0h10000000)))
node _T_1502 = asSInt(_T_1501)
node _T_1503 = eq(_T_1502, asSInt(UInt<1>(0h0)))
node _T_1504 = or(_T_1458, _T_1463)
node _T_1505 = or(_T_1504, _T_1468)
node _T_1506 = or(_T_1505, _T_1473)
node _T_1507 = or(_T_1506, _T_1478)
node _T_1508 = or(_T_1507, _T_1483)
node _T_1509 = or(_T_1508, _T_1488)
node _T_1510 = or(_T_1509, _T_1493)
node _T_1511 = or(_T_1510, _T_1498)
node _T_1512 = or(_T_1511, _T_1503)
node _T_1513 = and(_T_1453, _T_1512)
node _T_1514 = or(UInt<1>(0h0), _T_1513)
node _T_1515 = and(UInt<1>(0h0), _T_1514)
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_106
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(address_ok, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1522 = asUInt(reset)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
when _T_1523 :
node _T_1524 = eq(legal_source, UInt<1>(0h0))
when _T_1524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1528 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1529 = asUInt(reset)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
when _T_1530 :
node _T_1531 = eq(_T_1528, UInt<1>(0h0))
when _T_1531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1528, UInt<1>(0h1), "") : assert_110
node _T_1532 = not(mask_1)
node _T_1533 = and(io.in.b.bits.mask, _T_1532)
node _T_1534 = eq(_T_1533, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_111
node _T_1538 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1538 :
node _T_1539 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1540 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1541 = and(_T_1539, _T_1540)
node _T_1542 = or(UInt<1>(0h0), _T_1541)
node _T_1543 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1544 = cvt(_T_1543)
node _T_1545 = and(_T_1544, asSInt(UInt<14>(0h2000)))
node _T_1546 = asSInt(_T_1545)
node _T_1547 = eq(_T_1546, asSInt(UInt<1>(0h0)))
node _T_1548 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1549 = cvt(_T_1548)
node _T_1550 = and(_T_1549, asSInt(UInt<13>(0h1000)))
node _T_1551 = asSInt(_T_1550)
node _T_1552 = eq(_T_1551, asSInt(UInt<1>(0h0)))
node _T_1553 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1554 = cvt(_T_1553)
node _T_1555 = and(_T_1554, asSInt(UInt<17>(0h10000)))
node _T_1556 = asSInt(_T_1555)
node _T_1557 = eq(_T_1556, asSInt(UInt<1>(0h0)))
node _T_1558 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1559 = cvt(_T_1558)
node _T_1560 = and(_T_1559, asSInt(UInt<18>(0h2f000)))
node _T_1561 = asSInt(_T_1560)
node _T_1562 = eq(_T_1561, asSInt(UInt<1>(0h0)))
node _T_1563 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1564 = cvt(_T_1563)
node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000)))
node _T_1566 = asSInt(_T_1565)
node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0)))
node _T_1568 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1569 = cvt(_T_1568)
node _T_1570 = and(_T_1569, asSInt(UInt<13>(0h1000)))
node _T_1571 = asSInt(_T_1570)
node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1574 = cvt(_T_1573)
node _T_1575 = and(_T_1574, asSInt(UInt<17>(0h10000)))
node _T_1576 = asSInt(_T_1575)
node _T_1577 = eq(_T_1576, asSInt(UInt<1>(0h0)))
node _T_1578 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1579 = cvt(_T_1578)
node _T_1580 = and(_T_1579, asSInt(UInt<27>(0h4000000)))
node _T_1581 = asSInt(_T_1580)
node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0)))
node _T_1583 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1584 = cvt(_T_1583)
node _T_1585 = and(_T_1584, asSInt(UInt<13>(0h1000)))
node _T_1586 = asSInt(_T_1585)
node _T_1587 = eq(_T_1586, asSInt(UInt<1>(0h0)))
node _T_1588 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1589 = cvt(_T_1588)
node _T_1590 = and(_T_1589, asSInt(UInt<29>(0h10000000)))
node _T_1591 = asSInt(_T_1590)
node _T_1592 = eq(_T_1591, asSInt(UInt<1>(0h0)))
node _T_1593 = or(_T_1547, _T_1552)
node _T_1594 = or(_T_1593, _T_1557)
node _T_1595 = or(_T_1594, _T_1562)
node _T_1596 = or(_T_1595, _T_1567)
node _T_1597 = or(_T_1596, _T_1572)
node _T_1598 = or(_T_1597, _T_1577)
node _T_1599 = or(_T_1598, _T_1582)
node _T_1600 = or(_T_1599, _T_1587)
node _T_1601 = or(_T_1600, _T_1592)
node _T_1602 = and(_T_1542, _T_1601)
node _T_1603 = or(UInt<1>(0h0), _T_1602)
node _T_1604 = and(UInt<1>(0h0), _T_1603)
node _T_1605 = asUInt(reset)
node _T_1606 = eq(_T_1605, UInt<1>(0h0))
when _T_1606 :
node _T_1607 = eq(_T_1604, UInt<1>(0h0))
when _T_1607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1604, UInt<1>(0h1), "") : assert_112
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(address_ok, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(legal_source, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1614 = asUInt(reset)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
when _T_1615 :
node _T_1616 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1617 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1618 = asUInt(reset)
node _T_1619 = eq(_T_1618, UInt<1>(0h0))
when _T_1619 :
node _T_1620 = eq(_T_1617, UInt<1>(0h0))
when _T_1620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1617, UInt<1>(0h1), "") : assert_116
node _T_1621 = eq(io.in.b.bits.mask, mask_1)
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_117
node _T_1625 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1625 :
node _T_1626 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1627 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1628 = and(_T_1626, _T_1627)
node _T_1629 = or(UInt<1>(0h0), _T_1628)
node _T_1630 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1631 = cvt(_T_1630)
node _T_1632 = and(_T_1631, asSInt(UInt<14>(0h2000)))
node _T_1633 = asSInt(_T_1632)
node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0)))
node _T_1635 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1636 = cvt(_T_1635)
node _T_1637 = and(_T_1636, asSInt(UInt<13>(0h1000)))
node _T_1638 = asSInt(_T_1637)
node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0)))
node _T_1640 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1641 = cvt(_T_1640)
node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000)))
node _T_1643 = asSInt(_T_1642)
node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0)))
node _T_1645 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1646 = cvt(_T_1645)
node _T_1647 = and(_T_1646, asSInt(UInt<18>(0h2f000)))
node _T_1648 = asSInt(_T_1647)
node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0)))
node _T_1650 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1651 = cvt(_T_1650)
node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000)))
node _T_1653 = asSInt(_T_1652)
node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0)))
node _T_1655 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1656 = cvt(_T_1655)
node _T_1657 = and(_T_1656, asSInt(UInt<13>(0h1000)))
node _T_1658 = asSInt(_T_1657)
node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0)))
node _T_1660 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1661 = cvt(_T_1660)
node _T_1662 = and(_T_1661, asSInt(UInt<17>(0h10000)))
node _T_1663 = asSInt(_T_1662)
node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0)))
node _T_1665 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1666 = cvt(_T_1665)
node _T_1667 = and(_T_1666, asSInt(UInt<27>(0h4000000)))
node _T_1668 = asSInt(_T_1667)
node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0)))
node _T_1670 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1671 = cvt(_T_1670)
node _T_1672 = and(_T_1671, asSInt(UInt<13>(0h1000)))
node _T_1673 = asSInt(_T_1672)
node _T_1674 = eq(_T_1673, asSInt(UInt<1>(0h0)))
node _T_1675 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1676 = cvt(_T_1675)
node _T_1677 = and(_T_1676, asSInt(UInt<29>(0h10000000)))
node _T_1678 = asSInt(_T_1677)
node _T_1679 = eq(_T_1678, asSInt(UInt<1>(0h0)))
node _T_1680 = or(_T_1634, _T_1639)
node _T_1681 = or(_T_1680, _T_1644)
node _T_1682 = or(_T_1681, _T_1649)
node _T_1683 = or(_T_1682, _T_1654)
node _T_1684 = or(_T_1683, _T_1659)
node _T_1685 = or(_T_1684, _T_1664)
node _T_1686 = or(_T_1685, _T_1669)
node _T_1687 = or(_T_1686, _T_1674)
node _T_1688 = or(_T_1687, _T_1679)
node _T_1689 = and(_T_1629, _T_1688)
node _T_1690 = or(UInt<1>(0h0), _T_1689)
node _T_1691 = and(UInt<1>(0h0), _T_1690)
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_118
node _T_1695 = asUInt(reset)
node _T_1696 = eq(_T_1695, UInt<1>(0h0))
when _T_1696 :
node _T_1697 = eq(address_ok, UInt<1>(0h0))
when _T_1697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1698 = asUInt(reset)
node _T_1699 = eq(_T_1698, UInt<1>(0h0))
when _T_1699 :
node _T_1700 = eq(legal_source, UInt<1>(0h0))
when _T_1700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1701 = asUInt(reset)
node _T_1702 = eq(_T_1701, UInt<1>(0h0))
when _T_1702 :
node _T_1703 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1704 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1705 = asUInt(reset)
node _T_1706 = eq(_T_1705, UInt<1>(0h0))
when _T_1706 :
node _T_1707 = eq(_T_1704, UInt<1>(0h0))
when _T_1707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1704, UInt<1>(0h1), "") : assert_122
node _T_1708 = eq(io.in.b.bits.mask, mask_1)
node _T_1709 = asUInt(reset)
node _T_1710 = eq(_T_1709, UInt<1>(0h0))
when _T_1710 :
node _T_1711 = eq(_T_1708, UInt<1>(0h0))
when _T_1711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1708, UInt<1>(0h1), "") : assert_123
node _T_1712 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1712 :
node _T_1713 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1714 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1715 = and(_T_1713, _T_1714)
node _T_1716 = or(UInt<1>(0h0), _T_1715)
node _T_1717 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1718 = cvt(_T_1717)
node _T_1719 = and(_T_1718, asSInt(UInt<14>(0h2000)))
node _T_1720 = asSInt(_T_1719)
node _T_1721 = eq(_T_1720, asSInt(UInt<1>(0h0)))
node _T_1722 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1723 = cvt(_T_1722)
node _T_1724 = and(_T_1723, asSInt(UInt<13>(0h1000)))
node _T_1725 = asSInt(_T_1724)
node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0)))
node _T_1727 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1728 = cvt(_T_1727)
node _T_1729 = and(_T_1728, asSInt(UInt<17>(0h10000)))
node _T_1730 = asSInt(_T_1729)
node _T_1731 = eq(_T_1730, asSInt(UInt<1>(0h0)))
node _T_1732 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1733 = cvt(_T_1732)
node _T_1734 = and(_T_1733, asSInt(UInt<18>(0h2f000)))
node _T_1735 = asSInt(_T_1734)
node _T_1736 = eq(_T_1735, asSInt(UInt<1>(0h0)))
node _T_1737 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1738 = cvt(_T_1737)
node _T_1739 = and(_T_1738, asSInt(UInt<17>(0h10000)))
node _T_1740 = asSInt(_T_1739)
node _T_1741 = eq(_T_1740, asSInt(UInt<1>(0h0)))
node _T_1742 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1743 = cvt(_T_1742)
node _T_1744 = and(_T_1743, asSInt(UInt<13>(0h1000)))
node _T_1745 = asSInt(_T_1744)
node _T_1746 = eq(_T_1745, asSInt(UInt<1>(0h0)))
node _T_1747 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1748 = cvt(_T_1747)
node _T_1749 = and(_T_1748, asSInt(UInt<17>(0h10000)))
node _T_1750 = asSInt(_T_1749)
node _T_1751 = eq(_T_1750, asSInt(UInt<1>(0h0)))
node _T_1752 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1753 = cvt(_T_1752)
node _T_1754 = and(_T_1753, asSInt(UInt<27>(0h4000000)))
node _T_1755 = asSInt(_T_1754)
node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0)))
node _T_1757 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1758 = cvt(_T_1757)
node _T_1759 = and(_T_1758, asSInt(UInt<13>(0h1000)))
node _T_1760 = asSInt(_T_1759)
node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0)))
node _T_1762 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1763 = cvt(_T_1762)
node _T_1764 = and(_T_1763, asSInt(UInt<29>(0h10000000)))
node _T_1765 = asSInt(_T_1764)
node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0)))
node _T_1767 = or(_T_1721, _T_1726)
node _T_1768 = or(_T_1767, _T_1731)
node _T_1769 = or(_T_1768, _T_1736)
node _T_1770 = or(_T_1769, _T_1741)
node _T_1771 = or(_T_1770, _T_1746)
node _T_1772 = or(_T_1771, _T_1751)
node _T_1773 = or(_T_1772, _T_1756)
node _T_1774 = or(_T_1773, _T_1761)
node _T_1775 = or(_T_1774, _T_1766)
node _T_1776 = and(_T_1716, _T_1775)
node _T_1777 = or(UInt<1>(0h0), _T_1776)
node _T_1778 = and(UInt<1>(0h0), _T_1777)
node _T_1779 = asUInt(reset)
node _T_1780 = eq(_T_1779, UInt<1>(0h0))
when _T_1780 :
node _T_1781 = eq(_T_1778, UInt<1>(0h0))
when _T_1781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1778, UInt<1>(0h1), "") : assert_124
node _T_1782 = asUInt(reset)
node _T_1783 = eq(_T_1782, UInt<1>(0h0))
when _T_1783 :
node _T_1784 = eq(address_ok, UInt<1>(0h0))
when _T_1784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1785 = asUInt(reset)
node _T_1786 = eq(_T_1785, UInt<1>(0h0))
when _T_1786 :
node _T_1787 = eq(legal_source, UInt<1>(0h0))
when _T_1787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1791 = eq(io.in.b.bits.mask, mask_1)
node _T_1792 = asUInt(reset)
node _T_1793 = eq(_T_1792, UInt<1>(0h0))
when _T_1793 :
node _T_1794 = eq(_T_1791, UInt<1>(0h0))
when _T_1794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1791, UInt<1>(0h1), "") : assert_128
node _T_1795 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1796 = asUInt(reset)
node _T_1797 = eq(_T_1796, UInt<1>(0h0))
when _T_1797 :
node _T_1798 = eq(_T_1795, UInt<1>(0h0))
when _T_1798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1795, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1799 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1800 = asUInt(reset)
node _T_1801 = eq(_T_1800, UInt<1>(0h0))
when _T_1801 :
node _T_1802 = eq(_T_1799, UInt<1>(0h0))
when _T_1802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1799, UInt<1>(0h1), "") : assert_130
node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_2 : UInt<1>[3]
connect _source_ok_WIRE_2[0], _source_ok_T_8
connect _source_ok_WIRE_2[1], _source_ok_T_9
connect _source_ok_WIRE_2[2], _source_ok_T_10
node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _T_1803 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
node _T_1805 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1806 = cvt(_T_1805)
node _T_1807 = and(_T_1806, asSInt(UInt<1>(0h0)))
node _T_1808 = asSInt(_T_1807)
node _T_1809 = eq(_T_1808, asSInt(UInt<1>(0h0)))
node _T_1810 = or(_T_1804, _T_1809)
node _T_1811 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1812 = eq(_T_1811, UInt<1>(0h0))
node _T_1813 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1814 = cvt(_T_1813)
node _T_1815 = and(_T_1814, asSInt(UInt<1>(0h0)))
node _T_1816 = asSInt(_T_1815)
node _T_1817 = eq(_T_1816, asSInt(UInt<1>(0h0)))
node _T_1818 = or(_T_1812, _T_1817)
node _T_1819 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1820 = eq(_T_1819, UInt<1>(0h0))
node _T_1821 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1822 = cvt(_T_1821)
node _T_1823 = and(_T_1822, asSInt(UInt<1>(0h0)))
node _T_1824 = asSInt(_T_1823)
node _T_1825 = eq(_T_1824, asSInt(UInt<1>(0h0)))
node _T_1826 = or(_T_1820, _T_1825)
node _T_1827 = and(_T_1810, _T_1818)
node _T_1828 = and(_T_1827, _T_1826)
node _T_1829 = asUInt(reset)
node _T_1830 = eq(_T_1829, UInt<1>(0h0))
when _T_1830 :
node _T_1831 = eq(_T_1828, UInt<1>(0h0))
when _T_1831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1828, UInt<1>(0h1), "") : assert_131
node _T_1832 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1832 :
node _T_1833 = asUInt(reset)
node _T_1834 = eq(_T_1833, UInt<1>(0h0))
when _T_1834 :
node _T_1835 = eq(address_ok_1, UInt<1>(0h0))
when _T_1835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1836 = asUInt(reset)
node _T_1837 = eq(_T_1836, UInt<1>(0h0))
when _T_1837 :
node _T_1838 = eq(source_ok_2, UInt<1>(0h0))
when _T_1838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1839 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1840 = asUInt(reset)
node _T_1841 = eq(_T_1840, UInt<1>(0h0))
when _T_1841 :
node _T_1842 = eq(_T_1839, UInt<1>(0h0))
when _T_1842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1839, UInt<1>(0h1), "") : assert_134
node _T_1843 = asUInt(reset)
node _T_1844 = eq(_T_1843, UInt<1>(0h0))
when _T_1844 :
node _T_1845 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1846 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(_T_1846, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1846, UInt<1>(0h1), "") : assert_136
node _T_1850 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1851 = asUInt(reset)
node _T_1852 = eq(_T_1851, UInt<1>(0h0))
when _T_1852 :
node _T_1853 = eq(_T_1850, UInt<1>(0h0))
when _T_1853 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1850, UInt<1>(0h1), "") : assert_137
node _T_1854 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1854 :
node _T_1855 = asUInt(reset)
node _T_1856 = eq(_T_1855, UInt<1>(0h0))
when _T_1856 :
node _T_1857 = eq(address_ok_1, UInt<1>(0h0))
when _T_1857 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1858 = asUInt(reset)
node _T_1859 = eq(_T_1858, UInt<1>(0h0))
when _T_1859 :
node _T_1860 = eq(source_ok_2, UInt<1>(0h0))
when _T_1860 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1861 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1862 = asUInt(reset)
node _T_1863 = eq(_T_1862, UInt<1>(0h0))
when _T_1863 :
node _T_1864 = eq(_T_1861, UInt<1>(0h0))
when _T_1864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1861, UInt<1>(0h1), "") : assert_140
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1868 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1869 = asUInt(reset)
node _T_1870 = eq(_T_1869, UInt<1>(0h0))
when _T_1870 :
node _T_1871 = eq(_T_1868, UInt<1>(0h0))
when _T_1871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1868, UInt<1>(0h1), "") : assert_142
node _T_1872 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1872 :
node _T_1873 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1874 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1875 = and(_T_1873, _T_1874)
node _T_1876 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1877 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1878 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_1879 = or(_T_1876, _T_1877)
node _T_1880 = or(_T_1879, _T_1878)
node _T_1881 = and(_T_1875, _T_1880)
node _T_1882 = or(UInt<1>(0h0), _T_1881)
node _T_1883 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1884 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1885 = cvt(_T_1884)
node _T_1886 = and(_T_1885, asSInt(UInt<14>(0h2000)))
node _T_1887 = asSInt(_T_1886)
node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0)))
node _T_1889 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1890 = cvt(_T_1889)
node _T_1891 = and(_T_1890, asSInt(UInt<13>(0h1000)))
node _T_1892 = asSInt(_T_1891)
node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1895 = cvt(_T_1894)
node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000)))
node _T_1897 = asSInt(_T_1896)
node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0)))
node _T_1899 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1900 = cvt(_T_1899)
node _T_1901 = and(_T_1900, asSInt(UInt<18>(0h2f000)))
node _T_1902 = asSInt(_T_1901)
node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0)))
node _T_1904 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1905 = cvt(_T_1904)
node _T_1906 = and(_T_1905, asSInt(UInt<17>(0h10000)))
node _T_1907 = asSInt(_T_1906)
node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0)))
node _T_1909 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1910 = cvt(_T_1909)
node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000)))
node _T_1912 = asSInt(_T_1911)
node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0)))
node _T_1914 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1915 = cvt(_T_1914)
node _T_1916 = and(_T_1915, asSInt(UInt<27>(0h4000000)))
node _T_1917 = asSInt(_T_1916)
node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0)))
node _T_1919 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1920 = cvt(_T_1919)
node _T_1921 = and(_T_1920, asSInt(UInt<13>(0h1000)))
node _T_1922 = asSInt(_T_1921)
node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0)))
node _T_1924 = or(_T_1888, _T_1893)
node _T_1925 = or(_T_1924, _T_1898)
node _T_1926 = or(_T_1925, _T_1903)
node _T_1927 = or(_T_1926, _T_1908)
node _T_1928 = or(_T_1927, _T_1913)
node _T_1929 = or(_T_1928, _T_1918)
node _T_1930 = or(_T_1929, _T_1923)
node _T_1931 = and(_T_1883, _T_1930)
node _T_1932 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1933 = or(UInt<1>(0h0), _T_1932)
node _T_1934 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1935 = cvt(_T_1934)
node _T_1936 = and(_T_1935, asSInt(UInt<17>(0h10000)))
node _T_1937 = asSInt(_T_1936)
node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0)))
node _T_1939 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1940 = cvt(_T_1939)
node _T_1941 = and(_T_1940, asSInt(UInt<29>(0h10000000)))
node _T_1942 = asSInt(_T_1941)
node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0)))
node _T_1944 = or(_T_1938, _T_1943)
node _T_1945 = and(_T_1933, _T_1944)
node _T_1946 = or(UInt<1>(0h0), _T_1931)
node _T_1947 = or(_T_1946, _T_1945)
node _T_1948 = and(_T_1882, _T_1947)
node _T_1949 = asUInt(reset)
node _T_1950 = eq(_T_1949, UInt<1>(0h0))
when _T_1950 :
node _T_1951 = eq(_T_1948, UInt<1>(0h0))
when _T_1951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1948, UInt<1>(0h1), "") : assert_143
node _T_1952 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1953 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1954 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_6 : UInt<1>[3]
connect _WIRE_6[0], _T_1952
connect _WIRE_6[1], _T_1953
connect _WIRE_6[2], _T_1954
node _T_1955 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1956 = mux(_WIRE_6[0], _T_1955, UInt<1>(0h0))
node _T_1957 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1958 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1959 = or(_T_1956, _T_1957)
node _T_1960 = or(_T_1959, _T_1958)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1960
node _T_1961 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1962 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1963 = and(_T_1961, _T_1962)
node _T_1964 = or(UInt<1>(0h0), _T_1963)
node _T_1965 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1966 = cvt(_T_1965)
node _T_1967 = and(_T_1966, asSInt(UInt<14>(0h2000)))
node _T_1968 = asSInt(_T_1967)
node _T_1969 = eq(_T_1968, asSInt(UInt<1>(0h0)))
node _T_1970 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1971 = cvt(_T_1970)
node _T_1972 = and(_T_1971, asSInt(UInt<13>(0h1000)))
node _T_1973 = asSInt(_T_1972)
node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0)))
node _T_1975 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1976 = cvt(_T_1975)
node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000)))
node _T_1978 = asSInt(_T_1977)
node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0)))
node _T_1980 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1981 = cvt(_T_1980)
node _T_1982 = and(_T_1981, asSInt(UInt<18>(0h2f000)))
node _T_1983 = asSInt(_T_1982)
node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0)))
node _T_1985 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1986 = cvt(_T_1985)
node _T_1987 = and(_T_1986, asSInt(UInt<17>(0h10000)))
node _T_1988 = asSInt(_T_1987)
node _T_1989 = eq(_T_1988, asSInt(UInt<1>(0h0)))
node _T_1990 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1991 = cvt(_T_1990)
node _T_1992 = and(_T_1991, asSInt(UInt<13>(0h1000)))
node _T_1993 = asSInt(_T_1992)
node _T_1994 = eq(_T_1993, asSInt(UInt<1>(0h0)))
node _T_1995 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1996 = cvt(_T_1995)
node _T_1997 = and(_T_1996, asSInt(UInt<17>(0h10000)))
node _T_1998 = asSInt(_T_1997)
node _T_1999 = eq(_T_1998, asSInt(UInt<1>(0h0)))
node _T_2000 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2001 = cvt(_T_2000)
node _T_2002 = and(_T_2001, asSInt(UInt<27>(0h4000000)))
node _T_2003 = asSInt(_T_2002)
node _T_2004 = eq(_T_2003, asSInt(UInt<1>(0h0)))
node _T_2005 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2006 = cvt(_T_2005)
node _T_2007 = and(_T_2006, asSInt(UInt<13>(0h1000)))
node _T_2008 = asSInt(_T_2007)
node _T_2009 = eq(_T_2008, asSInt(UInt<1>(0h0)))
node _T_2010 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2011 = cvt(_T_2010)
node _T_2012 = and(_T_2011, asSInt(UInt<29>(0h10000000)))
node _T_2013 = asSInt(_T_2012)
node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0)))
node _T_2015 = or(_T_1969, _T_1974)
node _T_2016 = or(_T_2015, _T_1979)
node _T_2017 = or(_T_2016, _T_1984)
node _T_2018 = or(_T_2017, _T_1989)
node _T_2019 = or(_T_2018, _T_1994)
node _T_2020 = or(_T_2019, _T_1999)
node _T_2021 = or(_T_2020, _T_2004)
node _T_2022 = or(_T_2021, _T_2009)
node _T_2023 = or(_T_2022, _T_2014)
node _T_2024 = and(_T_1964, _T_2023)
node _T_2025 = or(UInt<1>(0h0), _T_2024)
node _T_2026 = and(_WIRE_7, _T_2025)
node _T_2027 = asUInt(reset)
node _T_2028 = eq(_T_2027, UInt<1>(0h0))
when _T_2028 :
node _T_2029 = eq(_T_2026, UInt<1>(0h0))
when _T_2029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2026, UInt<1>(0h1), "") : assert_144
node _T_2030 = asUInt(reset)
node _T_2031 = eq(_T_2030, UInt<1>(0h0))
when _T_2031 :
node _T_2032 = eq(source_ok_2, UInt<1>(0h0))
when _T_2032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2033 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2034 = asUInt(reset)
node _T_2035 = eq(_T_2034, UInt<1>(0h0))
when _T_2035 :
node _T_2036 = eq(_T_2033, UInt<1>(0h0))
when _T_2036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2033, UInt<1>(0h1), "") : assert_146
node _T_2037 = asUInt(reset)
node _T_2038 = eq(_T_2037, UInt<1>(0h0))
when _T_2038 :
node _T_2039 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2040 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2041 = asUInt(reset)
node _T_2042 = eq(_T_2041, UInt<1>(0h0))
when _T_2042 :
node _T_2043 = eq(_T_2040, UInt<1>(0h0))
when _T_2043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2040, UInt<1>(0h1), "") : assert_148
node _T_2044 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2045 = asUInt(reset)
node _T_2046 = eq(_T_2045, UInt<1>(0h0))
when _T_2046 :
node _T_2047 = eq(_T_2044, UInt<1>(0h0))
when _T_2047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2044, UInt<1>(0h1), "") : assert_149
node _T_2048 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2048 :
node _T_2049 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2050 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2051 = and(_T_2049, _T_2050)
node _T_2052 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2053 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2054 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2055 = or(_T_2052, _T_2053)
node _T_2056 = or(_T_2055, _T_2054)
node _T_2057 = and(_T_2051, _T_2056)
node _T_2058 = or(UInt<1>(0h0), _T_2057)
node _T_2059 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2060 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<14>(0h2000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2066 = cvt(_T_2065)
node _T_2067 = and(_T_2066, asSInt(UInt<13>(0h1000)))
node _T_2068 = asSInt(_T_2067)
node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0)))
node _T_2070 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<17>(0h10000)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2076 = cvt(_T_2075)
node _T_2077 = and(_T_2076, asSInt(UInt<18>(0h2f000)))
node _T_2078 = asSInt(_T_2077)
node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0)))
node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2081 = cvt(_T_2080)
node _T_2082 = and(_T_2081, asSInt(UInt<17>(0h10000)))
node _T_2083 = asSInt(_T_2082)
node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0)))
node _T_2085 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2086 = cvt(_T_2085)
node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000)))
node _T_2088 = asSInt(_T_2087)
node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0)))
node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2091 = cvt(_T_2090)
node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000)))
node _T_2093 = asSInt(_T_2092)
node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0)))
node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2096 = cvt(_T_2095)
node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000)))
node _T_2098 = asSInt(_T_2097)
node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0)))
node _T_2100 = or(_T_2064, _T_2069)
node _T_2101 = or(_T_2100, _T_2074)
node _T_2102 = or(_T_2101, _T_2079)
node _T_2103 = or(_T_2102, _T_2084)
node _T_2104 = or(_T_2103, _T_2089)
node _T_2105 = or(_T_2104, _T_2094)
node _T_2106 = or(_T_2105, _T_2099)
node _T_2107 = and(_T_2059, _T_2106)
node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2109 = or(UInt<1>(0h0), _T_2108)
node _T_2110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2111 = cvt(_T_2110)
node _T_2112 = and(_T_2111, asSInt(UInt<17>(0h10000)))
node _T_2113 = asSInt(_T_2112)
node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0)))
node _T_2115 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2116 = cvt(_T_2115)
node _T_2117 = and(_T_2116, asSInt(UInt<29>(0h10000000)))
node _T_2118 = asSInt(_T_2117)
node _T_2119 = eq(_T_2118, asSInt(UInt<1>(0h0)))
node _T_2120 = or(_T_2114, _T_2119)
node _T_2121 = and(_T_2109, _T_2120)
node _T_2122 = or(UInt<1>(0h0), _T_2107)
node _T_2123 = or(_T_2122, _T_2121)
node _T_2124 = and(_T_2058, _T_2123)
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(_T_2124, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2124, UInt<1>(0h1), "") : assert_150
node _T_2128 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2129 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2130 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_8 : UInt<1>[3]
connect _WIRE_8[0], _T_2128
connect _WIRE_8[1], _T_2129
connect _WIRE_8[2], _T_2130
node _T_2131 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2132 = mux(_WIRE_8[0], _T_2131, UInt<1>(0h0))
node _T_2133 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2134 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2135 = or(_T_2132, _T_2133)
node _T_2136 = or(_T_2135, _T_2134)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2136
node _T_2137 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2138 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2139 = and(_T_2137, _T_2138)
node _T_2140 = or(UInt<1>(0h0), _T_2139)
node _T_2141 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2142 = cvt(_T_2141)
node _T_2143 = and(_T_2142, asSInt(UInt<14>(0h2000)))
node _T_2144 = asSInt(_T_2143)
node _T_2145 = eq(_T_2144, asSInt(UInt<1>(0h0)))
node _T_2146 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2147 = cvt(_T_2146)
node _T_2148 = and(_T_2147, asSInt(UInt<13>(0h1000)))
node _T_2149 = asSInt(_T_2148)
node _T_2150 = eq(_T_2149, asSInt(UInt<1>(0h0)))
node _T_2151 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2152 = cvt(_T_2151)
node _T_2153 = and(_T_2152, asSInt(UInt<17>(0h10000)))
node _T_2154 = asSInt(_T_2153)
node _T_2155 = eq(_T_2154, asSInt(UInt<1>(0h0)))
node _T_2156 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2157 = cvt(_T_2156)
node _T_2158 = and(_T_2157, asSInt(UInt<18>(0h2f000)))
node _T_2159 = asSInt(_T_2158)
node _T_2160 = eq(_T_2159, asSInt(UInt<1>(0h0)))
node _T_2161 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2162 = cvt(_T_2161)
node _T_2163 = and(_T_2162, asSInt(UInt<17>(0h10000)))
node _T_2164 = asSInt(_T_2163)
node _T_2165 = eq(_T_2164, asSInt(UInt<1>(0h0)))
node _T_2166 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2167 = cvt(_T_2166)
node _T_2168 = and(_T_2167, asSInt(UInt<13>(0h1000)))
node _T_2169 = asSInt(_T_2168)
node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0)))
node _T_2171 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2172 = cvt(_T_2171)
node _T_2173 = and(_T_2172, asSInt(UInt<17>(0h10000)))
node _T_2174 = asSInt(_T_2173)
node _T_2175 = eq(_T_2174, asSInt(UInt<1>(0h0)))
node _T_2176 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2177 = cvt(_T_2176)
node _T_2178 = and(_T_2177, asSInt(UInt<27>(0h4000000)))
node _T_2179 = asSInt(_T_2178)
node _T_2180 = eq(_T_2179, asSInt(UInt<1>(0h0)))
node _T_2181 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2182 = cvt(_T_2181)
node _T_2183 = and(_T_2182, asSInt(UInt<13>(0h1000)))
node _T_2184 = asSInt(_T_2183)
node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0)))
node _T_2186 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2187 = cvt(_T_2186)
node _T_2188 = and(_T_2187, asSInt(UInt<29>(0h10000000)))
node _T_2189 = asSInt(_T_2188)
node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0)))
node _T_2191 = or(_T_2145, _T_2150)
node _T_2192 = or(_T_2191, _T_2155)
node _T_2193 = or(_T_2192, _T_2160)
node _T_2194 = or(_T_2193, _T_2165)
node _T_2195 = or(_T_2194, _T_2170)
node _T_2196 = or(_T_2195, _T_2175)
node _T_2197 = or(_T_2196, _T_2180)
node _T_2198 = or(_T_2197, _T_2185)
node _T_2199 = or(_T_2198, _T_2190)
node _T_2200 = and(_T_2140, _T_2199)
node _T_2201 = or(UInt<1>(0h0), _T_2200)
node _T_2202 = and(_WIRE_9, _T_2201)
node _T_2203 = asUInt(reset)
node _T_2204 = eq(_T_2203, UInt<1>(0h0))
when _T_2204 :
node _T_2205 = eq(_T_2202, UInt<1>(0h0))
when _T_2205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2202, UInt<1>(0h1), "") : assert_151
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
node _T_2208 = eq(source_ok_2, UInt<1>(0h0))
when _T_2208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2209 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_153
node _T_2213 = asUInt(reset)
node _T_2214 = eq(_T_2213, UInt<1>(0h0))
when _T_2214 :
node _T_2215 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2216 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2217 = asUInt(reset)
node _T_2218 = eq(_T_2217, UInt<1>(0h0))
when _T_2218 :
node _T_2219 = eq(_T_2216, UInt<1>(0h0))
when _T_2219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2216, UInt<1>(0h1), "") : assert_155
node _T_2220 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2220 :
node _T_2221 = asUInt(reset)
node _T_2222 = eq(_T_2221, UInt<1>(0h0))
when _T_2222 :
node _T_2223 = eq(address_ok_1, UInt<1>(0h0))
when _T_2223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2224 = asUInt(reset)
node _T_2225 = eq(_T_2224, UInt<1>(0h0))
when _T_2225 :
node _T_2226 = eq(source_ok_2, UInt<1>(0h0))
when _T_2226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2227 = asUInt(reset)
node _T_2228 = eq(_T_2227, UInt<1>(0h0))
when _T_2228 :
node _T_2229 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2230 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2231 = asUInt(reset)
node _T_2232 = eq(_T_2231, UInt<1>(0h0))
when _T_2232 :
node _T_2233 = eq(_T_2230, UInt<1>(0h0))
when _T_2233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2230, UInt<1>(0h1), "") : assert_159
node _T_2234 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2235 = asUInt(reset)
node _T_2236 = eq(_T_2235, UInt<1>(0h0))
when _T_2236 :
node _T_2237 = eq(_T_2234, UInt<1>(0h0))
when _T_2237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2234, UInt<1>(0h1), "") : assert_160
node _T_2238 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2238 :
node _T_2239 = asUInt(reset)
node _T_2240 = eq(_T_2239, UInt<1>(0h0))
when _T_2240 :
node _T_2241 = eq(address_ok_1, UInt<1>(0h0))
when _T_2241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
node _T_2244 = eq(source_ok_2, UInt<1>(0h0))
when _T_2244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2245 = asUInt(reset)
node _T_2246 = eq(_T_2245, UInt<1>(0h0))
when _T_2246 :
node _T_2247 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2248 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2249 = asUInt(reset)
node _T_2250 = eq(_T_2249, UInt<1>(0h0))
when _T_2250 :
node _T_2251 = eq(_T_2248, UInt<1>(0h0))
when _T_2251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2248, UInt<1>(0h1), "") : assert_164
node _T_2252 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2252 :
node _T_2253 = asUInt(reset)
node _T_2254 = eq(_T_2253, UInt<1>(0h0))
when _T_2254 :
node _T_2255 = eq(address_ok_1, UInt<1>(0h0))
when _T_2255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2256 = asUInt(reset)
node _T_2257 = eq(_T_2256, UInt<1>(0h0))
when _T_2257 :
node _T_2258 = eq(source_ok_2, UInt<1>(0h0))
when _T_2258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2259 = asUInt(reset)
node _T_2260 = eq(_T_2259, UInt<1>(0h0))
when _T_2260 :
node _T_2261 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2262 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2263 = asUInt(reset)
node _T_2264 = eq(_T_2263, UInt<1>(0h0))
when _T_2264 :
node _T_2265 = eq(_T_2262, UInt<1>(0h0))
when _T_2265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2262, UInt<1>(0h1), "") : assert_168
node _T_2266 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2267 = asUInt(reset)
node _T_2268 = eq(_T_2267, UInt<1>(0h0))
when _T_2268 :
node _T_2269 = eq(_T_2266, UInt<1>(0h0))
when _T_2269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2266, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
node _T_2272 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2273 = eq(a_first, UInt<1>(0h0))
node _T_2274 = and(io.in.a.valid, _T_2273)
when _T_2274 :
node _T_2275 = eq(io.in.a.bits.opcode, opcode)
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
node _T_2278 = eq(_T_2275, UInt<1>(0h0))
when _T_2278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2275, UInt<1>(0h1), "") : assert_171
node _T_2279 = eq(io.in.a.bits.param, param)
node _T_2280 = asUInt(reset)
node _T_2281 = eq(_T_2280, UInt<1>(0h0))
when _T_2281 :
node _T_2282 = eq(_T_2279, UInt<1>(0h0))
when _T_2282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2279, UInt<1>(0h1), "") : assert_172
node _T_2283 = eq(io.in.a.bits.size, size)
node _T_2284 = asUInt(reset)
node _T_2285 = eq(_T_2284, UInt<1>(0h0))
when _T_2285 :
node _T_2286 = eq(_T_2283, UInt<1>(0h0))
when _T_2286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2283, UInt<1>(0h1), "") : assert_173
node _T_2287 = eq(io.in.a.bits.source, source)
node _T_2288 = asUInt(reset)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
when _T_2289 :
node _T_2290 = eq(_T_2287, UInt<1>(0h0))
when _T_2290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2287, UInt<1>(0h1), "") : assert_174
node _T_2291 = eq(io.in.a.bits.address, address)
node _T_2292 = asUInt(reset)
node _T_2293 = eq(_T_2292, UInt<1>(0h0))
when _T_2293 :
node _T_2294 = eq(_T_2291, UInt<1>(0h0))
when _T_2294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2291, UInt<1>(0h1), "") : assert_175
node _T_2295 = and(io.in.a.ready, io.in.a.valid)
node _T_2296 = and(_T_2295, a_first)
when _T_2296 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2297 = eq(d_first, UInt<1>(0h0))
node _T_2298 = and(io.in.d.valid, _T_2297)
when _T_2298 :
node _T_2299 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_176
node _T_2303 = eq(io.in.d.bits.param, param_1)
node _T_2304 = asUInt(reset)
node _T_2305 = eq(_T_2304, UInt<1>(0h0))
when _T_2305 :
node _T_2306 = eq(_T_2303, UInt<1>(0h0))
when _T_2306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2303, UInt<1>(0h1), "") : assert_177
node _T_2307 = eq(io.in.d.bits.size, size_1)
node _T_2308 = asUInt(reset)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
when _T_2309 :
node _T_2310 = eq(_T_2307, UInt<1>(0h0))
when _T_2310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2307, UInt<1>(0h1), "") : assert_178
node _T_2311 = eq(io.in.d.bits.source, source_1)
node _T_2312 = asUInt(reset)
node _T_2313 = eq(_T_2312, UInt<1>(0h0))
when _T_2313 :
node _T_2314 = eq(_T_2311, UInt<1>(0h0))
when _T_2314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2311, UInt<1>(0h1), "") : assert_179
node _T_2315 = eq(io.in.d.bits.sink, sink)
node _T_2316 = asUInt(reset)
node _T_2317 = eq(_T_2316, UInt<1>(0h0))
when _T_2317 :
node _T_2318 = eq(_T_2315, UInt<1>(0h0))
when _T_2318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2315, UInt<1>(0h1), "") : assert_180
node _T_2319 = eq(io.in.d.bits.denied, denied)
node _T_2320 = asUInt(reset)
node _T_2321 = eq(_T_2320, UInt<1>(0h0))
when _T_2321 :
node _T_2322 = eq(_T_2319, UInt<1>(0h0))
when _T_2322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2319, UInt<1>(0h1), "") : assert_181
node _T_2323 = and(io.in.d.ready, io.in.d.valid)
node _T_2324 = and(_T_2323, d_first)
when _T_2324 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2325 = eq(b_first, UInt<1>(0h0))
node _T_2326 = and(io.in.b.valid, _T_2325)
when _T_2326 :
node _T_2327 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2328 = asUInt(reset)
node _T_2329 = eq(_T_2328, UInt<1>(0h0))
when _T_2329 :
node _T_2330 = eq(_T_2327, UInt<1>(0h0))
when _T_2330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2327, UInt<1>(0h1), "") : assert_182
node _T_2331 = eq(io.in.b.bits.param, param_2)
node _T_2332 = asUInt(reset)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
when _T_2333 :
node _T_2334 = eq(_T_2331, UInt<1>(0h0))
when _T_2334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2331, UInt<1>(0h1), "") : assert_183
node _T_2335 = eq(io.in.b.bits.size, size_2)
node _T_2336 = asUInt(reset)
node _T_2337 = eq(_T_2336, UInt<1>(0h0))
when _T_2337 :
node _T_2338 = eq(_T_2335, UInt<1>(0h0))
when _T_2338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2335, UInt<1>(0h1), "") : assert_184
node _T_2339 = eq(io.in.b.bits.source, source_2)
node _T_2340 = asUInt(reset)
node _T_2341 = eq(_T_2340, UInt<1>(0h0))
when _T_2341 :
node _T_2342 = eq(_T_2339, UInt<1>(0h0))
when _T_2342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2339, UInt<1>(0h1), "") : assert_185
node _T_2343 = eq(io.in.b.bits.address, address_1)
node _T_2344 = asUInt(reset)
node _T_2345 = eq(_T_2344, UInt<1>(0h0))
when _T_2345 :
node _T_2346 = eq(_T_2343, UInt<1>(0h0))
when _T_2346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2343, UInt<1>(0h1), "") : assert_186
node _T_2347 = and(io.in.b.ready, io.in.b.valid)
node _T_2348 = and(_T_2347, b_first)
when _T_2348 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2349 = eq(c_first, UInt<1>(0h0))
node _T_2350 = and(io.in.c.valid, _T_2349)
when _T_2350 :
node _T_2351 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2352 = asUInt(reset)
node _T_2353 = eq(_T_2352, UInt<1>(0h0))
when _T_2353 :
node _T_2354 = eq(_T_2351, UInt<1>(0h0))
when _T_2354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2351, UInt<1>(0h1), "") : assert_187
node _T_2355 = eq(io.in.c.bits.param, param_3)
node _T_2356 = asUInt(reset)
node _T_2357 = eq(_T_2356, UInt<1>(0h0))
when _T_2357 :
node _T_2358 = eq(_T_2355, UInt<1>(0h0))
when _T_2358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2355, UInt<1>(0h1), "") : assert_188
node _T_2359 = eq(io.in.c.bits.size, size_3)
node _T_2360 = asUInt(reset)
node _T_2361 = eq(_T_2360, UInt<1>(0h0))
when _T_2361 :
node _T_2362 = eq(_T_2359, UInt<1>(0h0))
when _T_2362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2359, UInt<1>(0h1), "") : assert_189
node _T_2363 = eq(io.in.c.bits.source, source_3)
node _T_2364 = asUInt(reset)
node _T_2365 = eq(_T_2364, UInt<1>(0h0))
when _T_2365 :
node _T_2366 = eq(_T_2363, UInt<1>(0h0))
when _T_2366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2363, UInt<1>(0h1), "") : assert_190
node _T_2367 = eq(io.in.c.bits.address, address_2)
node _T_2368 = asUInt(reset)
node _T_2369 = eq(_T_2368, UInt<1>(0h0))
when _T_2369 :
node _T_2370 = eq(_T_2367, UInt<1>(0h0))
when _T_2370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2367, UInt<1>(0h1), "") : assert_191
node _T_2371 = and(io.in.c.ready, io.in.c.valid)
node _T_2372 = and(_T_2371, c_first)
when _T_2372 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<3>
connect a_set, UInt<3>(0h0)
wire a_set_wo_ready : UInt<3>
connect a_set_wo_ready, UInt<3>(0h0)
wire a_opcodes_set : UInt<12>
connect a_opcodes_set, UInt<12>(0h0)
wire a_sizes_set : UInt<24>
connect a_sizes_set, UInt<24>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2373 = and(io.in.a.valid, a_first_1)
node _T_2374 = and(_T_2373, UInt<1>(0h1))
when _T_2374 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2375 = and(io.in.a.ready, io.in.a.valid)
node _T_2376 = and(_T_2375, a_first_1)
node _T_2377 = and(_T_2376, UInt<1>(0h1))
when _T_2377 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2378 = dshr(inflight, io.in.a.bits.source)
node _T_2379 = bits(_T_2378, 0, 0)
node _T_2380 = eq(_T_2379, UInt<1>(0h0))
node _T_2381 = asUInt(reset)
node _T_2382 = eq(_T_2381, UInt<1>(0h0))
when _T_2382 :
node _T_2383 = eq(_T_2380, UInt<1>(0h0))
when _T_2383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2380, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<3>
connect d_clr, UInt<3>(0h0)
wire d_clr_wo_ready : UInt<3>
connect d_clr_wo_ready, UInt<3>(0h0)
wire d_opcodes_clr : UInt<12>
connect d_opcodes_clr, UInt<12>(0h0)
wire d_sizes_clr : UInt<24>
connect d_sizes_clr, UInt<24>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2384 = and(io.in.d.valid, d_first_1)
node _T_2385 = and(_T_2384, UInt<1>(0h1))
node _T_2386 = eq(d_release_ack, UInt<1>(0h0))
node _T_2387 = and(_T_2385, _T_2386)
when _T_2387 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2388 = and(io.in.d.ready, io.in.d.valid)
node _T_2389 = and(_T_2388, d_first_1)
node _T_2390 = and(_T_2389, UInt<1>(0h1))
node _T_2391 = eq(d_release_ack, UInt<1>(0h0))
node _T_2392 = and(_T_2390, _T_2391)
when _T_2392 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2393 = and(io.in.d.valid, d_first_1)
node _T_2394 = and(_T_2393, UInt<1>(0h1))
node _T_2395 = eq(d_release_ack, UInt<1>(0h0))
node _T_2396 = and(_T_2394, _T_2395)
when _T_2396 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2397 = dshr(inflight, io.in.d.bits.source)
node _T_2398 = bits(_T_2397, 0, 0)
node _T_2399 = or(_T_2398, same_cycle_resp)
node _T_2400 = asUInt(reset)
node _T_2401 = eq(_T_2400, UInt<1>(0h0))
when _T_2401 :
node _T_2402 = eq(_T_2399, UInt<1>(0h0))
when _T_2402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2399, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2403 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2404 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2405 = or(_T_2403, _T_2404)
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_194
node _T_2409 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_195
else :
node _T_2413 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2414 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2415 = or(_T_2413, _T_2414)
node _T_2416 = asUInt(reset)
node _T_2417 = eq(_T_2416, UInt<1>(0h0))
when _T_2417 :
node _T_2418 = eq(_T_2415, UInt<1>(0h0))
when _T_2418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2415, UInt<1>(0h1), "") : assert_196
node _T_2419 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2420 = asUInt(reset)
node _T_2421 = eq(_T_2420, UInt<1>(0h0))
when _T_2421 :
node _T_2422 = eq(_T_2419, UInt<1>(0h0))
when _T_2422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2419, UInt<1>(0h1), "") : assert_197
node _T_2423 = and(io.in.d.valid, d_first_1)
node _T_2424 = and(_T_2423, a_first_1)
node _T_2425 = and(_T_2424, io.in.a.valid)
node _T_2426 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2427 = and(_T_2425, _T_2426)
node _T_2428 = eq(d_release_ack, UInt<1>(0h0))
node _T_2429 = and(_T_2427, _T_2428)
when _T_2429 :
node _T_2430 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2431 = or(_T_2430, io.in.a.ready)
node _T_2432 = asUInt(reset)
node _T_2433 = eq(_T_2432, UInt<1>(0h0))
when _T_2433 :
node _T_2434 = eq(_T_2431, UInt<1>(0h0))
when _T_2434 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2431, UInt<1>(0h1), "") : assert_198
node _T_2435 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2436 = orr(a_set_wo_ready)
node _T_2437 = eq(_T_2436, UInt<1>(0h0))
node _T_2438 = or(_T_2435, _T_2437)
node _T_2439 = asUInt(reset)
node _T_2440 = eq(_T_2439, UInt<1>(0h0))
when _T_2440 :
node _T_2441 = eq(_T_2438, UInt<1>(0h0))
when _T_2441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2438, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_80
node _T_2442 = orr(inflight)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
node _T_2444 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2445 = or(_T_2443, _T_2444)
node _T_2446 = lt(watchdog, plusarg_reader.out)
node _T_2447 = or(_T_2445, _T_2446)
node _T_2448 = asUInt(reset)
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
when _T_2449 :
node _T_2450 = eq(_T_2447, UInt<1>(0h0))
when _T_2450 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2447, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2451 = and(io.in.a.ready, io.in.a.valid)
node _T_2452 = and(io.in.d.ready, io.in.d.valid)
node _T_2453 = or(_T_2451, _T_2452)
when _T_2453 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<3>
connect c_set, UInt<3>(0h0)
wire c_set_wo_ready : UInt<3>
connect c_set_wo_ready, UInt<3>(0h0)
wire c_opcodes_set : UInt<12>
connect c_opcodes_set, UInt<12>(0h0)
wire c_sizes_set : UInt<24>
connect c_sizes_set, UInt<24>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2454 = and(io.in.c.valid, c_first_1)
node _T_2455 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2456 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2457 = and(_T_2455, _T_2456)
node _T_2458 = and(_T_2454, _T_2457)
when _T_2458 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2459 = and(io.in.c.ready, io.in.c.valid)
node _T_2460 = and(_T_2459, c_first_1)
node _T_2461 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2462 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2463 = and(_T_2461, _T_2462)
node _T_2464 = and(_T_2460, _T_2463)
when _T_2464 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2465 = dshr(inflight_1, io.in.c.bits.source)
node _T_2466 = bits(_T_2465, 0, 0)
node _T_2467 = eq(_T_2466, UInt<1>(0h0))
node _T_2468 = asUInt(reset)
node _T_2469 = eq(_T_2468, UInt<1>(0h0))
when _T_2469 :
node _T_2470 = eq(_T_2467, UInt<1>(0h0))
when _T_2470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2467, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<3>
connect d_clr_1, UInt<3>(0h0)
wire d_clr_wo_ready_1 : UInt<3>
connect d_clr_wo_ready_1, UInt<3>(0h0)
wire d_opcodes_clr_1 : UInt<12>
connect d_opcodes_clr_1, UInt<12>(0h0)
wire d_sizes_clr_1 : UInt<24>
connect d_sizes_clr_1, UInt<24>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2471 = and(io.in.d.valid, d_first_2)
node _T_2472 = and(_T_2471, UInt<1>(0h1))
node _T_2473 = and(_T_2472, d_release_ack_1)
when _T_2473 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2474 = and(io.in.d.ready, io.in.d.valid)
node _T_2475 = and(_T_2474, d_first_2)
node _T_2476 = and(_T_2475, UInt<1>(0h1))
node _T_2477 = and(_T_2476, d_release_ack_1)
when _T_2477 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2478 = and(io.in.d.valid, d_first_2)
node _T_2479 = and(_T_2478, UInt<1>(0h1))
node _T_2480 = and(_T_2479, d_release_ack_1)
when _T_2480 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2481 = dshr(inflight_1, io.in.d.bits.source)
node _T_2482 = bits(_T_2481, 0, 0)
node _T_2483 = or(_T_2482, same_cycle_resp_1)
node _T_2484 = asUInt(reset)
node _T_2485 = eq(_T_2484, UInt<1>(0h0))
when _T_2485 :
node _T_2486 = eq(_T_2483, UInt<1>(0h0))
when _T_2486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2483, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2487 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2488 = asUInt(reset)
node _T_2489 = eq(_T_2488, UInt<1>(0h0))
when _T_2489 :
node _T_2490 = eq(_T_2487, UInt<1>(0h0))
when _T_2490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2487, UInt<1>(0h1), "") : assert_203
else :
node _T_2491 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2492 = asUInt(reset)
node _T_2493 = eq(_T_2492, UInt<1>(0h0))
when _T_2493 :
node _T_2494 = eq(_T_2491, UInt<1>(0h0))
when _T_2494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2491, UInt<1>(0h1), "") : assert_204
node _T_2495 = and(io.in.d.valid, d_first_2)
node _T_2496 = and(_T_2495, c_first_1)
node _T_2497 = and(_T_2496, io.in.c.valid)
node _T_2498 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2499 = and(_T_2497, _T_2498)
node _T_2500 = and(_T_2499, d_release_ack_1)
node _T_2501 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2502 = and(_T_2500, _T_2501)
when _T_2502 :
node _T_2503 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2504 = or(_T_2503, io.in.c.ready)
node _T_2505 = asUInt(reset)
node _T_2506 = eq(_T_2505, UInt<1>(0h0))
when _T_2506 :
node _T_2507 = eq(_T_2504, UInt<1>(0h0))
when _T_2507 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2504, UInt<1>(0h1), "") : assert_205
node _T_2508 = orr(c_set_wo_ready)
when _T_2508 :
node _T_2509 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2510 = asUInt(reset)
node _T_2511 = eq(_T_2510, UInt<1>(0h0))
when _T_2511 :
node _T_2512 = eq(_T_2509, UInt<1>(0h0))
when _T_2512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2509, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_81
node _T_2513 = orr(inflight_1)
node _T_2514 = eq(_T_2513, UInt<1>(0h0))
node _T_2515 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2516 = or(_T_2514, _T_2515)
node _T_2517 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2518 = or(_T_2516, _T_2517)
node _T_2519 = asUInt(reset)
node _T_2520 = eq(_T_2519, UInt<1>(0h0))
when _T_2520 :
node _T_2521 = eq(_T_2518, UInt<1>(0h0))
when _T_2521 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2518, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2522 = and(io.in.c.ready, io.in.c.valid)
node _T_2523 = and(io.in.d.ready, io.in.d.valid)
node _T_2524 = or(_T_2522, _T_2523)
when _T_2524 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2525 = and(io.in.d.ready, io.in.d.valid)
node _T_2526 = and(_T_2525, d_first_3)
node _T_2527 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2528 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2529 = eq(_T_2528, UInt<1>(0h0))
node _T_2530 = and(_T_2527, _T_2529)
node _T_2531 = and(_T_2526, _T_2530)
when _T_2531 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2532 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2533 = bits(_T_2532, 0, 0)
node _T_2534 = eq(_T_2533, UInt<1>(0h0))
node _T_2535 = asUInt(reset)
node _T_2536 = eq(_T_2535, UInt<1>(0h0))
when _T_2536 :
node _T_2537 = eq(_T_2534, UInt<1>(0h0))
when _T_2537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2534, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2538 = and(io.in.e.ready, io.in.e.valid)
node _T_2539 = and(_T_2538, UInt<1>(0h1))
node _T_2540 = and(_T_2539, UInt<1>(0h1))
when _T_2540 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2541 = or(d_set, inflight_2)
node _T_2542 = dshr(_T_2541, io.in.e.bits.sink)
node _T_2543 = bits(_T_2542, 0, 0)
node _T_2544 = asUInt(reset)
node _T_2545 = eq(_T_2544, UInt<1>(0h0))
when _T_2545 :
node _T_2546 = eq(_T_2543, UInt<1>(0h0))
when _T_2546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2543, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_82 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_83 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_40( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire _legal_source_T_3 = 1'h0; // @[Mux.scala:30:73]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = io_in_a_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _source_ok_T_2 = io_in_a_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2 = _source_ok_T_2; // @[Parameters.scala:1138:31]
wire _source_ok_T_3 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_3 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_4 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_4; // @[Parameters.scala:1138:31]
wire _source_ok_T_5 = io_in_d_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_d_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_2 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_7 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _legal_source_T = io_in_b_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _legal_source_T_1 = io_in_b_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _legal_source_T_2 = io_in_b_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71]
assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71]
assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = _legal_source_T_2; // @[Parameters.scala:1138:31]
wire _legal_source_T_4 = _legal_source_WIRE_1; // @[Mux.scala:30:73]
wire _legal_source_T_6 = _legal_source_T_4; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_5 = {_legal_source_WIRE_2, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _legal_source_T_7 = {1'h0, _legal_source_T_6} | _legal_source_T_5; // @[Mux.scala:30:73]
wire [1:0] _legal_source_WIRE_1_0 = _legal_source_T_7; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire _source_ok_T_8 = io_in_c_bits_source_0 == 2'h0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_8; // @[Parameters.scala:1138:31]
wire _source_ok_T_9 = io_in_c_bits_source_0 == 2'h1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_1 = _source_ok_T_9; // @[Parameters.scala:1138:31]
wire _source_ok_T_10 = io_in_c_bits_source_0 == 2'h2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_2 = _source_ok_T_10; // @[Parameters.scala:1138:31]
wire _source_ok_T_11 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_11 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire _T_2451 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2451; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2451; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [1:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2525; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2525; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [1:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg [1:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2522 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2522; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2522; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [1:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [2:0] inflight; // @[Monitor.scala:614:27]
reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [23:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [2:0] a_set; // @[Monitor.scala:626:34]
wire [2:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [11:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [23:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [4:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69]
wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101]
wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69]
wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {4'h0, _a_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65]
wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99]
wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67]
wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99]
wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [23:0] _a_size_lookup_T_6 = {16'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [23:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [3:0] _GEN_21 = 4'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35]
wire [3:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2377 = _T_2451 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2377 ? _a_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2377 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2377 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2377 ? _a_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2377 ? _a_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [2:0] d_clr; // @[Monitor.scala:664:34]
wire [2:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [11:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [23:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46]
wire _T_2423 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [3:0] _GEN_23 = 4'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2423 & ~d_release_ack ? _d_clr_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2392 = _T_2525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2392 ? _d_clr_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2392 ? _d_opcodes_clr_T_5[11:0] : 12'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2392 ? _d_sizes_clr_T_5[23:0] : 24'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [2:0] inflight_1; // @[Monitor.scala:726:35]
reg [11:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [2:0] c_set; // @[Monitor.scala:738:34]
wire [2:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [11:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [23:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [11:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {4'h0, _c_opcode_lookup_T_1 & 12'hF}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [23:0] _c_size_lookup_T_6 = {16'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [23:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [3:0] _GEN_24 = 4'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [3:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35]
wire [3:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2464 = _T_2522 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2464 ? _c_set_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2464 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2464 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [4:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [34:0] _c_opcodes_set_T_1 = {31'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2464 ? _c_opcodes_set_T_1[11:0] : 12'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [4:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [35:0] _c_sizes_set_T_1 = {31'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2464 ? _c_sizes_set_T_1[23:0] : 24'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [2:0] d_clr_1; // @[Monitor.scala:774:34]
wire [2:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [11:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [23:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2495 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2495 & d_release_ack_1 ? _d_clr_wo_ready_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire _T_2477 = _T_2525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2477 ? _d_clr_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2477 ? _d_opcodes_clr_T_11[11:0] : 12'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2477 ? _d_sizes_clr_T_11[23:0] : 24'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [11:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [11:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2531 = _T_2525 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35]
assign d_set = _T_2531 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2540 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35]
assign e_clr = _T_2540 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_58 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 12, 0)
node _source_ok_T = shr(io.in.a.bits.source, 13)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<13>(0h100f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits = bits(_uncommonBits_T, 12, 0)
node _T_4 = shr(io.in.a.bits.source, 13)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<13>(0h100f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 12, 0)
node _T_24 = shr(io.in.a.bits.source, 13)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<13>(0h100f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 12, 0)
node _T_86 = shr(io.in.a.bits.source, 13)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<13>(0h100f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 12, 0)
node _T_152 = shr(io.in.a.bits.source, 13)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<13>(0h100f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 12, 0)
node _T_199 = shr(io.in.a.bits.source, 13)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<13>(0h100f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 12, 0)
node _T_240 = shr(io.in.a.bits.source, 13)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<13>(0h100f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 12, 0)
node _T_283 = shr(io.in.a.bits.source, 13)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<13>(0h100f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 12, 0)
node _T_321 = shr(io.in.a.bits.source, 13)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<13>(0h100f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<13>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 12, 0)
node _T_359 = shr(io.in.a.bits.source, 13)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<13>(0h100f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<13>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 12, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 13)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<13>(0h100f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<12>(0h0)
connect _WIRE.bits.source, UInt<13>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<12>(0h0)
connect _WIRE_2.bits.source, UInt<13>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<4112>, clock, reset, UInt<4112>(0h0)
regreset inflight_opcodes : UInt<16448>, clock, reset, UInt<16448>(0h0)
regreset inflight_sizes : UInt<16448>, clock, reset, UInt<16448>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<4112>
connect a_set, UInt<4112>(0h0)
wire a_set_wo_ready : UInt<4112>
connect a_set_wo_ready, UInt<4112>(0h0)
wire a_opcodes_set : UInt<16448>
connect a_opcodes_set, UInt<16448>(0h0)
wire a_sizes_set : UInt<16448>
connect a_sizes_set, UInt<16448>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<4112>
connect d_clr, UInt<4112>(0h0)
wire d_clr_wo_ready : UInt<4112>
connect d_clr_wo_ready, UInt<4112>(0h0)
wire d_opcodes_clr : UInt<16448>
connect d_opcodes_clr, UInt<16448>(0h0)
wire d_sizes_clr : UInt<16448>
connect d_sizes_clr, UInt<16448>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_118
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<4112>, clock, reset, UInt<4112>(0h0)
regreset inflight_opcodes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0)
regreset inflight_sizes_1 : UInt<16448>, clock, reset, UInt<16448>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<12>(0h0)
connect _c_first_WIRE.bits.source, UInt<13>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<4112>
connect c_set, UInt<4112>(0h0)
wire c_set_wo_ready : UInt<4112>
connect c_set_wo_ready, UInt<4112>(0h0)
wire c_opcodes_set : UInt<16448>
connect c_opcodes_set, UInt<16448>(0h0)
wire c_sizes_set : UInt<16448>
connect c_sizes_set, UInt<16448>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<12>(0h0)
connect _WIRE_6.bits.source, UInt<13>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<12>(0h0)
connect _WIRE_8.bits.source, UInt<13>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<12>(0h0)
connect _WIRE_10.bits.source, UInt<13>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<12>(0h0)
connect _WIRE_12.bits.source, UInt<13>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<12>(0h0)
connect _WIRE_14.bits.source, UInt<13>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<4112>
connect d_clr_1, UInt<4112>(0h0)
wire d_clr_wo_ready_1 : UInt<4112>
connect d_clr_wo_ready_1, UInt<4112>(0h0)
wire d_opcodes_clr_1 : UInt<16448>
connect d_opcodes_clr_1, UInt<16448>(0h0)
wire d_sizes_clr_1 : UInt<16448>
connect d_sizes_clr_1, UInt<16448>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<12>(0h0)
connect _WIRE_16.bits.source, UInt<13>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<12>(0h0)
connect _WIRE_18.bits.source, UInt<13>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<12>(0h0)
connect _WIRE_20.bits.source, UInt<13>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<12>(0h0)
connect _WIRE_22.bits.source, UInt<13>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_119
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:15)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<12>(0h0)
connect _WIRE_24.bits.source, UInt<13>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_58( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74]
wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52]
wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79]
wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77]
wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35]
wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35]
wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34]
wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34]
wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34]
wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [12:0] source; // @[Monitor.scala:390:22]
reg [11:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [12:0] source_1; // @[Monitor.scala:541:22]
reg [4111:0] inflight; // @[Monitor.scala:614:27]
reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [4111:0] a_set; // @[Monitor.scala:626:34]
wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [8191:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [4111:0] d_clr; // @[Monitor.scala:664:34]
wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [4111:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [16447:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [16447:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [4111:0] inflight_1; // @[Monitor.scala:726:35]
wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [4111:0] d_clr_1; // @[Monitor.scala:774:34]
wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35]
wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113]
wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_69 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_80
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_69( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_80 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e11_s53_1 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e11_s53_1( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_50 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_50
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_50( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_50 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.